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80 lines
2.7 KiB
80 lines
2.7 KiB
3 years ago
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from adder import *
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from alu_controller import *
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from alu import *
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from binandint import *
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from branch_unit import *
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from data_mem import *
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from forwarding_unit import *
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from hazard_detector import *
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from Imm_gen import *
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from insn_mem import *
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from mux import *
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from mux4 import *
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from proc_controller import *
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from reg_file import reg_file
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3 years ago
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IM = insn_mem()
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PC = 0
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def IF(BrPC, Brflush, stall, PC, IM):
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PCplus4 = adder(PC, 4)
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if Brflush == '1':
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nPC = BrPC
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3 years ago
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else:
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3 years ago
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nPC = PC + 4
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insn = IM.fetch(nPC)
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return nPC, insn
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REG = reg_file()
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def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
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funct7 = insn[0:7]
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rs2 = BintoUInt(insn[7:12])
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rs1 = BintoUInt(insn[12:17])
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funct3 = insn[17:20]
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rd = BintoUInt(insn[20:25])
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opcode = insn[25:32]
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ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
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opcode)
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ImmG = Imm_gen(insn)
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REG.write(RegWrite, rd, WB_data)
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RD1, RD2 = REG.read(rs1, rs2)
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return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7
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def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
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RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7, lastrs1,
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lastrs2, forwardA, forwardB, WB_data, alu_out):
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stall = hazard_detector(lastrs1, lastrs2, rd, MemRead)
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tempA = mux4(RD1, alu_out, WB_data, 0, forwardA)
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tempB = mux4(RD2, alu_out, WB_data, 0, forwardB)
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tempB2 = mux(tempB, ImmG, ALUSrc)
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alu_ctrl = alu_controller(ALUOp, funct7, funct3)
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ALU_result = alu(tempA, tempB2, alu_ctrl)
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pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
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PC, ImmG, JalrSel, Branch, ALU_result)
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return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7
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MEMORY = data_mem()
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def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
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pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
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data_out = MEMORY(MemWrite, MemRead, ALU_result, tempB, funct3)
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return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd
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def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
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ex_mem_rd, mem_wb_rd, ex_mem_rs1, ex_mem_rs2, ex_mem_regwrite,
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mem_wb_regwrite):
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mem_out = mux(data_out, tempB, MemtoReg)
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WB_data = mux4(mem_out, pc_plus_4, pc_plus_imm, 0, RWSel)
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forward_a, forward_b = fowardingunit(ex_mem_rs1, ex_mem_rs2, ex_mem_rd,
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mem_wb_rd, ex_mem_regwrite,
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mem_wb_regwrite)
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return WB_data, RegWrite, forward_a, forward_b
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