master
郑几方 3 years ago
parent d00492399c
commit 198f73ceaf

@ -18,7 +18,6 @@ PC = 0
def IF(BrPC, Brflush, stall, PC, IM):
PCplus4 = adder(PC, 4)
if Brflush == '1':
nPC = BrPC
else:
@ -39,7 +38,7 @@ def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
opcode = insn[25:32]
ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
opcode)
ImmG = Imm_gen(insn)
ImmG = BintoInt(Imm_gen(insn))
REG.write(RegWrite, rd, WB_data)
RD1, RD2 = REG.read(rs1, rs2)
return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7
@ -56,7 +55,7 @@ def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
ALU_result = alu(tempA, tempB2, alu_ctrl)
pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
PC, ImmG, JalrSel, Branch, ALU_result)
return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7
return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7, stall
MEMORY = data_mem()
@ -64,7 +63,7 @@ MEMORY = data_mem()
def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
data_out = MEMORY(MemWrite, MemRead, ALU_result, tempB, funct3)
data_out = MEMORY.mem(MemWrite, MemRead, ALU_result, tempB, funct3)
return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd
@ -77,3 +76,133 @@ def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
mem_wb_rd, ex_mem_regwrite,
mem_wb_regwrite)
return WB_data, RegWrite, forward_a, forward_b
def dataPath():
MemtoRegD = '0'
RegWriteD = '0'
RWSelD = '0' * 2
pc_plus_immD = 0
pc_plus_4D = 0
data_outD = 0
tempBD = 0
rdD = 0
rdC = 0
rs1B = 0
rs2B = 0
RegWriteC = '0'
MemtoRegC = '0'
MemWriteC = '0'
RWSelC = '0' * 2
MemReadC = '0'
pc_plus_immC = 0
pc_plus_4C = 0
ALU_resultC = 0
tempAC = 0
tempBC = 0
funct3C = '0' * 3
funct7C = '0' * 7
ALUSrcB = '0'
MemtoRegB = '0'
RegWriteB = '0'
MemReadB = '0'
MemWriteB = '0'
ALUOpB = '0' * 2
BranchB = '0'
JalrSelB = '0'
RWSelB = '0' * 2
PCB = 0
RD1B = 0
RD2B = 0
ImmGB = 0
rdB = 0
funct3B = '0' * 3
funct7B = '0' * 7
insnA = '0' * 32
ALU_resultB = 0
PCA = 0
while True:
WB_dataD, RegWriteD, forward_a, forward_b = WB(
MemtoRegD,
RegWriteD,
RWSelD,
pc_plus_immD,
pc_plus_4D,
data_outD,
tempBD,
ex_mem_rd=rdC,
mem_wb_rd=rdD,
ex_mem_rs1=rs1B,
ex_mem_rs2=rs2B,
ex_mem_regwrite=RegWriteC,
mem_wb_regwrite=RegWriteD)
MemtoRegC, RegWriteC, RWSelC, pc_plus_immC, pc_plus_4C, data_outC, tempBC, rdC = MEM(
MEMORY, MemtoRegC, RegWriteC, MemWriteC, RWSelC, MemReadC,
pc_plus_immC, pc_plus_4C, ALU_resultC, rs1B, rs2B, rdC, tempAC,
tempBC, funct3C, funct7C)
RegWriteD = RegWriteC
MemtoRegD = MemtoRegC
RWSelD = RWSelC
pc_plus_immD = pc_plus_immC
pc_plus_4D = pc_plus_4C
data_outD = data_outC
rdD = rdC
tempBD = tempBC
MemtoRegB, RegWriteB, MemWriteB, RWSelB, MemReadB, pc_plus_immB, pc_plus_4B, BrPC, Brflush, ALU_resultB, rs1B, rs2B, rdB, tempAB, tempBB, funct3B, funct7B, stall = EX(
ALUSrcB, MemtoRegB, RegWriteB, MemReadB, MemWriteB, ALUOpB,
BranchB, JalrSelB, RWSelB, PCB, RD1B, RD2B, ImmGB, rs1B, rs2B, rdB,
funct3B, funct7B, lastrs1=insnA[12:17], lastrs2=insnA[7:12], forwardA=forward_a, forwardB=forward_b,
WB_data=WB_dataD,
alu_out=ALU_resultB)
RegWriteC = RegWriteB
MemtoRegC = MemtoRegB
MemReadC = MemReadB
MemWriteC = MemWriteB
RWSelC = RWSelB
pc_plus_immC = pc_plus_immB
pc_plus_4C = pc_plus_4B
Imm_OutC = ImmGB
ALU_resultC = ALU_resultB
rdC = rdB
funct3C = funct3B
funct7C = funct7B
tempAC = tempAB
tempBC = tempBB
ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PCA, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7 = ID(
PCA, insnA, RegWriteD, Brflush, stall, REG, WB_dataD)
ALUSrcB = ALUSrc
MemtoRegB = MemtoReg
RegWriteB = RegWritex
MemReadB = MemRead
MemWriteB = MemWrite
ALUOpB = ALUOp
BranchB = Branch
JalrSelB = JalrSel
RWSelB = RWSel
PCB = PCA
RD1B = RD1
RD2B = RD2
rs1B = insnA[12:17]
rs2B = insnA[7:12]
rdB = insnA[20:25]
ImmGB = ImmG
funct3B = insnA[17:20]
funct7B = insnA[0:7]
insnB = insnA
nPC, insn = IF(BrPC, Brflush, stall, PC, IM)
if Brflush == '1':
PCA = 4
insnA = '0' * 32
else:
PCA = nPC
insnA = insn
if insn == 32 * '0':
break

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