From 335efe2268b8156211ea80de0a693e7bdfa9e6ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=83=91=E5=87=A0=E6=96=B9?= Date: Tue, 23 Nov 2021 12:04:50 +0800 Subject: [PATCH] formatted --- code/adder.py | 4 +-- code/alu.py | 14 +++++------ code/binandint.py | 5 ++-- code/branch_unit.py | 10 +++++--- code/data_mem.py | 4 +-- code/insn_mem.py | 6 ++--- code/mux.py | 6 ++--- code/mux4.py | 10 ++++---- code/proc_controller.py | 46 +++++++++++++++++----------------- code/reg_file.py | 2 +- code/top(wating_to_filling).py | 2 +- 11 files changed, 57 insertions(+), 52 deletions(-) diff --git a/code/adder.py b/code/adder.py index fc897af..fd16540 100644 --- a/code/adder.py +++ b/code/adder.py @@ -1,2 +1,2 @@ -def adder(a,b): #返回加法运算结果y - return a+b \ No newline at end of file +def adder(a, b): # 返回加法运算结果y + return a + b diff --git a/code/alu.py b/code/alu.py index e25e92c..3c70730 100644 --- a/code/alu.py +++ b/code/alu.py @@ -38,11 +38,11 @@ def alu(a, b, alu_ctrl): # a,b为两个运算数，alu_ctrl为控制信号， alu_result = 0 elif alu_ctrl == '01001': if a < 0: - ua = a + 2**32 + ua = a + 2 ** 32 else: ua = a if b < 0: - ub = b + 2**32 + ub = b + 2 ** 32 else: ub = b if ua < ub: @@ -51,11 +51,11 @@ def alu(a, b, alu_ctrl): # a,b为两个运算数，alu_ctrl为控制信号， alu_result = 0 elif alu_ctrl == '01010': if a < 0: - ua = a + 2**32 + ua = a + 2 ** 32 else: ua = a if b < 0: - ub = b + 2**32 + ub = b + 2 ** 32 else: ub = b if ua >= ub: @@ -70,11 +70,11 @@ def alu(a, b, alu_ctrl): # a,b为两个运算数，alu_ctrl为控制信号， alu_result = a << b elif alu_ctrl == '01110': if a < 0: - ua = a + 2**32 + ua = a + 2 ** 32 else: ua = a if b < 0: - ub = b + 2**32 + ub = b + 2 ** 32 else: ub = b if ua <= ub: @@ -83,7 +83,7 @@ def alu(a, b, alu_ctrl): # a,b为两个运算数，alu_ctrl为控制信号， alu_result = 0 elif alu_ctrl == '01111': if a < 0: - ua = a + 2**32 + ua = a + 2 ** 32 else: ua = a alu_result = a >> b diff --git a/code/binandint.py b/code/binandint.py index ccbba6a..5e770db 100644 --- a/code/binandint.py +++ b/code/binandint.py @@ -1,7 +1,7 @@ def BintoInt(x): i = int(x, base=2) if x[0] == '1': - i = i - 2**len(x) + i = i - 2 ** len(x) return i @@ -15,9 +15,10 @@ def UInttoBin(x, n): def InttoBin(x, n): if x < 0: - x += 2**n + x += 2 ** n return UInttoBin(x, n) + def unsigned_ext(x, n): return '0' * (n - len(x)) + x diff --git a/code/branch_unit.py b/code/branch_unit.py index 11e0ef1..445476a 100644 --- a/code/branch_unit.py +++ b/code/branch_unit.py @@ -1,10 +1,14 @@ -def branch_unit(cur_pc, imm, jalr_sel, branch_taken, - alu_result): # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型) +from typing import Tuple + + +def branch_unit( + cur_pc: int, imm: int, jalr_sel: int, branch_taken: int, alu_result: int +) -> Tuple[int, int, int, int]: # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型) pc_plus_4 = cur_pc + 4 # 输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看) pc_plus_imm = cur_pc + imm pc_sel = jalr_sel | (branch_taken & (alu_result % 2)) if jalr_sel == 1: - branch_target = alu_result & (2**32 - 2) + branch_target = alu_result & (2 ** 32 - 2) else: branch_target = cur_pc + imm * 2 return pc_plus_imm, pc_plus_4, branch_target, pc_sel diff --git a/code/data_mem.py b/code/data_mem.py index 166b91a..6217511 100644 --- a/code/data_mem.py +++ b/code/data_mem.py @@ -11,9 +11,9 @@ class data_mem: ): # 写使能，读使能，(使能为int的0或1)地址，输入数据，func3 #输出为data_out if write_en: if funct3 == '000': # sb - self.memory[address] = InttoBin(data_in % 2**8, 8) + self.memory[address] = InttoBin(data_in % 2 ** 8, 8) elif funct3 == '001': # sh - temp = InttoBin(data_in % 2**16, 16) + temp = InttoBin(data_in % 2 ** 16, 16) self.memory[address + 1] = temp[0:8] self.memory[address] = temp[8:16] elif funct3 == '010': # sw diff --git a/code/insn_mem.py b/code/insn_mem.py index aa5ec26..edf56d6 100644 --- a/code/insn_mem.py +++ b/code/insn_mem.py @@ -1,10 +1,10 @@ class insn_mem: - memory = [8*'0']*4*1024*16 + memory = [8 * '0'] * 4 * 1024 * 16 def __init__(self) -> None: pass def fetch(self, address): - insn = self.memory[address+3]+self.memory[address+2] + \ - self.memory[address+1]+self.memory[address] + insn = self.memory[address + 3] + self.memory[address + 2] + \ + self.memory[address + 1] + self.memory[address] return insn diff --git a/code/mux.py b/code/mux.py index cf28eb8..2c95814 100644 --- a/code/mux.py +++ b/code/mux.py @@ -1,5 +1,5 @@ -def mux(d0,d1,s): #返回选择结果 - if s=='0': +def mux(d0, d1, s): # 返回选择结果 + if s == '0': return d0 else: - return d1 \ No newline at end of file + return d1 diff --git a/code/mux4.py b/code/mux4.py index d94648f..7b5df7c 100644 --- a/code/mux4.py +++ b/code/mux4.py @@ -1,9 +1,9 @@ -def mux4(d00,d01,d10,d11,s): #返回选择结果 - if s=='00': +def mux4(d00, d01, d10, d11, s): # 返回选择结果 + if s == '00': return d00 - elif s=='01': + elif s == '01': return d01 - elif s=='10': + elif s == '10': return d10 else: - return d11 \ No newline at end of file + return d11 diff --git a/code/proc_controller.py b/code/proc_controller.py index b81151c..2f631a6 100644 --- a/code/proc_controller.py +++ b/code/proc_controller.py @@ -1,25 +1,25 @@ def proc_controller(opcode): - if opcode=='0110011': #(add,and,or,sll,slt,sltu,sra,srl,sub,xor) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','10','0','0','00' - elif opcode=='0110111': #(lui)20位立即数 - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','00','0','0','10' - elif opcode=='1101111': #(jal) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01' - elif opcode=='0010011': #(addi,andi,ori,slli,slti,sltiu,srai,srli,xori) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','0','0','00' - elif opcode=='0000011': #(lb,lbu,lh,lhu,lw) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','1','1','1','0','00','0','0','00' - elif opcode=='1100111': #(jalr) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','1','1','01' - elif opcode=='0100011': #(sb, sh, sw) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','0','0','1','00','0','0','00' - elif opcode=='1100011': #(beq,bge,bgeu,blt,bne,bltu) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','01','1','0','00' - elif opcode=='1101111': #(jal) - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01' -################################# - elif opcode=='0010111': #(auipc)20位立即数 - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','00','1','0','10' + if opcode == '0110011': # (add,and,or,sll,slt,sltu,sra,srl,sub,xor) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '10', '0', '0', '00' + elif opcode == '0110111': # (lui)20位立即数 + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '00', '0', '0', '10' + elif opcode == '1101111': # (jal) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01' + elif opcode == '0010011': # (addi,andi,ori,slli,slti,sltiu,srai,srli,xori) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '0', '0', '00' + elif opcode == '0000011': # (lb,lbu,lh,lhu,lw) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '1', '1', '1', '0', '00', '0', '0', '00' + elif opcode == '1100111': # (jalr) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '1', '1', '01' + elif opcode == '0100011': # (sb, sh, sw) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '0', '0', '1', '00', '0', '0', '00' + elif opcode == '1100011': # (beq,bge,bgeu,blt,bne,bltu) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '01', '1', '0', '00' + elif opcode == '1101111': # (jal) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01' + ################################# + elif opcode == '0010111': # (auipc)20位立即数 + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '00', '1', '0', '10 ' else: - ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','00','0','0','00' - return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel \ No newline at end of file + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '00', '0', '0', '00' + return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel diff --git a/code/reg_file.py b/code/reg_file.py index 88ddedf..1a7b72b 100644 --- a/code/reg_file.py +++ b/code/reg_file.py @@ -1,5 +1,5 @@ class reg_file: - regs = [0]*32 + regs = [0] * 32 def __init__(self) -> None: pass diff --git a/code/top(wating_to_filling).py b/code/top(wating_to_filling).py index c0fc773..3445c37 100644 --- a/code/top(wating_to_filling).py +++ b/code/top(wating_to_filling).py @@ -1,4 +1,4 @@ from datapath import * if __name__ == '__main__': - dataPath() \ No newline at end of file + dataPath()