From 468beb8bf8a67d550030d96f28a1d38566099838 Mon Sep 17 00:00:00 2001 From: unknown <1975697725@qq.com> Date: Mon, 22 Nov 2021 16:57:04 +0800 Subject: [PATCH] code --- code/Imm_gen.py | 23 ++++++++++++++++++++ code/adder.py | 2 ++ code/alu.py | 36 +++++++++++++++++++++++++++++++ code/alu_controller.py | 48 +++++++++++++++++++++++++++++++++++++++++ code/binandint.py | 19 ++++++++++++++++ code/branch_unit.py | 9 ++++++++ code/data_mem.py | 26 ++++++++++++++++++++++ code/forwarding_unit.py | 14 ++++++++++++ code/hazard_detector.py | 6 ++++++ code/insn_mem.py | 5 +++++ code/mux.py | 5 +++++ code/mux4.py | 9 ++++++++ code/proc_controller.py | 25 +++++++++++++++++++++ 13 files changed, 227 insertions(+) create mode 100644 code/Imm_gen.py create mode 100644 code/adder.py create mode 100644 code/alu.py create mode 100644 code/alu_controller.py create mode 100644 code/binandint.py create mode 100644 code/branch_unit.py create mode 100644 code/data_mem.py create mode 100644 code/forwarding_unit.py create mode 100644 code/hazard_detector.py create mode 100644 code/insn_mem.py create mode 100644 code/mux.py create mode 100644 code/mux4.py create mode 100644 code/proc_controller.py diff --git a/code/Imm_gen.py b/code/Imm_gen.py new file mode 100644 index 0000000..e211483 --- /dev/null +++ b/code/Imm_gen.py @@ -0,0 +1,23 @@ +def Imm_gen(inst_code): + test=inst_code[25:32] + if test=='0010011': + imm_out=20*inst_code[0]+inst_code[0:12] + elif test=='0000011': + pass + elif test=='0100011': + pass + elif test=='1100011': + pass + elif test=='1101111': + pass + elif test=='1100111': + pass + elif test=='0110111': + pass +def imm_gen(inst_code,imm_out): + test=inst_code[25:32] + if test=="0010011": + imm_out=inst_code[0]*20+inst_code[0:12] + else: + imm_out='0'*32 + return imm_out \ No newline at end of file diff --git a/code/adder.py b/code/adder.py new file mode 100644 index 0000000..fc897af --- /dev/null +++ b/code/adder.py @@ -0,0 +1,2 @@ +def adder(a,b): #返回加法运算结果y + return a+b \ No newline at end of file diff --git a/code/alu.py b/code/alu.py new file mode 100644 index 0000000..6bdf879 --- /dev/null +++ b/code/alu.py @@ -0,0 +1,36 @@ +import binandint +def alu(a,b,alu_ctrl): #a,b为两个运算数，alu_ctrl为控制信号，返回运算结果result与是否为0 zero + if alu_ctrl=='00000': + pass + elif alu_ctrl=='00001': + pass + elif alu_ctrl=='00010': + pass + elif alu_ctrl=='00011': + pass + elif alu_ctrl=='00100': + pass + elif alu_ctrl=='00101': + pass + elif alu_ctrl=='00110': + pass + elif alu_ctrl=='00111': + pass + elif alu_ctrl=='01000': + pass + elif alu_ctrl=='01001': + pass + elif alu_ctrl=='01010': + pass + elif alu_ctrl=='01011': + pass + elif alu_ctrl=='01100': + pass + elif alu_ctrl=='01101': + pass + elif alu_ctrl=='01110': + pass + elif alu_ctrl=='01111': + pass + else: + pass \ No newline at end of file diff --git a/code/alu_controller.py b/code/alu_controller.py new file mode 100644 index 0000000..a36bc80 --- /dev/null +++ b/code/alu_controller.py @@ -0,0 +1,48 @@ +def alu_controller(alu_op,funct7,funct3): #alu_op来自主控制器，funct7和funct3来自指令的特定部位 返回alu_ctrl + if alu_op=='00': + opreation='00000' #lw.sw.auipc + elif alu_op=='01': + if funct3=='000': + opreation='00101' #beq + elif funct3=='001': + opreation='00110' #bne + elif funct3=='100': + opreation='00111' #blt + elif funct3=='101': + opreation='01000' #bge + elif funct3=='110': + opreation='01001' #bltu + elif funct3=='111': + opreation='01010' #bgeu + else: + opreation='00000' + elif alu_op=='10': + if funct3=='000': + if funct7=='0100000': #sub + opreation='00001' + else: #add,addi + opreation='00000' + elif funct3=='100': + opreation='01100' #xor,xori + elif funct3=='110': + opreation='00010' #or,ori + elif funct3=='111': + opreation='00011' #and, andi + elif funct3=='010': + opreation='00100' #slt,slti + elif funct3=='001': + opreation='01101' #sll,slli 未存在 + elif funct3=='011': + opreation='01110' #sliu,sltiu 未存在 + elif funct3=='101': + if funct7=='0100000': #sra,srai + opreation='01111' + else: #srl,srli + opreation='10000' + else: + opreation='00000' + elif alu_op=='11': #jal + opreation='01011' + else: + opreation='00000' + return opreation diff --git a/code/binandint.py b/code/binandint.py new file mode 100644 index 0000000..389cce0 --- /dev/null +++ b/code/binandint.py @@ -0,0 +1,19 @@ +def BintoInt(x): + i = int(x, base=2) + if x[0] == '1': + i = i - 2**len(x) + return i + + +def BintoUInt(x): + return int(x, base=2) + + +def UInttoBin(x, n): + return '0' * (n - len(bin(x)[2:])) + bin(x)[2:] + + +def InttoBin(x, n): + if x < 0: + x += 2**n + return UInttoBin(x, n) \ No newline at end of file diff --git a/code/branch_unit.py b/code/branch_unit.py new file mode 100644 index 0000000..baf20fb --- /dev/null +++ b/code/branch_unit.py @@ -0,0 +1,9 @@ +def branch_unit(cur_pc,imm,jalr_sel,branch_taken,alu_result): #输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型) + pc_plus_4=cur_pc+4 #输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看) + pc_plus_imm=cur_pc+imm + pc_sel = jalr_sel | (branch_taken & (alu_result%2)) + if jalr_sel==1: + branch_target=alu_result&(2**32-2) + else: + branch_target=cur_pc+imm*2 + return pc_plus_imm,pc_plus_4,branch_target,pc_sel \ No newline at end of file diff --git a/code/data_mem.py b/code/data_mem.py new file mode 100644 index 0000000..2846be7 --- /dev/null +++ b/code/data_mem.py @@ -0,0 +1,26 @@ +class data_mem: + memory=[8*'0']*4*1024*16 + def mem(self,write_en,read_en,address,data_in,funct3): #写使能，读使能，(使能为int的0或1)地址，输入数据，func3 #输出为data_out + if write_en: + if funct3=='000': + pass + elif funct3=='001': + pass + elif funct3=='010': + pass + else: + pass + + if read_en: + if funct3=='000': + pass + elif funct3=='001': + pass + elif funct3=='010': + pass + elif funct3=='100': + pass + elif funct3=='101': + pass + else: + pass diff --git a/code/forwarding_unit.py b/code/forwarding_unit.py new file mode 100644 index 0000000..b673390 --- /dev/null +++ b/code/forwarding_unit.py @@ -0,0 +1,14 @@ +def fowardingunit(rs1,rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite): + if rs1!=0 and rs1==ex_mem_rd and ex_mem_regwrite: + forward_a='01' + elif rs1!=0 and rs1==mem_wb_rd and mem_wb_regwrite: + forward_a='10' + else: + forward_a='00' + if rs2!=0 and rs2==ex_mem_rd and ex_mem_regwrite: + forward_b='01' + elif rs2!=0 and rs2==mem_wb_rd and mem_wb_regwrite: + forward_b='10' + else: + forward_b='00' + return forward_a,forward_b diff --git a/code/hazard_detector.py b/code/hazard_detector.py new file mode 100644 index 0000000..167110c --- /dev/null +++ b/code/hazard_detector.py @@ -0,0 +1,6 @@ +def hazard_detector(if_id_rs1,if_id_rs2,id_ex_rd,id_ex_memread): + if id_ex_memread and (id_ex_rd==if_id_rs1 or id_ex_rd==if_id_rs2): + stall=1 + else: + stall=0 + return stall \ No newline at end of file diff --git a/code/insn_mem.py b/code/insn_mem.py new file mode 100644 index 0000000..5f17c02 --- /dev/null +++ b/code/insn_mem.py @@ -0,0 +1,5 @@ +class insn_mem: + memory=[8*'0']*4*1024*16 + def fetch(self,address): + insn=self.memory[address] + return insn \ No newline at end of file diff --git a/code/mux.py b/code/mux.py new file mode 100644 index 0000000..cf28eb8 --- /dev/null +++ b/code/mux.py @@ -0,0 +1,5 @@ +def mux(d0,d1,s): #返回选择结果 + if s=='0': + return d0 + else: + return d1 \ No newline at end of file diff --git a/code/mux4.py b/code/mux4.py new file mode 100644 index 0000000..d94648f --- /dev/null +++ b/code/mux4.py @@ -0,0 +1,9 @@ +def mux4(d00,d01,d10,d11,s): #返回选择结果 + if s=='00': + return d00 + elif s=='01': + return d01 + elif s=='10': + return d10 + else: + return d11 \ No newline at end of file diff --git a/code/proc_controller.py b/code/proc_controller.py new file mode 100644 index 0000000..832426b --- /dev/null +++ b/code/proc_controller.py @@ -0,0 +1,25 @@ +def proc_controller(opcode): + if opcode=='0110011': #(add,and,or,sll,slt,sltu,sra,srl,sub,xor) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','10','0','0','00' + elif opcode=='0110111': #(lui)20位立即数 + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','00','0','0','10' + elif opcode=='1101111': #(jal) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01' + elif opcode=='0010011': #(addi,andi,ori,slli,slti,sltiu,srai,srli,xori) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','0','0','00' + elif opcode=='0000011': #(lb,lbu,lh,lhu,lw) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','1','1','1','0','00','0','0','00' + elif opcode=='1100111': #(jalr) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','1','1','01' + elif opcode=='0100011': #(sb, sh, sw) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','0','0','1','00','0','0','00' + elif opcode=='1100011': #(beq,bge,bgeu,blt,bne,bltu) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','01','1','0','00' + elif opcode=='1101111': #(jal) + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01' +################################# + elif opcode=='0010111': #(auipc)20位立即数 + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','00','1','0','11' + else: + ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','00','0','0','00' + return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel \ No newline at end of file