from adder import *
from alu_controller import *
from alu import *
from binandint import *
from branch_unit import *
from data_mem import *
from forwarding_unit import *
from hazard_detector import *
from Imm_gen import *
from insn_mem import *
from mux import *
from mux4 import *
from proc_controller import *
from reg_file import reg_file
from elftools.elf.elffile import ELFFile

IM = insn_mem()
PC = 0


def IF(BrPC, Brflush, stall, PC, IM):
    if Brflush == 1:
        nPC = BrPC
    else:
        nPC = PC + 4
    insn = IM.fetch(nPC)
    return nPC, insn


REG = reg_file()


def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
    funct7 = insn[0:7]
    rs2 = BintoUInt(insn[7:12])
    rs1 = BintoUInt(insn[12:17])
    funct3 = insn[17:20]
    rd = BintoUInt(insn[20:25])
    opcode = insn[25:32]
    ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
        opcode)
    ImmG = BintoInt(Imm_gen(insn))
    REG.write(RegWrite, rd, WB_data)
    RD1, RD2 = REG.read(rs1, rs2)
    return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7


def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
       RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7, lastrs1,
       lastrs2, forwardA, forwardB, WB_data, alu_out):
    stall = hazard_detector(lastrs1, lastrs2, rd, MemRead)
    tempA = mux4(RD1, alu_out, WB_data, 0, forwardA)
    tempB = mux4(RD2, alu_out, WB_data, 0, forwardB)
    tempB2 = mux(tempB, ImmG, ALUSrc)
    alu_ctrl = alu_controller(ALUOp, funct7, funct3)
    ALU_result = alu(tempA, tempB2, alu_ctrl)
    pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
        PC, ImmG, JalrSel, Branch, ALU_result)
    return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7, stall


MEMORY = data_mem()


def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
        pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
    data_out = MEMORY.mem(MemWrite, MemRead, ALU_result, tempB, funct3)
    return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd


def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
       ex_mem_rd, mem_wb_rd, ex_mem_rs1, ex_mem_rs2, ex_mem_regwrite,
       mem_wb_regwrite):
    mem_out = mux(data_out, tempB, MemtoReg)
    WB_data = mux4(mem_out, pc_plus_4, pc_plus_imm, 0, RWSel)
    forward_a, forward_b = fowardingunit(ex_mem_rs1, ex_mem_rs2, ex_mem_rd,
                                         mem_wb_rd, ex_mem_regwrite,
                                         mem_wb_regwrite)
    return WB_data, RegWrite, forward_a, forward_b


def dataPath():
    MemtoRegD = '0'
    RegWriteD = '0'
    RWSelD = '0' * 2
    pc_plus_immD = 0
    pc_plus_4D = 0
    data_outD = 0
    tempBD = 0
    rdD = 0
    rdC = 0
    rs1B = 0
    rs2B = 0
    RegWriteC = '0'
    MemtoRegC = '0'
    MemWriteC = '0'
    RWSelC = '0' * 2
    MemReadC = '0'
    pc_plus_immC = 0
    pc_plus_4C = 0
    ALU_resultC = 0
    tempAC = 0
    tempBC = 0
    funct3C = '0' * 3
    funct7C = '0' * 7
    ALUSrcB = '0'
    MemtoRegB = '0'
    RegWriteB = '0'
    MemReadB = '0'
    MemWriteB = '0'
    ALUOpB = '0' * 2
    BranchB = '0'
    JalrSelB = '0'
    RWSelB = '0' * 2
    PCB = 0
    RD1B = 0
    RD2B = 0
    ImmGB = 0
    rdB = 0
    funct3B = '0' * 3
    funct7B = '0' * 7
    insnA = '0' * 32
    ALU_resultB = 0
    PCA = 0
    nPC = 0

    imaddr = 4
    testfile = open('outFileBinary.txt', 'r')
    line = ''
    with open('arch-fib', 'rb') as f:
        e = ELFFile(f)
        code = e.get_section_by_name('.text')
        nextc = e.get_section_by_name('.rodata')
        ops = code.data()
        addr = code['sh_addr']
        nextaddr = nextc['sh_addr']
        for pos in range(0, nextaddr - addr, 4):
            s = ''
            for i in range(3, -1, -1):
                s += (8 - len(bin(ops[pos + i])[2:])) * '0' + bin(
                    ops[pos + i])[2:]
            line = testfile.readline()[:-1]
            if s != line:
                print('fault in line ' + str(int(pos / 4 + 1)))
            IM.memory[imaddr + 3], IM.memory[imaddr + 2], IM.memory[
                imaddr +
                1], IM.memory[imaddr] = s[:8], s[8:16], s[16:24], s[24:]
            imaddr += 4

    while True:
        WB_dataD, RegWriteD, forward_a, forward_b = WB(
            MemtoRegD,
            RegWriteD,
            RWSelD,
            pc_plus_immD,
            pc_plus_4D,
            data_outD,
            tempBD,
            ex_mem_rd=rdC,
            mem_wb_rd=rdD,
            ex_mem_rs1=rs1B,
            ex_mem_rs2=rs2B,
            ex_mem_regwrite=RegWriteC,
            mem_wb_regwrite=RegWriteD)

        MemtoRegC, RegWriteC, RWSelC, pc_plus_immC, pc_plus_4C, data_outC, tempBC, rdC = MEM(
            MEMORY, MemtoRegC, RegWriteC, MemWriteC, RWSelC, MemReadC,
            pc_plus_immC, pc_plus_4C, ALU_resultC, rs1B, rs2B, rdC, tempAC,
            tempBC, funct3C, funct7C)

        RegWriteD = RegWriteC
        MemtoRegD = MemtoRegC
        RWSelD = RWSelC
        pc_plus_immD = pc_plus_immC
        pc_plus_4D = pc_plus_4C
        data_outD = data_outC
        rdD = rdC
        tempBD = tempBC

        MemtoRegB, RegWriteB, MemWriteB, RWSelB, MemReadB, pc_plus_immB, pc_plus_4B, BrPC, Brflush, ALU_resultB, rs1B, rs2B, rdB, tempAB, tempBB, funct3B, funct7B, stall = EX(
            ALUSrcB,
            MemtoRegB,
            RegWriteB,
            MemReadB,
            MemWriteB,
            ALUOpB,
            BranchB,
            JalrSelB,
            RWSelB,
            PCB,
            RD1B,
            RD2B,
            ImmGB,
            rs1B,
            rs2B,
            rdB,
            funct3B,
            funct7B,
            lastrs1=insnA[12:17],
            lastrs2=insnA[7:12],
            forwardA=forward_a,
            forwardB=forward_b,
            WB_data=WB_dataD,
            alu_out=ALU_resultB)

        RegWriteC = RegWriteB
        MemtoRegC = MemtoRegB
        MemReadC = MemReadB
        MemWriteC = MemWriteB
        RWSelC = RWSelB
        pc_plus_immC = pc_plus_immB
        pc_plus_4C = pc_plus_4B
        Imm_OutC = ImmGB
        ALU_resultC = ALU_resultB
        rdC = rdB
        funct3C = funct3B
        funct7C = funct7B
        tempAC = tempAB
        tempBC = tempBB

        ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PCA, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7 = ID(
            PCA, insnA, RegWriteD, Brflush, stall, REG, WB_dataD)

        ALUSrcB = ALUSrc
        MemtoRegB = MemtoReg
        RegWriteB = RegWritex
        MemReadB = MemRead
        MemWriteB = MemWrite
        ALUOpB = ALUOp
        BranchB = Branch
        JalrSelB = JalrSel
        RWSelB = RWSel
        PCB = PCA
        RD1B = RD1
        RD2B = RD2
        rs1B = BintoUInt(insnA[12:17])
        rs2B = BintoUInt(insnA[7:12])
        rdB = BintoUInt(insnA[20:25])
        ImmGB = ImmG
        funct3B = insnA[17:20]
        funct7B = insnA[0:7]
        insnB = insnA

        nPC, insn = IF(BrPC, Brflush, stall, nPC, IM)

        if Brflush == '1':
            PCA = 4
            insnA = '0' * 32
        else:
            PCA = nPC
            insnA = insn

        if insn == 32 * '0':
            break