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39 lines
1.9 KiB
39 lines
1.9 KiB
`timescale 1ns / 1ps
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// 数据存储器
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module datamemory#(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 32
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)(
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input logic clock,
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input logic read_en,
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input logic write_en,
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input logic [ADDR_WIDTH -1 : 0] address, // read/write address
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input logic [DATA_WIDTH -1 : 0] data_in, // write Data
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input logic [2:0] funct3, // insn[14:12]
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output logic [DATA_WIDTH -1 : 0] data_out // read data
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);
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logic [DATA_WIDTH - 1 : 0] MEM[(2**(ADDR_WIDTH - 2)) - 1 : 0];
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always @(posedge clock)
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if (write_en) // sw etc.
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case (funct3)
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3'b000: MEM[address[ADDR_WIDTH - 1 : 2]][7:0] <= data_in; // sb
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3'b001: MEM[address[ADDR_WIDTH - 1 : 2]][15:0] <= data_in; // sh
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3'b010: MEM[address[ADDR_WIDTH - 1 : 2]] <= data_in; // sw
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default: MEM[address[ADDR_WIDTH - 1 : 2]] <= data_in; // 默认sw
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endcase
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always_comb
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if (read_en) // lw etc.
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case (funct3)
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3'b000: data_out = {{24{MEM[address[ADDR_WIDTH - 1 : 2]][7]}}, MEM[address[ADDR_WIDTH - 1 : 2]][7:0]}; // lb
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3'b001: data_out = {{16{MEM[address[ADDR_WIDTH - 1 : 2]][15]}}, MEM[address[ADDR_WIDTH - 1 : 2]][15:0]}; // lh
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3'b010: data_out = MEM[address[ADDR_WIDTH - 1 : 2]]; // lw
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3'b100: data_out = {24'b0,MEM[address[ADDR_WIDTH - 1 : 2]][7:0]}; // lbu
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3'b101: data_out = {16'b0,MEM[address[ADDR_WIDTH - 1 : 2]][15:0]}; // lhu
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default: data_out = MEM[address[ADDR_WIDTH - 1 : 2]]; // 默认lw
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endcase
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endmodule
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