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`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: flipflop
// Description: An edge-triggered register
// When reset is `1`, the value of the register is set to 0.
// 当reset被置为1时，
// Otherwise:
// 否则
// - if stall is set, the register preserves its original data
// - else, it is updated by `d`.
// 如果stall被置为1， ， ，
//////////////////////////////////////////////////////////////////////////////////
// 边沿触发寄存器
module flipflop # (
parameter WIDTH = 8
) (
input logic clock ,
input logic reset ,
input logic [ WIDTH - 1 : 0 ] d ,
input logic stall ,
output logic [ WIDTH - 1 : 0 ] q
) ;
always_ff @ ( posedge clock , posedge reset )
begin
if ( reset )
q < = 0 ;
else if ( ! stall )
q < = d ;
end
endmodule
