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55 lines
1.8 KiB
55 lines
1.8 KiB
`timescale 1ns / 1ps
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// 寄存器文件
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module Reg_file #(
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parameter DATA_WIDTH = 32, // number of bits in each register
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parameter ADDRESS_WIDTH = 5, //number of registers = 2^ADDRESS_WIDTH
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parameter NUM_REGS = 2 ** ADDRESS_WIDTH
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)(
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// Inputs
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input clock, //clock
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input reset, //synchronous reset; reset all regs to 0 upon assertion.
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input write_en, //write enable
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input [ADDRESS_WIDTH-1:0] write_addr, //address of the register that supposed to written into
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input [DATA_WIDTH-1:0] data_in, // data that supposed to be written into the register file
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input [ADDRESS_WIDTH-1:0] read_addr1, //first address to be read from
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input [ADDRESS_WIDTH-1:0] read_addr2, //second address to be read from
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// Outputs
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output logic [DATA_WIDTH-1:0] data_out1, //content of reg_file[read_addr1] is loaded into
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output logic [DATA_WIDTH-1:0] data_out2 //content of reg_file[read_addr2] is loaded into
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);
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integer i;
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logic [DATA_WIDTH-1:0] register_file [NUM_REGS-1:0];
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integer log_file;
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initial begin
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log_file = $fopen("./reg_trace.txt", "w");
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if (log_file)
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$display("***************************** File was opened succussfully: %s", "./test.txt");
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else
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$display("***************************** Failed to open the file: %s", "./test.txt");
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end
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always @( negedge clock )
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begin
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if( reset == 1'b1 )
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for (i = 0; i < NUM_REGS ; i = i + 1) begin
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register_file [i] <= 0;
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$fwrite(log_file, "r%d, 0", i);
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end
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else if( reset ==1'b0 && write_en ==1'b1 && write_addr != 0) begin
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register_file [ write_addr ] <= data_in;
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$fwrite(log_file, "r%02x, %08x\n", write_addr, data_in);
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end
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end
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assign data_out1 = register_file[read_addr1];
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assign data_out2 = register_file[read_addr2];
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endmodule
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