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255 lines
7.3 KiB
255 lines
7.3 KiB
from adder import *
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from alu_controller import *
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from alu import *
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from binandint import *
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from branch_unit import *
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from data_mem import *
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from forwarding_unit import *
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from hazard_detector import *
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from Imm_gen import *
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from insn_mem import *
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from mux import *
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from mux4 import *
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from proc_controller import *
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from reg_file import reg_file
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from elftools.elf.elffile import ELFFile
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IM = insn_mem()
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PC = 0
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def IF(BrPC, Brflush, stall, PC, IM):
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if Brflush == 1:
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nPC = BrPC
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else:
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nPC = PC + 4
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insn = IM.fetch(nPC)
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return nPC, insn
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REG = reg_file()
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def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
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funct7 = insn[0:7]
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rs2 = BintoUInt(insn[7:12])
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rs1 = BintoUInt(insn[12:17])
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funct3 = insn[17:20]
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rd = BintoUInt(insn[20:25])
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opcode = insn[25:32]
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ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
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opcode)
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ImmG = BintoInt(Imm_gen(insn))
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REG.write(RegWrite, rd, WB_data)
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RD1, RD2 = REG.read(rs1, rs2)
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return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7
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def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
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RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7, lastrs1,
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lastrs2, forwardA, forwardB, WB_data, alu_out):
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stall = hazard_detector(lastrs1, lastrs2, rd, MemRead)
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tempA = mux4(RD1, alu_out, WB_data, 0, forwardA)
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tempB = mux4(RD2, alu_out, WB_data, 0, forwardB)
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tempB2 = mux(tempB, ImmG, ALUSrc)
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alu_ctrl = alu_controller(ALUOp, funct7, funct3)
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ALU_result = alu(tempA, tempB2, alu_ctrl)
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pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
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PC, ImmG, JalrSel, Branch, ALU_result)
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return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7, stall
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MEMORY = data_mem()
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def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
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pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
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data_out = MEMORY.mem(MemWrite, MemRead, ALU_result, tempB, funct3)
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return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd
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def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
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ex_mem_rd, mem_wb_rd, ex_mem_rs1, ex_mem_rs2, ex_mem_regwrite,
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mem_wb_regwrite):
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mem_out = mux(data_out, tempB, MemtoReg)
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WB_data = mux4(mem_out, pc_plus_4, pc_plus_imm, 0, RWSel)
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forward_a, forward_b = fowardingunit(ex_mem_rs1, ex_mem_rs2, ex_mem_rd,
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mem_wb_rd, ex_mem_regwrite,
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mem_wb_regwrite)
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return WB_data, RegWrite, forward_a, forward_b
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def dataPath():
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MemtoRegD = '0'
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RegWriteD = '0'
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RWSelD = '0' * 2
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pc_plus_immD = 0
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pc_plus_4D = 0
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data_outD = 0
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tempBD = 0
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rdD = 0
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rdC = 0
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rs1B = 0
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rs2B = 0
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RegWriteC = '0'
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MemtoRegC = '0'
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MemWriteC = '0'
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RWSelC = '0' * 2
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MemReadC = '0'
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pc_plus_immC = 0
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pc_plus_4C = 0
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ALU_resultC = 0
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tempAC = 0
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tempBC = 0
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funct3C = '0' * 3
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funct7C = '0' * 7
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ALUSrcB = '0'
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MemtoRegB = '0'
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RegWriteB = '0'
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MemReadB = '0'
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MemWriteB = '0'
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ALUOpB = '0' * 2
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BranchB = '0'
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JalrSelB = '0'
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RWSelB = '0' * 2
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PCB = 0
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RD1B = 0
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RD2B = 0
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ImmGB = 0
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rdB = 0
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funct3B = '0' * 3
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funct7B = '0' * 7
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insnA = '0' * 32
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ALU_resultB = 0
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PCA = 0
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nPC = 0
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imaddr = 4
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testfile = open('outFileBinary.txt', 'r')
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line = ''
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with open('arch-fib', 'rb') as f:
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e = ELFFile(f)
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code = e.get_section_by_name('.text')
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nextc = e.get_section_by_name('.rodata')
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ops = code.data()
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addr = code['sh_addr']
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nextaddr = nextc['sh_addr']
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for pos in range(0, nextaddr - addr, 4):
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s = ''
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for i in range(3, -1, -1):
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s += (8 - len(bin(ops[pos + i])[2:])) * '0' + bin(
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ops[pos + i])[2:]
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line = testfile.readline()[:-1]
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if s != line:
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print('fault in line ' + str(int(pos / 4 + 1)))
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IM.memory[imaddr + 3], IM.memory[imaddr + 2], IM.memory[
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imaddr +
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1], IM.memory[imaddr] = s[:8], s[8:16], s[16:24], s[24:]
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imaddr += 4
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while True:
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WB_dataD, RegWriteD, forward_a, forward_b = WB(
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MemtoRegD,
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RegWriteD,
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RWSelD,
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pc_plus_immD,
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pc_plus_4D,
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data_outD,
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tempBD,
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ex_mem_rd=rdC,
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mem_wb_rd=rdD,
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ex_mem_rs1=rs1B,
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ex_mem_rs2=rs2B,
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ex_mem_regwrite=RegWriteC,
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mem_wb_regwrite=RegWriteD)
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MemtoRegC, RegWriteC, RWSelC, pc_plus_immC, pc_plus_4C, data_outC, tempBC, rdC = MEM(
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MEMORY, MemtoRegC, RegWriteC, MemWriteC, RWSelC, MemReadC,
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pc_plus_immC, pc_plus_4C, ALU_resultC, rs1B, rs2B, rdC, tempAC,
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tempBC, funct3C, funct7C)
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RegWriteD = RegWriteC
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MemtoRegD = MemtoRegC
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RWSelD = RWSelC
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pc_plus_immD = pc_plus_immC
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pc_plus_4D = pc_plus_4C
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data_outD = data_outC
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rdD = rdC
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tempBD = tempBC
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MemtoRegB, RegWriteB, MemWriteB, RWSelB, MemReadB, pc_plus_immB, pc_plus_4B, BrPC, Brflush, ALU_resultB, rs1B, rs2B, rdB, tempAB, tempBB, funct3B, funct7B, stall = EX(
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ALUSrcB,
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MemtoRegB,
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RegWriteB,
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MemReadB,
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MemWriteB,
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ALUOpB,
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BranchB,
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JalrSelB,
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RWSelB,
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PCB,
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RD1B,
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RD2B,
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ImmGB,
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rs1B,
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rs2B,
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rdB,
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funct3B,
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funct7B,
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lastrs1=insnA[12:17],
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lastrs2=insnA[7:12],
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forwardA=forward_a,
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forwardB=forward_b,
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WB_data=WB_dataD,
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alu_out=ALU_resultB)
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RegWriteC = RegWriteB
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MemtoRegC = MemtoRegB
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MemReadC = MemReadB
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MemWriteC = MemWriteB
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RWSelC = RWSelB
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pc_plus_immC = pc_plus_immB
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pc_plus_4C = pc_plus_4B
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Imm_OutC = ImmGB
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ALU_resultC = ALU_resultB
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rdC = rdB
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funct3C = funct3B
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funct7C = funct7B
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tempAC = tempAB
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tempBC = tempBB
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ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PCA, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7 = ID(
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PCA, insnA, RegWriteD, Brflush, stall, REG, WB_dataD)
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ALUSrcB = ALUSrc
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MemtoRegB = MemtoReg
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RegWriteB = RegWritex
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MemReadB = MemRead
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MemWriteB = MemWrite
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ALUOpB = ALUOp
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BranchB = Branch
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JalrSelB = JalrSel
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RWSelB = RWSel
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PCB = PCA
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RD1B = RD1
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RD2B = RD2
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rs1B = BintoUInt(insnA[12:17])
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rs2B = BintoUInt(insnA[7:12])
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rdB = BintoUInt(insnA[20:25])
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ImmGB = ImmG
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funct3B = insnA[17:20]
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funct7B = insnA[0:7]
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insnB = insnA
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nPC, insn = IF(BrPC, Brflush, stall, nPC, IM)
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if Brflush == '1':
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PCA = 4
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insnA = '0' * 32
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else:
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PCA = nPC
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insnA = insn
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if insn == 32 * '0':
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break
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