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`timescale 1ns / 1ps
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// 二端口多路选择器
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module mux2 #(
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parameter WIDTH = 32
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)(
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y
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);
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assign y = s ? d1 : d0;
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endmodule
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