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150 lines
3.5 KiB
150 lines
3.5 KiB
from architecture import *
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#执行一个周期
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def run(arch):
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arch1 = Architecture()
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for i in range(INSTR_MEM_SIZE):
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arch1.mem[INSTR_MEM_OFF + i] = arch.mem[INSTR_MEM_OFF + i]
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arch1.clk = arch.clk + 1
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arch1.reg[PC_REG_OFF] = runPC(arch)
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'''
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for i in range(INT_REG_SIZE):
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arch1.reg[INT_REG_OFF + i] = runIntReg(arch, i)
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for i in range(FP_REG_SIZE):
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arch1.reg[FP_REG_OFF + i] = runFpReg(arch, i)
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for i in range(DATA_MEM_SIZE):
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arch1.mem[DATA_MEM_OFF + i] = runMem(arch, i)
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arch1.fu[INT_FU_OFF] = runIntFU(arch)
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arch1.fu[ADD_FU_OFF] = runAddFU(arch)
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arch1.fu[MUL_FU_OFF] = runMulFU(arch)
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arch1.fu[MEM_FU_OFF] = runMemFU(arch)
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arch1.rs[INT_RS_OFF] = runIntRS(arch)
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for i in range(ADD_RS_SIZE):
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arch1.rs[ADD_RS_OFF + i] = runAddRS(arch, i)
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for i in range(MUL_RS_SIZE):
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arch1.rs[MUL_RS_OFF + i] = runMulRS(arch, i)
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for i in range(MEM_RS_SIZE):
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arch1.rs[MEM_RS_OFF + i] = runMemRS(arch, i)
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for i in range(BUF_REG_SIZE):
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arch1.reg[BUF_REG_OFF + i] = runBufReg(arch, i)
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arch1.bus = runBus(arch)
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'''
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return arch1
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def runPC(arch):
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pc = Register()
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if issue(arch):
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pc.val = arch.reg[PC_REG_OFF].val + 1
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instr = fetch(arch)
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if instr.op == 'jump':
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pc.src = INT_RS_OFF
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else:
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pc.src = arch.reg[PC_REG_OFF].src
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elif arch.reg[PC_REG_OFF].src and not arch.fu[INT_FU_OFF].clk:
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pc.val = arch.fu[INT_FU_OFF].res
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pc.src = 0
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else:
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pc.val = arch.reg[PC_REG_OFF].val
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pc.src = arch.reg[PC_REG_OFF].src
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return pc
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def runIntReg(arch, i):
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reg = Register()
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fuOff = writeReg(arch, INT_REG_OFF + i)
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if fuOff:
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reg.val = arch.fu[fuOff].res
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else:
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reg.val = arch.reg[INT_REG_OFF + i].val
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rsOff = issue(arch)
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if rsOff:
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instr = fetch(arch)
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if instr.op == 'addi':
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#TODO
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def runFpReg(arch, i):
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pass
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def runMem(arch, i):
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pass
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def runIntFU(arch):
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pass
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def runAddFU(arch):
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pass
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def runMulFU(arch):
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pass
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def runMemFU(arch):
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pass
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def runIntRS(arch):
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pass
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def runAddRS(arch, i):
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pass
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def runMulRS(arch, i):
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pass
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def runMemRS(arch, i):
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pass
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def runBufReg(arch, i):
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pass
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def runBus(arch, i):
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pass
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def issue(arch):
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if not arch.reg[PC_REG_OFF].src:
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instr = fetch(arch)
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if instr:
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rsMap = {
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'addi': (INT_RS_OFF, INT_RS_SIZE),
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'jump': (INT_RS_OFF, INT_RS_SIZE),
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'fadd': (ADD_RS_OFF, ADD_RS_SIZE),
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'fmul': (MUL_RS_OFF, MUL_RS_SIZE),
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'load': (MEM_RS_OFF, MEM_RS_SIZE),
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'store': (MEM_RS_OFF, MEM_RS_SIZE)
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}
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offset, size = rsMap[instr.op]
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return first(arch, offset, size):
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return 0
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def fetch(arch):
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return arch.mem[INSTR_MEM_OFF + arch.reg[PC_REG_OFF].val]
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def first(arch, offset, size):
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for i in range(size):
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if not arch.rs[offset + i].busy:
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return offset + i
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return 0
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def writeReg(arch, i):
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src = arch.reg[i].src
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if src == INT_RS_OFF:
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return INT_FU_OFF
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elif src >= ADD_RS_OFF and src < ADD_RS_OFF + ADD_RS_SIZE:
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return ADD_FU_OFF
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elif src >= MUL_RS_OFF and src < MUL_RS_OFF + MUL_RS_SIZE:
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return MUL_FU_OFF
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elif src >= MEM_RS_OFF and src < MEM_RS_OFF + MEM_RS_SIZE:
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return MEM_FU_OFF
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else:
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return 0
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