; ModuleID = 'infeasable.ll'
source_filename = "infeasable.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: noinline nounwind optnone uwtable
define dso_local i32 @main() #0 {
entry:
  call void @__DSE_Init__()
  %retval = alloca i32, align 4
  %x = alloca i32, align 4
  call void @__DSE_Alloca__(i32 0, i32* %x)
  %c = alloca i32, align 4
  call void @__DSE_Alloca__(i32 1, i32* %c)
  %y = alloca i32, align 4
  call void @__DSE_Alloca__(i32 2, i32* %y)
  %i = alloca i32, align 4
  call void @__DSE_Alloca__(i32 3, i32* %i)
  store i32 0, i32* %retval, align 4
  call void @__DSE_Const__(i32 0)
  call void @__DSE_Store__(i32* %retval)
  call void @__DSE_Input__(i32* noundef %x, i32 noundef 0)
  store i32 34571, i32* %c, align 4
  call void @__DSE_Const__(i32 34571)
  call void @__DSE_Store__(i32* %c)
  store i32 1, i32* %y, align 4
  call void @__DSE_Const__(i32 1)
  call void @__DSE_Store__(i32* %y)
  store i32 0, i32* %i, align 4
  call void @__DSE_Const__(i32 0)
  call void @__DSE_Store__(i32* %i)
  br label %for.cond

for.cond:                                         ; preds = %for.inc, %entry
  %0 = load i32, i32* %i, align 4
  call void @__DSE_Load__(i32 4, i32* %i)
  %1 = load i32, i32* %x, align 4
  call void @__DSE_Load__(i32 5, i32* %x)
  %cmp = icmp slt i32 %0, %1
  call void @__DSE_Register__(i32 5)
  call void @__DSE_Register__(i32 4)
  call void @__DSE_ICmp__(i32 6, i32 40)
  call void @__DSE_Label__(i32 6, i32 7, i32 1)
  call void @__DSE_Label__(i32 6, i32 8, i32 0)
  br i1 %cmp, label %for.body, label %for.end

for.body:                                         ; preds = %for.cond
  %2 = load i32, i32* %y, align 4
  call void @__DSE_Load__(i32 9, i32* %y)
  %mul = mul nsw i32 %2, 2
  call void @__DSE_Const__(i32 2)
  call void @__DSE_Register__(i32 9)
  call void @__DSE_BinOp__(i32 10, i32 17)
  store i32 %mul, i32* %y, align 4
  call void @__DSE_Register__(i32 10)
  call void @__DSE_Store__(i32* %y)
  br label %for.inc

for.inc:                                          ; preds = %for.body
  %3 = load i32, i32* %i, align 4
  call void @__DSE_Load__(i32 11, i32* %i)
  %inc = add nsw i32 %3, 1
  call void @__DSE_Const__(i32 1)
  call void @__DSE_Register__(i32 11)
  call void @__DSE_BinOp__(i32 12, i32 13)
  store i32 %inc, i32* %i, align 4
  call void @__DSE_Register__(i32 12)
  call void @__DSE_Store__(i32* %i)
  br label %for.cond, !llvm.loop !4

for.end:                                          ; preds = %for.cond
  %4 = load i32, i32* %y, align 4
  call void @__DSE_Load__(i32 13, i32* %y)
  %5 = load i32, i32* %c, align 4
  call void @__DSE_Load__(i32 14, i32* %c)
  %rem = srem i32 %4, %5
  %cmp1 = icmp eq i32 %rem, 17
  call void @__DSE_Const__(i32 17)
  call void @__DSE_Register__(i32 16)
  call void @__DSE_ICmp__(i32 15, i32 32)
  call void @__DSE_Label__(i32 15, i32 17, i32 1)
  call void @__DSE_Label__(i32 15, i32 18, i32 0)
  br i1 %cmp1, label %if.then, label %if.end

if.then:                                          ; preds = %for.end
  call void @__DSE_Branch__(i32 17, i32 2)
  %6 = load i32, i32* %x, align 4
  call void @__DSE_Load__(i32 19, i32* %x)
  %7 = load i32, i32* %c, align 4
  call void @__DSE_Load__(i32 20, i32* %c)
  %8 = load i32, i32* %c, align 4
  call void @__DSE_Load__(i32 21, i32* %c)
  %sub = sub nsw i32 %7, %8
  call void @__DSE_Register__(i32 21)
  call void @__DSE_Register__(i32 20)
  call void @__DSE_BinOp__(i32 22, i32 15)
  %div = sdiv i32 %6, %sub
  call void @__DSE_Register__(i32 22)
  call void @__DSE_Register__(i32 19)
  call void @__DSE_BinOp__(i32 23, i32 20)
  store i32 %div, i32* %x, align 4
  call void @__DSE_Register__(i32 23)
  call void @__DSE_Store__(i32* %x)
  br label %if.end

if.end:                                           ; preds = %if.then, %for.end
  call void @__DSE_Branch__(i32 18, i32 3)
  ret i32 0
}

declare dso_local void @__DSE_Input__(i32* noundef, i32 noundef) #1

declare void @__DSE_Init__()

declare void @__DSE_Alloca__(i32, i32*)

declare void @__DSE_Store__(i32*)

declare void @__DSE_Load__(i32, i32*)

declare void @__DSE_ICmp__(i32, i32)

declare void @__DSE_Label__(i32, i32, i32)

declare void @__DSE_Branch__(i32, i32)

declare void @__DSE_BinOp__(i32, i32)

declare void @__DSE_Const__(i32)

declare void @__DSE_Register__(i32)

attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"uwtable", i32 1}
!2 = !{i32 7, !"frame-pointer", i32 2}
!3 = !{!"clang version 14.0.0"}
!4 = distinct !{!4, !5}
!5 = !{!"llvm.loop.mustprogress"}