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#include "mir/MIR.h"
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#include <ostream>
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#include <stdexcept>
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#include <set>
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#include "utils/Log.h"
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//#define DEBUG_Asm
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#ifdef DEBUG_Asm
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#include <iostream>
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#define DEBUG_MSG(msg) std::cerr << "[Asm Debug] " << msg << std::endl
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#else
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#define DEBUG_MSG(msg)
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#endif
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namespace mir {
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namespace {
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static void PrintLoadImm64(std::ostream& os, PhysReg reg, uint64_t imm);
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const FrameSlot& GetFrameSlot(const MachineFunction& function,
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const Operand& operand) {
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if (operand.GetKind() != Operand::Kind::FrameIndex) {
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throw std::runtime_error(FormatError("mir", "期望 FrameIndex 操作数"));
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}
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return function.GetFrameSlot(operand.GetFrameIndex());
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}
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void PrintStackAccess(std::ostream& os, const char* insn, PhysReg reg, int64_t offset) {
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// offset 通常是负数，例如 -8, -24, -40 等
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if (offset >= -256 && offset <= 255) {
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os << " " << insn << " " << PhysRegName(reg) << ", [x29, #" << offset << "]\n";
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return;
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}
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// 大偏移量：用 x16 计算 x29 + offset，然后间接访问
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os << " mov x16, x29\n";
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int64_t abs_offset = (offset >= 0) ? offset : -offset;
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if (abs_offset <= 4095) {
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if (offset >= 0) {
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os << " add x16, x16, #" << offset << "\n";
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} else {
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os << " sub x16, x16, #" << abs_offset << "\n";
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}
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} else {
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// 分解大偏移量
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PrintLoadImm64(os, PhysReg::X17, abs_offset);
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if (offset >= 0) {
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os << " add x16, x16, x17\n";
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} else {
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os << " sub x16, x16, x17\n";
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}
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}
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os << " " << insn << " " << PhysRegName(reg) << ", [x16]\n";
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}
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// 打印单个操作数
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void PrintOperand(std::ostream& os, const Operand& op) {
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switch (op.GetKind()) {
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case Operand::Kind::Reg:
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os << PhysRegName(op.GetReg());
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break;
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case Operand::Kind::VReg:
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throw std::runtime_error(
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FormatError("asm", "寄存器分配未完成: 存在虚拟寄存器 #" +
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std::to_string(op.GetVReg())));
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case Operand::Kind::Imm:
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os << "#" << op.GetImm();
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break;
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case Operand::Kind::FrameIndex:
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os << "[sp, #" << op.GetFrameIndex() << "]";
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break;
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case Operand::Kind::Cond:
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os << CondCodeName(op.GetCondCode());
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break;
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case Operand::Kind::Label:
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DEBUG_MSG("label is" << op.GetLabel());
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os << op.GetLabel();
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break;
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}
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}
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// 判断立即数是否可作为 AArch64 ADD/SUB 指令的 12 位立即数（可左移 0 或 12 位）
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static bool IsLegalAddSubImm(int64_t imm) {
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if (imm < 0) imm = -imm; // 取绝对值，因为移位规则对称
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if (imm <= 4095) return true; // 0-4095 直接合法
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if ((imm & 0xFFF) == 0 && imm <= 4095 * 4096) return true; // 4096 的倍数且 ≤ 16773120
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return false;
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}
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// ---- 寄存器宽度规范化 ----
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static bool IsWReg(PhysReg reg) {
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return reg >= PhysReg::W0 && reg <= PhysReg::W30;
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}
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static bool IsXReg(PhysReg reg) {
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return reg >= PhysReg::X0 && reg <= PhysReg::X30;
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}
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static bool IsSReg(PhysReg reg) {
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return reg >= PhysReg::S0 && reg <= PhysReg::S31;
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}
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// Xn → Wn, Wn → Wn, Sn → Sn
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static PhysReg ToW(PhysReg reg) {
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if (IsXReg(reg))
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return static_cast<PhysReg>(
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static_cast<int>(reg) - static_cast<int>(PhysReg::X0) + static_cast<int>(PhysReg::W0));
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return reg;
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}
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// Wn → Xn, Xn → Xn, Sn → Sn
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static PhysReg ToX(PhysReg reg) {
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if (IsWReg(reg))
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return static_cast<PhysReg>(
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static_cast<int>(reg) - static_cast<int>(PhysReg::W0) + static_cast<int>(PhysReg::X0));
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return reg;
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}
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// 检查一组操作数是否全是同一宽度（W/X/S）
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static bool AllSameRegWidth(const std::vector<Operand>& ops) {
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int kind = -1;
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for (const auto& op : ops) {
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if (op.GetKind() != Operand::Kind::Reg) continue;
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PhysReg r = op.GetReg();
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if (IsWReg(r)) { if (kind == -1) kind = 0; else if (kind != 0) return false; }
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else if (IsXReg(r)) { if (kind == -1) kind = 1; else if (kind != 1) return false; }
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else if (IsSReg(r)) { if (kind == -1) kind = 2; else if (kind != 2) return false; }
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}
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return true;
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}
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// 根据目的地宽度规范化所有寄存器操作数
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static void NormalizeRegOps(std::vector<Operand>& ops, PhysReg dst) {
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PhysReg base = dst;
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bool wantW = IsWReg(base);
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bool wantX = IsXReg(base);
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for (auto& op : ops) {
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if (op.GetKind() != Operand::Kind::Reg) continue;
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if (wantW) op = Operand::Reg(ToW(op.GetReg()));
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else if (wantX) op = Operand::Reg(ToX(op.GetReg()));
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}
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}
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// 在匿名命名空间添加辅助函数
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static void PrintLoadImm64(std::ostream& os, PhysReg reg, uint64_t imm) {
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// 输出 movz + movk 序列
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uint16_t part0 = imm & 0xFFFF;
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uint16_t part1 = (imm >> 16) & 0xFFFF;
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uint16_t part2 = (imm >> 32) & 0xFFFF;
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uint16_t part3 = (imm >> 48) & 0xFFFF;
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os << " movz " << PhysRegName(reg) << ", #" << part0;
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if (part1 != 0 || part2 != 0 || part3 != 0) {
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os << ", lsl #0";
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}
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os << "\n";
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if (part1 != 0) {
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os << " movk " << PhysRegName(reg) << ", #" << part1 << ", lsl #16\n";
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}
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if (part2 != 0) {
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os << " movk " << PhysRegName(reg) << ", #" << part2 << ", lsl #32\n";
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}
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if (part3 != 0) {
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os << " movk " << PhysRegName(reg) << ", #" << part3 << ", lsl #48\n";
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}
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}
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// 打印单条指令
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void PrintInstruction(std::ostream& os, const MachineInstr& instr,
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const MachineFunction& function) {
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const auto& ops = instr.GetOperands();
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switch (instr.GetOpcode()) {
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case Opcode::Prologue:
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os << " stp x29, x30, [sp, #-16]!\n";
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os << " mov x29, sp\n";
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if (function.GetFrameSize() > 0) {
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int64_t size = function.GetFrameSize();
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if (IsLegalAddSubImm(size)) {
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os << " sub sp, sp, #" << size << "\n";
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} else {
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PrintLoadImm64(os, PhysReg::X16, size);
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os << " sub sp, sp, x16\n";
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}
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}
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break;
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case Opcode::Epilogue:
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if (function.GetFrameSize() > 0) {
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int64_t size = function.GetFrameSize();
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if (IsLegalAddSubImm(size)) {
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os << " add sp, sp, #" << size << "\n";
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} else {
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PrintLoadImm64(os, PhysReg::X16, size);
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os << " add sp, sp, x16\n";
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}
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}
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os << " ldp x29, x30, [sp], #16\n";
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break;
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case Opcode::MovImm:
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os << " mov " << PhysRegName(ops.at(0).GetReg()) << ", #"
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<< ops.at(1).GetImm() << "\n";
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break;
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case Opcode::MovReg:{
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PhysReg dst = ops.at(0).GetReg();
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PhysReg src = ops.at(1).GetReg();
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if (IsSReg(dst) || IsSReg(src)) {
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// 涉及 S 寄存器的 move：使用 fmov
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if (!IsSReg(dst)) dst = ToW(dst); // 确保是 W 寄存器
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if (!IsSReg(src)) src = ToW(src);
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os << " fmov " << PhysRegName(dst) << ", " << PhysRegName(src) << "\n";
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} else {
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// GPR move：规范化宽度
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if (IsWReg(dst) && IsXReg(src)) {
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src = ToW(src);
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} else if (IsXReg(dst) && IsWReg(src)) {
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src = ToX(src);
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}
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os << " mov " << PhysRegName(dst) << ", " << PhysRegName(src) << "\n";
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}
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break;
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}
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case Opcode::StoreStack: {
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if (ops.size() >= 2 && ops.at(1).GetKind() == Operand::Kind::FrameIndex) {
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const auto& slot = GetFrameSlot(function, ops.at(1));
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PrintStackAccess(os, "stur", ops.at(0).GetReg(), slot.offset);
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} else if (ops.size() >= 2 && ops.at(1).GetKind() == Operand::Kind::Reg) {
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// 间接存储：基址必须是 X 寄存器
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PhysReg base = ToX(ops.at(1).GetReg());
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os << " str " << PhysRegName(ops.at(0).GetReg()) << ", ["
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<< PhysRegName(base) << "]\n";
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} else {
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throw std::runtime_error("StoreStack: 无效的操作数类型");
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}
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break;
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}
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case Opcode::LoadStack: {
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if (ops.size() >= 2 && ops.at(1).GetKind() == Operand::Kind::FrameIndex) {
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const auto& slot = GetFrameSlot(function, ops.at(1));
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PrintStackAccess(os, "ldur", ops.at(0).GetReg(), slot.offset);
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} else if (ops.size() >= 2 && ops.at(1).GetKind() == Operand::Kind::Reg) {
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// 间接加载：基址必须是 X 寄存器
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PhysReg base = ToX(ops.at(1).GetReg());
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os << " ldr " << PhysRegName(ops.at(0).GetReg()) << ", ["
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<< PhysRegName(base) << "]\n";
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} else {
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throw std::runtime_error("LoadStack: 无效的操作数类型");
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}
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break;
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}
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case Opcode::StoreStackPair:
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// stp x29, x30, [sp, #-16]!
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os << " stp " << PhysRegName(ops.at(0).GetReg()) << ", "
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<< PhysRegName(ops.at(1).GetReg()) << ", [sp";
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if (ops.size() > 2 && ops.at(2).GetKind() == Operand::Kind::Imm) {
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int offset = ops.at(2).GetImm();
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os << ", #" << offset;
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}
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os << "]!\n"; // 注意添加 ! 表示 pre-index
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break;
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case Opcode::LoadStackPair:
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// ldp x29, x30, [sp], #16
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os << " ldp " << PhysRegName(ops.at(0).GetReg()) << ", "
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<< PhysRegName(ops.at(1).GetReg()) << ", [sp]";
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if (ops.size() > 2 && ops.at(2).GetKind() == Operand::Kind::Imm) {
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int offset = ops.at(2).GetImm();
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os << ", #" << offset;
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}
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os << "\n";
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break;
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case Opcode::AddRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " add " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::AddRI: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " add " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", #"
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<< nops[2].GetImm() << "\n";
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break;
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}
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case Opcode::SubRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " sub " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::SubRI: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " sub " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", #"
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<< nops[2].GetImm() << "\n";
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break;
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}
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case Opcode::MulRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " mul " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::SDivRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " sdiv " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::UDivRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " udiv " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::FAddRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " fadd " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::FSubRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " fsub " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::FMulRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " fmul " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::FDivRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " fdiv " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << ", "
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<< PhysRegName(nops[2].GetReg()) << "\n";
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break;
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}
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case Opcode::CmpRR: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " cmp " << PhysRegName(nops[0].GetReg()) << ", "
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<< PhysRegName(nops[1].GetReg()) << "\n";
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break;
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}
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case Opcode::CmpRI: {
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std::vector<Operand> nops = ops;
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NormalizeRegOps(nops, nops[0].GetReg());
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os << " cmp " << PhysRegName(nops[0].GetReg()) << ", #"
|
|
|
<< nops[1].GetImm() << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::FCmpRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " fcmp " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::SIToFP: {
|
|
|
PhysReg dst = ops.at(0).GetReg();
|
|
|
PhysReg src = ops.at(1).GetReg();
|
|
|
if (!IsWReg(src)) src = ToW(src);
|
|
|
os << " scvtf " << PhysRegName(dst) << ", " << PhysRegName(src) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::FPToSI: {
|
|
|
PhysReg dst = ops.at(0).GetReg();
|
|
|
PhysReg src = ops.at(1).GetReg();
|
|
|
if (!IsWReg(dst)) dst = ToW(dst);
|
|
|
os << " fcvtzs " << PhysRegName(dst) << ", " << PhysRegName(src) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::ZExt:
|
|
|
os << " and " << PhysRegName(ops.at(0).GetReg()) << ", "
|
|
|
<< PhysRegName(ops.at(1).GetReg()) << ", #1\n";
|
|
|
break;
|
|
|
case Opcode::AndRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " and " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::OrRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " orr " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::EorRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " eor " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::LslRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " lsl " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::LsrRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " lsr " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::AsrRR: {
|
|
|
std::vector<Operand> nops = ops;
|
|
|
NormalizeRegOps(nops, nops[0].GetReg());
|
|
|
os << " asr " << PhysRegName(nops[0].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[1].GetReg()) << ", "
|
|
|
<< PhysRegName(nops[2].GetReg()) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::B:
|
|
|
os << " b ";
|
|
|
PrintOperand(os, ops.at(0));
|
|
|
os << "\n";
|
|
|
break;
|
|
|
case Opcode::BCond:
|
|
|
os << " b.";
|
|
|
PrintOperand(os, ops.at(0));
|
|
|
os << " ";
|
|
|
PrintOperand(os, ops.at(1));
|
|
|
os << "\n";
|
|
|
break;
|
|
|
case Opcode::Call:
|
|
|
os << " bl ";
|
|
|
PrintOperand(os, ops.at(0));
|
|
|
os << "\n";
|
|
|
break;
|
|
|
case Opcode::Ret:
|
|
|
os << " ret\n";
|
|
|
break;
|
|
|
case Opcode::Nop:
|
|
|
os << " nop\n";
|
|
|
break;
|
|
|
case Opcode::Label:
|
|
|
os << ops.at(0).GetLabel() << ":\n";
|
|
|
break;
|
|
|
case Opcode::Movk:
|
|
|
os << " movk " << PhysRegName(ops.at(0).GetReg()) << ", #"
|
|
|
<< ops.at(1).GetImm() << ", lsl #" << ops.at(2).GetImm() << "\n";
|
|
|
break;
|
|
|
case Opcode::LoadStackAddr: {
|
|
|
const FrameSlot& slot = GetFrameSlot(function, ops.at(1));
|
|
|
int64_t offset = slot.offset;
|
|
|
PhysReg dst = ToX(ops.at(0).GetReg()); // 地址必须是 X 寄存器
|
|
|
|
|
|
auto tryEmitSimple = [&]() -> bool {
|
|
|
if (offset >= 0 && offset <= 4095) {
|
|
|
os << " add " << PhysRegName(dst) << ", x29, #" << offset << "\n";
|
|
|
return true;
|
|
|
} else if (offset < 0 && offset >= -4095) {
|
|
|
os << " sub " << PhysRegName(dst) << ", x29, #" << (-offset) << "\n";
|
|
|
return true;
|
|
|
}
|
|
|
return false;
|
|
|
};
|
|
|
|
|
|
if (tryEmitSimple()) break;
|
|
|
|
|
|
// 复杂偏移
|
|
|
uint64_t absOffset = (offset >= 0) ? offset : -offset;
|
|
|
PrintLoadImm64(os, PhysReg::X16, absOffset);
|
|
|
if (offset >= 0) {
|
|
|
os << " add " << PhysRegName(dst) << ", x29, x16\n";
|
|
|
} else {
|
|
|
os << " sub " << PhysRegName(dst) << ", x29, x16\n";
|
|
|
}
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::Adrp: {
|
|
|
// adrp Xd, label
|
|
|
os << " adrp " << PhysRegName(ops.at(0).GetReg()) << ", "
|
|
|
<< ops.at(1).GetLabel() << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::AddLabel: {
|
|
|
// add Xd, Xn, :lo12:label
|
|
|
os << " add " << PhysRegName(ops.at(0).GetReg()) << ", "
|
|
|
<< PhysRegName(ops.at(1).GetReg()) << ", :lo12:"
|
|
|
<< ops.at(2).GetLabel() << "\n";
|
|
|
break;
|
|
|
}
|
|
|
case Opcode::Sxtw: {
|
|
|
PhysReg dst = ops.at(0).GetReg();
|
|
|
PhysReg src = ops.at(1).GetReg();
|
|
|
// sxtw 要求 X 目标，W 源
|
|
|
if (!IsXReg(dst)) dst = ToX(dst);
|
|
|
if (!IsWReg(src)) src = ToW(src);
|
|
|
os << " sxtw " << PhysRegName(dst) << ", " << PhysRegName(src) << "\n";
|
|
|
break;
|
|
|
}
|
|
|
default:
|
|
|
os << " // unknown instruction\n";
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
// 打印单个函数（单函数版本）
|
|
|
void PrintAsm(const MachineFunction& function, std::ostream& os) {
|
|
|
// 输出函数标签
|
|
|
os << ".text\n";
|
|
|
os << ".global " << function.GetName() << "\n";
|
|
|
os << ".type " << function.GetName() << ", %function\n";
|
|
|
os << function.GetName() << ":\n";
|
|
|
|
|
|
// 计算栈帧大小
|
|
|
int frameSize = function.GetFrameSize();
|
|
|
|
|
|
// 输出每个基本块
|
|
|
const auto& blocks = function.GetBasicBlocks();
|
|
|
bool firstBlock = true;
|
|
|
|
|
|
for (const auto& bb : blocks) {
|
|
|
DEBUG_MSG("block");
|
|
|
// 输出基本块标签（非第一个基本块）
|
|
|
if (!firstBlock) {
|
|
|
os << bb->GetName() << ":\n";
|
|
|
}
|
|
|
firstBlock = false;
|
|
|
|
|
|
// 输出基本块中的指令
|
|
|
for (const auto& inst : bb->GetInstructions()) {
|
|
|
DEBUG_MSG("inst");
|
|
|
PrintInstruction(os, inst, function);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
os << ".size " << function.GetName() << ", .-" << function.GetName() << "\n";
|
|
|
}
|
|
|
|
|
|
} // namespace
|
|
|
|
|
|
// 打印模块（模块版本）
|
|
|
void PrintAsm(const MachineModule& module, std::ostream& os) {
|
|
|
// 输出文件头
|
|
|
os << ".arch armv8-a\n";
|
|
|
|
|
|
// 输出数据段：全局变量
|
|
|
const auto& globals = module.GetGlobals();
|
|
|
if (!globals.empty()) {
|
|
|
os << "\n.data\n";
|
|
|
for (const auto& g : globals) {
|
|
|
os << ".global " << g.name << "\n";
|
|
|
os << ".type " << g.name << ", %object\n";
|
|
|
os << ".align " << g.alignment << "\n";
|
|
|
os << g.name << ":\n";
|
|
|
if (g.is_zero_init) {
|
|
|
os << " .zero " << g.size << "\n";
|
|
|
} else if (g.has_init_data) {
|
|
|
if (g.size == 4) {
|
|
|
os << " .word " << static_cast<uint32_t>(g.init_data) << "\n";
|
|
|
} else if (g.size == 8) {
|
|
|
os << " .quad " << g.init_data << "\n";
|
|
|
} else {
|
|
|
// 暂不支持的标量大小，回退为零初始化
|
|
|
os << " .zero " << g.size << " // unhandled init size\n";
|
|
|
}
|
|
|
} else {
|
|
|
// 有初始值但无法提取（例如数组、结构体）
|
|
|
os << " .zero " << g.size << " // unhandled initializer\n";
|
|
|
}
|
|
|
os << ".size " << g.name << ", " << g.size << "\n\n";
|
|
|
}
|
|
|
}
|
|
|
|
|
|
static const std::set<std::string> externalFuncs = {
|
|
|
"getint", "getch", "getarray", "putint", "putch", "putarray", "puts",
|
|
|
"_sysy_starttime", "_sysy_stoptime", "starttime", "stoptime",
|
|
|
"getfloat", "putfloat", "getfarray", "putfarray", "memset",
|
|
|
"sysy_alloc_i32", "sysy_alloc_f32", "sysy_free_i32", "sysy_free_f32",
|
|
|
"sysy_zero_i32", "sysy_zero_f32"
|
|
|
};
|
|
|
DEBUG_MSG("module");
|
|
|
// 遍历所有函数，输出汇编
|
|
|
for (const auto& func : module.GetFunctions()) {
|
|
|
|
|
|
if (externalFuncs.count(func->GetName())) {
|
|
|
continue; // 跳过库函数桩
|
|
|
}
|
|
|
DEBUG_MSG("func");
|
|
|
PrintAsm(*func, os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
}
|
|
|
|
|
|
} // namespace mir
|
