From 9f415f6564e1b1c65ed7d91222a94efecb19b877 Mon Sep 17 00:00:00 2001 From: xiaokai <2485423036@qq.com> Date: Tue, 27 Jun 2023 19:30:07 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=A3=E7=A0=81=E4=BF=AE=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/UWE_projectCode/tmp/tmp/.Makefile.swl | Bin 16384 -> 0 bytes src/UWE_projectCode/tmp/tmp/.Makefile.swm | Bin 16384 -> 0 bytes src/UWE_projectCode/tmp/tmp/.Makefile.swn | Bin 16384 -> 0 bytes src/UWE_projectCode/tmp/tmp/.Makefile.swo | Bin 16384 -> 0 bytes src/UWE_projectCode/tmp/tmp/.Makefile.swp | Bin 20480 -> 0 bytes src/UWE_projectCode/tmp/tmp/.dc.log.swo | Bin 16384 -> 0 bytes .../tmp/tmp/.setModuleName.tcl.swp | Bin 12288 -> 0 bytes src/UWE_projectCode/tmp/tmp/Makefile | 440 -- src/UWE_projectCode/tmp/tmp/Makefile (copy) | 440 -- src/UWE_projectCode/tmp/tmp/Makefile~ | 440 -- .../tmp/tmp/ProjectPathSetting.tcl | 2 - .../tmp/tmp/Scripts/R0_check.result | 7 - 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/space/PRJ_Front_End/M7004V/src/DSPCORE/VRF/lib/*WC.lib >> ez.work/lib.f -ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/LVT/lib/RHSTD_LVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f - -cp ${PROJECTPATH}/syn/dont_use.tcl ez.work/dont_use_cells.tcl -sed -i "s?set_dont_use?dont_use_cell?" ez.work/dont_use_cells.tcl - -${SCRIPTPATH}/ezeco_setup.sh dc - -${SCRIPTPATH}/ezlec.sh - -ezeco -in ./ez.work/$ECO_COMM/easyeco_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt - -cp ez.work/$ECO_COMM/${moduleName}_eco.sv.v $R1_PATH/result/${moduleName}_eco.sv - -cp ${TCLPATH}/formality.tcl ez.work/$ECO_COMM/ - -fm_eco_to_svf ./ez.work/R1src/rtl ./src/rtl > ./ez.work/$ECO_COMM/eco_change.svf - -sed -i 's?./${PP}/result/${Design}.sv?./${R1_PATH}/result/${Design}_eco.sv?' ez.work/$ECO_COMM/formality.tcl -sed -i 's?./${PP}/report/$Design.svf?./${R1_PATH}/report/$Design.svf?' ez.work/$ECO_COMM/formality.tcl -sed -i "s?Design.svf?Design.svf ./ez.work/$ECO_COMM/eco_change.svf?" ez.work/$ECO_COMM/formality.tcl -sed -i "s?fm.log?fm_ez.log?" ez.work/$ECO_COMM/formality.tcl -sed -i "s?fm_svf?fm_ez_svf?" ez.work/$ECO_COMM/formality.tcl - -fm_shell -64 -f ./ez.work/$ECO_COMM/formality.tcl | tee fm_ez.log ${DCWORK}/Logs/fm_ez_${current_date}.log - -fm_result=`grep "Verification SUCCEEDED" fm_ez.log` -if [[ ${fm_result} == "" ]]; then - echo "ECO FM CHECK FAILED!!!" - exit -else - echo "ECO FM CHECK SUCCEEDED!" -fi - -${SCRIPTPATH}/ezeco_setup.sh dft - -ezeco -in ./ez.work/$ECO_COMM/easyeco_dft_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt - -cp ez.work/$ECO_COMM/${moduleName}_dft_eco.sv.v $R1_PATH/result/${moduleName}_dft_eco.v - -#ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/RVT/lib/RHSTD_RVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f -#ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/ULVT/lib/RHSTD_ULVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f -# -#${SCRIPTPATH}/ezeco_setup.sh pr -# -#ezeco -in ./ez.work/$ECO_COMM/easyeco_pr_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt -# -#cp ez.work/$ECO_COMM/${moduleName}_pr_eco.sv.v $R1_PATH/result/${moduleName}_pr_eco.v - -#if [ -e $R1_PATH/result/${moduleName}.v ]; then -# mv $R1_PATH/result/${moduleName}.v $R1_PATH/result/${moduleName}_B4_$ECO_COMM.v -#else -# mv $R1_PATH/result/${moduleName}.sv $R1_PATH/result/${moduleName}_B4_$ECO_COMM.sv -#fi - -echo ez.work/$ECO_COMM > ez.work/LastECO.txt diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/calc_dff_count.sh b/src/UWE_projectCode/tmp/tmp/Scripts/calc_dff_count.sh deleted file mode 100644 index b4030fb..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/calc_dff_count.sh +++ /dev/null @@ -1,14 +0,0 @@ -echo "FullChip"; grep "_D_" ./Syn_FullChip/20190418_1124/result/DM6672V_FullChip_20190418_1124_ultra.v | wc -l -echo "VPIF"; grep "_D_" ./Syn_SubModule/Syn_VPIF/20190408_0916/result/*.v | wc -l -echo "GMAC"; grep "_D_" ./Syn_SubModule/Syn_GMAC/20190108_1644/result/*.v | wc -l -echo "DDR"; grep "_D_" ./Syn_SubModule/Syn_DDR/20190108_1644/result/*.v | wc -l -echo "H264E"; grep "_D_" ./Syn_SubModule/Syn_H264E/20190108_1644/result/*.v | wc -l -echo "CD"; grep "_D_" ./Syn_SubModule/Syn_CrossNet_Data/20190407_2037/result/*.v | wc -l -echo "CC"; grep "_D_" ./Syn_SubModule/Syn_CrossNet_Config/20190407_2037/result/*.v | wc -l -echo "SMC_BankPort"; grep "_D_" ./Syn_SubModule/Syn_SMC_BankPort/20190108_1644/result/*.v | wc -l -echo "CorePac"; grep "_D_" ./Syn_SubModule/Syn_CorePac/*.v | wc -l -echo "H264D"; grep "_D_" ./Syn_SubModule/Syn_H264D/20190108_1644/result/*.v | wc -l -echo "SMC"; grep "_D_" ./Syn_SubModule/Syn_SMC/20190108_1708/result/*.v | wc -l -echo "DMAx"; grep "_D_" ./Syn_SubModule/Syn_DMAx/20190108_1644/result/*.v | wc -l -echo "PPC"; grep "_D_" ./Syn_SubModule/Syn_PowerPC/20190108_1644/result/*.v | wc -l -echo "SRIO"; grep "_D_" ./Syn_SubModule/Syn_SRIO/20190226_0837/result/*.v | wc -l diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/cds_gen b/src/UWE_projectCode/tmp/tmp/Scripts/cds_gen deleted file mode 100644 index 59410cd..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/cds_gen +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh -#Author: liusheng -#Date: 2019.09.03 -#Role: use it, users do not need to modify the path in cds.lib. - - -NC_PATH=`which simvision` - -CDS_LIB_PATH=${NC_PATH/\/bin\/simvision/.lnx86\/inca\/files\/cds.lib} - -echo "# Contain a project-wide cds.lib" > cds.lib -echo INCLUDE ${CDS_LIB_PATH} >> cds.lib -echo " " >> cds.lib -echo "# Bind library. Logic name <=> Physical Library path." >> cds.lib -echo "# ======LEON3's Library=====" >> cds.lib -echo "DEFINE grlib xncsim/grlib" >> cds.lib -echo "DEFINE techmap xncsim/techmap" >> cds.lib -echo "DEFINE gaisler xncsim/gaisler" >> cds.lib -echo "DEFINE work xncsim/work" >> cds.lib - -echo "WORK > DEFAULT" > synopsys_sim.setup -echo "DEFAULT:vcs_lib/work" >> synopsys_sim.setup -echo "grlib:vcs_lib/grlib" >> synopsys_sim.setup -echo "gaisler:vcs_lib/gaisler" >> synopsys_sim.setup -echo "techmap:vcs_lib/techmap" >> synopsys_sim.setup - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check.sh deleted file mode 100644 index 45268c5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check.sh +++ /dev/null @@ -1,11 +0,0 @@ -find . -name "log.txt" | xargs grep "Error:" > check.result -find . -name "log.txt" | xargs grep "Can't" >> check.result -find . -name "log.txt" | xargs grep "unresolv" >> check.result -find . -name "fm.log" | xargs grep "Error:" >> check.result -find . -name "fm.log" | xargs grep "Can't" >> check.result -find . -name "pt.log" | xargs grep "Error:" >> check.result -find . -name "pt.log" | xargs grep "Can't" >> check.result -find . -name "lib2db.log" | xargs grep "Error:" >> check.result -find . -name "lib2db.log" | xargs grep "Can't" >> check.result - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_R0.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check_R0.sh deleted file mode 100644 index 57d6aac..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_R0.sh +++ /dev/null @@ -1,65 +0,0 @@ -PP=`./Scripts/setPP.sh` -echo "PP = ${PP}" - -echo "Checking dc.log ..." > R0_check.result -find ${PP} -name "dc.log" | xargs grep "Error:" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "Latch " >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "Timing loop" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "FFGEN" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "have the default net type" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "unresolved" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "unmapped" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "(LINT-5)" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "sensiti" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "MV-038" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "MV-039" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "MV-513" >> R0_check.result -find ${PP} -name "dc.log" | xargs grep "MV-514" >> R0_check.result - -echo " " >> R0_check.result -echo "Checking check_timing.txt and check_design.txt ..." >> R0_check.result -find ${PP} -name "check_timing.txt" | xargs grep "timing loop" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-0)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-3)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-4)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-6)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-7)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-11)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-12)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-20)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-21)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-22)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-23)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-26)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-27)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-40)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-41)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-42)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-56)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-57)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-58)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-59)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-61)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-62)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-63)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-64)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-65)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-66)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-68)" >> R0_check.result -find ${PP} -name "check_design.txt" | xargs grep "(LINT-69)" >> R0_check.result - -echo " " >> R0_check.result -echo "Checking pt.log, check_timing_pt.txt ..." >> R0_check.result -find ${PP} -name "pt.log" | xargs grep "Error:" >> R0_check.result -find ${PP} -name "pt.log" | xargs grep "(LNT-005)" >> R0_check.result -find ${PP} -name "check_timing_pt.txt" | xargs grep "Error:" >> R0_check.result -find ${PP} -name "check_timing_pt.txt" | xargs grep "Warning:" >> R0_check.result - -echo " " >> R0_check.result -echo "Checking fm.log ..." >> R0_check.result -find ${PP} -name "fm.log" | xargs grep "Error: " >> R0_check.result -find ${PP} -name "fm.log" | xargs grep "***** Verification Results *****" >> R0_check.result -find ${PP} -name "fm.log" | xargs grep "Verification SUCCEEDED" >> R0_check.result -find ${PP} -name "fm.log" | xargs grep "Verification FAILED" >> R0_check.result - -cp R0_check.result ${PP}/R0_check.result diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_SRC_ID.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check_SRC_ID.sh deleted file mode 100644 index f910296..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_SRC_ID.sh +++ /dev/null @@ -1,44 +0,0 @@ -dir=`tclsh ./ProjectPathSetting.tcl` -moduleName=`tclsh setModuleName.tcl` -cur_dir=`pwd` -echo $dir -echo $cur_dir -echo $moduleName -srcpath=`find $dir -maxdepth 1 -name '*src' -type d` -echo $srcpath - -cd src -svn info > $cur_dir/RTL_DC_info.log -svn list -vR >> $cur_dir/RTL_DC_info.log -ID=`svn list -vR | cksum | awk '{print $1}'` -echo "set RTL_DC_ID $ID" > $cur_dir/RTL_DC_ID.tcl - -cd $cur_dir -echo "#!/bin/sh" > update_RTL_SVN.sh -echo "" >> update_RTL_SVN.sh -while read line -do - #echo $line - r=`echo $line | cut -d' ' -f1` - f=`echo $line | cut -d' ' -f7` - if [ -n "$f" ]&&[ $r != "Last" ]; then - echo svn up -r$r $f >> update_RTL_SVN.sh - fi -done < RTL_DC_info.log - -cd $srcpath/PUBLIC -svn list -vR >> $cur_dir/RTL_DC_info.log -svn list -vR > $cur_dir/tmp.log - -cd $cur_dir -while read line -do - #echo $line - r=`echo $line | cut -d' ' -f1` - f=`echo $line | cut -d' ' -f7` - if [ -n "$f" ]&&[ $r != "Last" ]; then - echo svn up -r$r $srcpath/PUBLIC/$f >> update_RTL_SVN.sh - fi -done < tmp.log - -rm tmp.log diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_Skeyword b/src/UWE_projectCode/tmp/tmp/Scripts/check_Skeyword deleted file mode 100644 index 84633a1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_Skeyword +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash -PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -find $PROJECTPATH -name "*.v" | xargs grep -n 'full_case' -find $PROJECTPATH -name "*.v" | xargs grep -n 'parallel_case' -find $PROJECTPATH -name "*.v" | xargs grep -n 'translate on' -find $PROJECTPATH -name "*.v" | xargs grep -n 'translate off' diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_code.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check_code.sh deleted file mode 100644 index 4073b73..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_code.sh +++ /dev/null @@ -1,75 +0,0 @@ -c_date=`date +%Y_%m%d_%H%M` - -echo "Checking filelist.v ..." > code_check.result -filelistpath=`find ./src/ -name '*flist*' -type f` -echo "filelistpath:" $filelistpath -for file in $filelistpath; do - filelistname+=${file#*src/}' ' -done -echo "filelistname:" $filelistname -if [ -z "$filelistname" ]; then - echo "Error: Filelist is not exist or the name is not matching '*_filelist' format. exit." - echo "Error: Filelist is not exist or the name is not matching '*_filelist' format. exit." >> code_check.result - exit -fi -SIMEMU=`grep -n "_SIMULATION_\|_EMULATION_" $filelistpath` -if [ -z "$SIMEMU" ]; then - echo "Info: There are no _SIMULATION_ or _EMULATION_ definition in file $filelistname ." -fi - -echo " " >> code_check.result -echo "Checking 'timescale' in *.v files ... (Warning)" >> code_check.result -find ./src/ -name "*.v" | xargs grep -n 'timescale' >> code_check.result - -echo " " >> code_check.result -echo "Checking Chinese words in *.v files .. (Warning)." >> code_check.result -find ./src/ -name "*.v" | xargs grep -nP '[\p{Han}]' >> code_check.result - -echo " " >> code_check.result -echo "Checking Synophsis key words in *.v files ... (Info)" >> code_check.result -find ./src/ -name "*.v" | xargs grep -n 'full_case' >> code_check.result -find ./src/ -name "*.v" | xargs grep -n 'parallel_case' >> code_check.result -find ./src/ -name "*.v" | xargs grep -n 'translate on' >> code_check.result -find ./src/ -name "*.v" | xargs grep -n 'translate off' >> code_check.result - -echo " " >> code_check.result -echo "Checking author notes in *.v files .. (Warning)." >> code_check.result -for file in `find ./src/ -regex ".*\.vh\|.*\.v\|.*\.h"` -do - authorname=`grep -n "author\|Author\|AUTHOR\|Generated by\|created" $file` - if [ -z "$authorname" ]; then - echo "Warning: Author notes is not exist or the name is not matching 'author|Author|AUTHOR|Generated by|created' format in file $file" - echo "Warning: Author notes is not exist or the name is not matching 'author|Author|AUTHOR|Generated by|created' format in file $file" >> code_check.result - fi -done - -echo " " >> code_check.result -echo "Checking NC log in xrun.log ... " >> code_check.result -find . -maxdepth 1 -name "xrun.log" | xargs grep "*E" >> code_check.result -find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,RECOME" >> code_check.result -find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVWSP" >> code_check.result -find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVWSI" >> code_check.result -find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVMPW" >> code_check.result - -echo " " >> code_check.result -echo "Checking DC dc.log ..." >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "Error:" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "Latch " >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "Timing loop" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "FFGEN" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "have the default net type" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "unresolved" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "unmapped" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "(LINT-5)" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "sensiti" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "MV-038" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "MV-039" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "MV-513" >> code_check.result -find . -maxdepth 1 -name "dc.log" | xargs grep "MV-514" >> code_check.result - -echo " " >> code_check.result -echo "Checking SpyGlass Lint. ..." >> code_check.result -find ./spyglass.work/sg_results/*/consolidated_reports/ -name "moresimple.rpt" | xargs grep "Error" >> code_check.result -find ./spyglass.work/sg_results/*/consolidated_reports/ -name "moresimple.rpt" | xargs grep "WARNING" >> code_check.result - -cp code_check.result Logs/code_check_${c_date}.result diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_code_auto.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check_code_auto.sh deleted file mode 100644 index 771edd8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_code_auto.sh +++ /dev/null @@ -1,108 +0,0 @@ -MODULES=(DDR_top PCIE_Top RapidIO_top DMA0_wrapper RA14S_top SMC_BankMem) -MASK=( 1 1 1 1 0 1) - -i=0 -for m in ${MODULES[@]} -do - echo $i ${MASK[$i]} - if [ ${MASK[$i]} == 1 ]; then - echo $m - if [ $m == SMC_BankMem ]; then - gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../SMC_Top; make flow; cd ../../; touch ${m}_done.tmp; exec csh" - else - gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../../; touch ${m}_done.tmp; exec csh" - fi - fi - i=$(($i+1)) -done - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - i=0 - k=0 - for m in ${MODULES[@]} - do - if [ ${MASK[$i]} == 1 ]; then - if [ -f ${m}_done.tmp ]; then - echo $i $m "continue" - i=$(($i+1)) - continue - else - echo $i $m "break" - k=1 - break - fi - fi - i=$(($i+1)) - done - if [ $k == 0 ]; then - j=0 - fi -done - -gnome-terminal --geometry=100x30+100*$i+0 --window --title="M8024V_SuperNode" -x csh -c "cd Syn_SubModule/M8024V_SuperNode; make flow; cd ../../; touch M8024V_SuperNode_done.tmp; exec csh" - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - k=0 - if [ ! -f M8024V_SuperNode_done.tmp ]; then - echo "M8024V_SuperNode break" - k=1 - else - echo "M8024V_SuperNode continue" - fi - if [ $k == 0 ]; then - j=0 - fi -done - -date=`date +%Y_%m%d_%H%M` -echo $date -reportfile=flow_${date}.report -touch reportfile -i=0 -for m in ${MODULES[@]} -do - if [ ${MASK[$i]} == 1 ]; then - echo $m >> $reportfile - cat Syn_SubModule/${m}/R0_check.result >> $reportfile - echo " " >> $reportfile - echo " " >> $reportfile - fi - i=$(($i+1)) -done - -echo "M8024V_SuperNode:" >> $reportfile -cat Syn_SubModule/M8024V_SuperNode/R0_check.result >> $reportfile -echo " " >> $reportfile -echo " " >> $reportfile - -gnome-terminal --geometry=100x30+110*$i+0 --window --title="M8024V_FullChip" -x csh -c "cd Syn_Top; make flow; cd ..; touch M8024V_FullChip_done.tmp; exec csh" - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - k=0 - if [ ! -f M8024V_FullChip_done.tmp ]; then - echo "M8024V_FullChip break" - k=1 - else - echo "M8024V_FullChip continue" - fi - if [ $k == 0 ]; then - j=0 - fi -done - -echo "M8024V_FullChip:" >> $reportfile -cat Syn_Top/R0_check.result >> $reportfile - -rm *_done.tmp diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_file_occupy b/src/UWE_projectCode/tmp/tmp/Scripts/check_file_occupy deleted file mode 100644 index 825dd5b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_file_occupy +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh -ls | tee te.log -rm -f space_occupylist.log -touch space_occupylist.log -while read LINE -do - du -hs $LINE | tee -a space_occupylist.log -done < te.log -rm -f te.log -gedit space_occupylist.log diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_files.sh b/src/UWE_projectCode/tmp/tmp/Scripts/check_files.sh deleted file mode 100644 index 3f4f242..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_files.sh +++ /dev/null @@ -1,15 +0,0 @@ - -dir=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -moduleName=`tclsh setModuleName.tcl` - -if [ ! -d ${dir}/src/${moduleName} ]; then - echo "Source code is not exist or the dir name is not moduleName. exit." - exit -fi - -if [ ! -e ${dir}/src/${moduleName}/${moduleName}_filelist.v ]; then - echo "Filelist is not exist or the name is not moduleName_filelist. exit." - exit -fi - -echo "Source codes and filelist is existing." diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_han b/src/UWE_projectCode/tmp/tmp/Scripts/check_han deleted file mode 100644 index 5a5f602..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_han +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -find $PROJECTPATH -name "*.v" | xargs grep -nP '[\p{Han}]' diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/check_timescale b/src/UWE_projectCode/tmp/tmp/Scripts/check_timescale deleted file mode 100644 index 00a0ce1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/check_timescale +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash -PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -find $PROJECTPATH -name "*.v" | xargs grep -n 'timescale' diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/clock_cross.pl b/src/UWE_projectCode/tmp/tmp/Scripts/clock_cross.pl deleted file mode 100644 index 4b5d4f3..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/clock_cross.pl +++ /dev/null @@ -1,18 +0,0 @@ -#! /usr/bin/perl -$i=0; -$flag=0; -open(NEW,"> $ARGV[1]")||die "ERROR:can't create fzg_result\n"; -open(OLD,"$ARGV[0]")||die "ERROR:can't open clock_cross.v\n"; -while(){ - chomp; - if(/From Clock Crossing Clocks/) {$flag=1;next;} - if(/Information\: Checking \'no\_clock\'/) {$flag=0;} - if($flag==1) { - @array=split(/\s+/,$_); - print NEW "$array[0]\n"; - for($i=1;$i<@array;$i++) - {print NEW "-----> $array[$i]\n";} - print NEW "\n\n";} - - -} diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/copy_sdc.sh b/src/UWE_projectCode/tmp/tmp/Scripts/copy_sdc.sh deleted file mode 100644 index ba78cbd..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/copy_sdc.sh +++ /dev/null @@ -1,32 +0,0 @@ -moduleName=`tclsh setModuleName.tcl` -echo $moduleName - -PP=`setPP.sh` -echo "PP = ${PP}" -PP_date=${PP#*dc.work/} -echo "PP_date = ${PP#*dc.work/}" - -cp $RELATIVEPATH/SDC/${moduleName}.sdc NetlistSubmit/${PP_date}/ -cp $RELATIVEPATH/SDC/${moduleName}_CDC_check.tcl NetlistSubmit/${PP}/ -sed -i 's/set BACKEND false/set BACKEND true/' NetlistSubmit/${PP_date}/${moduleName}.sdc -sed -i 's/set EXTRACT_MODEL true/set EXTRACT_MODEL false/' NetlistSubmit/${PP_date}/${moduleName}.sdc - -if [ ${moduleName} == "SRIO_top" ]; then -cp $RELATIVEPATH/SDC/dwc_e25mp_phy_x4_ns_phy_con.tcl NetlistSubmit/${PP}/ -#sed -i 's/set FLOW SYN/set FLOW STA/' NetlistSubmit/${PP}/const.srio3_ep_phy_top.tcl -fi - -if [ ${moduleName} == "fullchip_top" ]; then -cp ${PP}/result/*.sv NetlistSubmit/${PP} -rf -sed -i 's/set PR true/set PR false/' NetlistSubmit/${PP}/${moduleName}.sdc -cp $RELATIVEPATH/SDC/M66AK_FullChip_skew_check.tcl NetlistSubmit/${PP}/ -cp $RELATIVEPATH/SDC/MaxMinDelay.tcl NetlistSubmit/${PP}/ -#remove power and ground pins. -#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_CLC_Top.sv -#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_CrossNet.sv -#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_excluding_CLC_RESETC_CrossNet.sv -#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_RESETC.sv -#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip.sv -fi - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/create_dummy.py b/src/UWE_projectCode/tmp/tmp/Scripts/create_dummy.py deleted file mode 100644 index 3655456..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/create_dummy.py +++ /dev/null @@ -1,200 +0,0 @@ -#!/usr/bin/python -#company: nudt-wdzs-671 -#filename: creat_dummy.py -#description: generate the dummy file of a verilog top file -#author: liusheng -#revision List: -#(rn: date : modifier: description) -#r1: 2019.01.12 the first copy -#r2: 2020.04.05 solve the problem that the signalname inlcudes "input" / "output" or "inout", such as "input bscan_select_jtag_input; " -#r3: 2020.05.05 solve the problem that the file inlcudes "`resetall or `timescale". -#r4: 2020.05.11 fix the bug in "\n" - -import sys -import re - -####main########################################################################################### -print "welcome to use".center(100,"-") -print 'This tool can generate the dummy file of a verilog file.' -print 'please type "creat_dummy.py src.v dst.v" it will geneate the dummy file (dst.v) of src.v.' -print 'The author of this sofware is liusheng from national university of defense technology, China.' -print "welcome to use".center(100,"-") -print "" - -filepath=sys.argv[1] -file_in=open(filepath,"r") -file_all_1=file_in.read() - -modulename=sys.argv[2]; - -realmodulename=modulename.strip('\.v'); - -#delete all the commenting -file_all_2=re.sub('\/\/.*?\n','\n',file_all_1) -file_all_3=re.sub('\/\*.*?\*\/','',file_all_2) -file_all_4=re.sub('\/\*[\s\S]*?\*\/','\n',file_all_3) -#delete all the `, such as "`resetall or `timescale". -file_all_4=re.sub('`.*?\n','\n',file_all_4) - -#print file_all_4 - -#delete declare -file_all_5=re.sub('.*module[\s\S]*?;','',file_all_4) - -#print file_all_5 - -#get declare -all_declare_1=re.findall('.*module[\s\S]*?\)',file_all_4) -all_declare=re.sub(',|\)',';',''.join(all_declare_1)) - -#print all_declare - -#fix \n -file_all_1=all_declare+file_all_5 -#file_all_2=file_all_1.replace("\n","") -file_all_3=file_all_1.replace(";",";\n") - -#fix reg wire -file_all_4=file_all_3.replace("reg","") -file_all=file_all_4.replace("wire","") - - - -#replace the true "parameter localparam input output inout" as "PARAMETER LOCALPARAM INPUT OUTPUT INOUT" - -file_all=re.sub(r'^parameter','PARAMETER',file_all); -file_all=re.sub(r'\sparameter','\nPARAMETER',file_all); -file_all=re.sub(r' parameter',' PARAMETER',file_all); -file_all=re.sub(r'^localparam','LOCALPARAM',file_all); -file_all=re.sub(r'\slocalparam','\nLOCALPARAM',file_all); -file_all=re.sub(r' localparam',' LOCALPARAM',file_all); -file_all=re.sub(r'^input','INPUT',file_all); -file_all=re.sub(r'\sinput','\nINPUT',file_all); -file_all=re.sub(r' input',' INPUT',file_all); -file_all=re.sub(r'\soutput','\nOUTPUT',file_all); -file_all=re.sub(r' output',' OUTPUT',file_all); -file_all=re.sub(r'^output','OUTPUT',file_all); -file_all=re.sub(r'\sinout','\nINOUT',file_all); -file_all=re.sub(r' inout',' INOUT',file_all); -file_all=re.sub(r'^inout','INOUT',file_all); - -#print file_all - - -#find all parameter -allparameter=re.findall('.*PARAMETER(.*?);',file_all) - -#find all localparam -alllocalparam=re.findall('.*LOCALPARAM(.*?);',file_all) - -#find all input -allinput_ini=re.findall('.*INPUT(.*?);',file_all) - -allinput=",".join(allinput_ini) - -#find all true input -alltrueinput=re.sub('\[.*?\]|\s','',allinput) - -#find all output -alloutput_ini=re.findall('.*OUTPUT(.*?);',file_all) -alloutput=",".join(alloutput_ini) - -#find all true output -alltrueoutput=re.sub('\[.*?\]|\s','',alloutput) - -#find all inout -allinout_ini=re.findall('.*inout(.*?);',file_all) -allinout=",".join(allinout_ini) - -#find all true input -alltrueinout=re.sub('\[.*?\]|\s','',allinout) - -file_out=open(modulename,"w") - -#print allparameter -i=0 -j=0 - -print>>file_out,"module "+realmodulename+"(" -print>>file_out,"//output" -for p in list(re.split(",",alltrueoutput)): - i=i+len(p)+2 - if(i>70): - print>>file_out,'\n'+p+',', - i=len(p)+2 - else: - print>>file_out,p+',', - -i=0 -if(alltrueinout!=''): - print>>file_out,"\n//inout" - for p in list(re.split(",",alltrueinout)): - i=i+len(p)+2 - if(i>70): - print>>file_out,'\n'+p+',', - i=len(p)+2 - else: - print>>file_out,p+',', - -print>>file_out,"" -print>>file_out,"//input" -i=0 -for p in list(re.split(",",alltrueinput)): - j=j+1 - i=i+len(p)+2 - if(i>70): - if(len(re.split(",",alltrueinput))==j): - print>>file_out,'\n'+p - else: - print>>file_out,'\n'+p+',', - i=len(p)+2 - else: - if(len(re.split(",",alltrueinput))==j): - print>>file_out,p - else: - print>>file_out,p+',', -print>>file_out,");" -print>>file_out,"" - -for p in list(allparameter): - p=re.sub('\s','',p) - print>>file_out,' parameter '+p+';' - -for p in list(alllocalparam): - p=re.sub('\s','',p) - print>>file_out,' localparam '+p+';' - - -print>>file_out,"" -for p in list(allinput_ini): - p=re.sub('\s','',p) - print>>file_out," input "+p+";" - -print>>file_out,"" -for p in list(allinout_ini): - p=re.sub('\s','',p) - print>>file_out," inout "+p+";" - -print>>file_out,"" -for p in list(alloutput_ini): - p=re.sub('\s','',p) - print>>file_out," output "+p+";" - -print>>file_out,"" -for p in list(re.split(",",alltrueoutput)): - if("rst" in p)|("reset" in p)|("RST" in p)|("RESET" in p): - print>>file_out," assign "+p+"=1'b1;" - elif ("JTAGC_TDO" in p): - print>>file_out," assign "+p+"=JTAGC_TDI;" - else: - print>>file_out," assign "+p+"='b0;" - - -print>>file_out,"" -for p in list(re.split(",",alltrueinout)): - if(p!=""): - print>>file_out," assign "+p+"='b0;" - -print>>file_out,"endmodule" - -####main########################################################################################### diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/.submethodology_help deleted file mode 100644 index 8c4d9f0..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/.submethodology_help +++ /dev/null @@ -1,9 +0,0 @@ -This step recommends goals to be used during the entire -RTL development cycle for new RTL blocks. - -When RTL is almost ready and final handoff checks are being performed. -At this time, majority of GuideWare New_RTL goals should be run after -every ECO. - -This step also includes a set of Optional goals at each stage. -Design teams should inspect these goals for applicability to their design. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/.submethodology_help deleted file mode 100644 index 7acb53e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/.submethodology_help +++ /dev/null @@ -1,3 +0,0 @@ -The aim of this goal is to check the simulation readiness of the design. At this stage the designer is typically interested in the following - * The designs meets basic connectivity checks such as floating inputs, width mismatch - * The design meets basic simulation prerequisites that can cause functional errors or possible race conditions diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup.spq deleted file mode 100644 index 5ab1bd1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup.spq +++ /dev/null @@ -1,34 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : adv_lint_setup -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -adv_lint_setup mixed -* -Defines Clocks and Resets -* -This step is used to find the clocks and resets in a design. Follow steps below -to complete initial clocks and resets constraints creation: - 1- Understand your design clocks architecture by exploring clocks and resets - as identified by rules run in this template. Black box clocks need to be - resolved. - 2- Copy autoclocks.sgdc and autoresets.sgdc into a new constraint file and - edit the clocks to provide valid clock/reset sources and remove all - non clocks/resets signals from the file -In addition you can also add known case-analysis under which you want to do the -analysis -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --mixed --policy=clock-reset --rules Clock_info01 --rules Reset_info01 --rules Info_Case_Analysis diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup_debug_help.htm deleted file mode 100644 index cfd2114..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_setup_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - adv_lint_setup - - - - - - - - - - - - - -
- -
-

-adv_lint_setup -

-

-The aim of this goal is to help the user in finding the clocks and resets. Review clocks and resets reported by Clock_info01 and Reset_info01. For viewing constant propagation in the design, the user can look at Info_Case_Analysis. -

- - - - -
- -
- - - -
- - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct.spq deleted file mode 100644 index 597016d..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct.spq +++ /dev/null @@ -1,43 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : adv_lint_struct -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 1.1.0 16-Apr-2014 Av_fsm01 deleted -// -// Copyright Atrenta Inc, 2013. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -adv_lint_verify_struct mixed -* -Helps identify and fix structural problems and explore assertion checking opportunities -in a design without performing the actual checks. -Reports design complexity characteristics. -* -The adv_lint_verify_struct goal analyzes structural problems and assertion checking -opportunities in the design. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --mixed --policies=auto-verify - --rule=Av_Info_Case_Analysis // Highlights case-analysis settings --rule=Av_fsminf01 // Reports all the FSMs in the design --rule=Av_fsminf02 // Reports all the interacting FSMs in the design --rule=Av_fsm_analysis // Reports all Fsm related issues like deadlock, livelock, unreachable state and dead transitions --rules=Av_divide_by_zero // Report Divide/Modulus by zero issue --rule=Av_case01 // Reports all the sensitive case items which are not specified --rule=Av_case02 // Reports the case statements with parallel case pragma which have overlapping case items --rule=Av_deadcode01 // Reports redundant logic in the design --rule=Av_bus01 // Reports all the bus contentions in the design --rule=Av_bus02 // Reports all the floating busses in the design --rule=Av_dontcare01 // Reports sensitizable X-assignments in the design --rule=Av_range01 // Reports array bound violation --rule=Av_complexity01 // Reports design characteristics and complexity for all the RTL modules and FSMs in the design - --audit=yes -+syntharg -ignoreHangingFF diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct_debug_help.htm deleted file mode 100644 index 47cec03..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_struct_debug_help.htm +++ /dev/null @@ -1,72 +0,0 @@ - - - - - - - - - - adv_lint_verify_struct - - - - - - - - - - - - - -
- -
-

-adv_lint_verify_struct -

-

-The aim of this goal is to identify and fix structural problems, report design complexity, and explore assertion checking opportunities in a design -The violations can be debugged and fixed in the following order -

-
    -
  1. Analyze reported FSMs
    2. -
  2. Analyze reported design complexity
    3. -
  3. Analyze assertion opportunities for functional rules
    4. -

    -
- - - - -
- -
- - - -
- - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify.spq deleted file mode 100644 index f1df021..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify.spq +++ /dev/null @@ -1,41 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : adv_lint_verify -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 1.1.0 16-Apr-2014 Av_fsm01 deleted -// -// Copyright Atrenta Inc, 2013. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -adv_lint_verify mixed -* -Helps identify and fix functional problems related to FSMs, case statements, dead and static code, -busses, and x assignment. -Reports design complexity characteristics. -* -The adv_lint_verify goal analyzes functional problems in the design. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --mixed --policies=auto-verify - --rule=Av_Info_Case_Analysis // Highlights case-analysis settings --rule=Av_fsminf01 // Reports all the FSMs in the design --rule=Av_fsminf02 // Reports all the interacting FSMs in the design --rule=Av_fsm_analysis // Reports all Fsm related issues like deadlock, livelock, unreachable state and dead transitions --rule=Av_divide_by_zero // Report Divide/Modulus by zero issue --rule=Av_case01 // Reports all the sensitive case items which are not specified --rule=Av_case02 // Reports the case statements with parallel case pragma which have overlapping case items --rule=Av_deadcode01 // Reports redundant logic in the design --rule=Av_bus01 // Reports all the bus contentions in the design --rule=Av_bus02 // Reports all the floating busses in the design --rule=Av_dontcare01 // Reports sensitizable X-assignments in the design --rule=Av_range01 // Reports array bound violation --rule=Av_complexity01 // Reports design characteristics and complexity for all the RTL modules and FSMs in the design - -+syntharg -ignoreHangingFF diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify_debug_help.htm deleted file mode 100644 index cba3831..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/adv_lint_verify_debug_help.htm +++ /dev/null @@ -1,72 +0,0 @@ - - - - - - - - - - adv_lint_verify - - - - - - - - - - - - - -
- -
-

-adv_lint_verify -

-

-The aim of this goal is to analyze all the functional problems in the design. This runs all the functional rules of the Advanced Lint policy. -The violations can be debugged and fixed in the following order -

-
    -
  1. Analyze and resolve x-assignments, divide/modulus by zero issues, generation and propagation problems in the design reported by the rules Av_dontcare01, Av_divide_by_zero, Av_bus01, Av_bus02 and Av_range01.
    2. -
  2. Fix the FSM-related issues and case statement related issues reported by the rules Av_fsm_analysis, Av_case01 and Av_case02
    3. -
  3. Fix the redundant code related violations reported by Av_deadcode01 and Av_staticnet01 rules.
    4. -

    -
- - - - -
- -
- - - -
- - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl.spq deleted file mode 100644 index c33863c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl.spq +++ /dev/null @@ -1,81 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : lint_functional_rtl -// Version: 5.6.1 -// -// Revision History: -// Ver Date Comments -// 1.0.0 26-Nov-2014 Initial version -// 5.4.1 04-Mar-2015 Made following changes -// Removed arg: +syntharg -ignoreHanginFF -// Added use_inferred_clocks & use_inferred_resets -// -// 5.5.0 16-Apr-2015 Added Av_signed_unsigned_mismatch and Av_width_mismatch_expr -// -// 5.6.0 18-Nov-2015 5.6 Added Following Rules -// Rule Name Policy GW Type -// =============================================== -// Av_width_mismatch_expr02 auto-verify MUST -// Av_width_mismatch_expr03 auto-verify MUST -// Av_dontcare_mismatch auto-verify MUST -// Av_case_default_missing auto-verify MUST -// Av_case_default_redundant auto-verify MUST -// -// 5.6.1 29-Mar-2015 Removed use_inferred_resets & use_inferred_clocks -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_functional_rtl mixed -* -Helps identify width related issues in assignment, case expression-select, instance -port connection and function arguments using functional analysis -* -This goal uses functional analysis to identify width related issues in the design. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ --policies=auto-verify - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ --nocheckoverflow='yes' // Width will be calculated as per LRM rather best fit. - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ --rule=Av_Info_Case_Analysis // Highlights case-analysis settings - --rule=Av_width_mismatch_assign // LHS width is less than RHS width of assignment (Truncation) - --rule=Av_width_mismatch_case // Case expression width does not match case select expression width - --rule=Av_width_mismatch_port // Instance port connection has different width compared to the port definition - --rule=Av_width_mismatch_function // Bit-width of function call arguments must match bit-width of the corresponding function definition arguments - -// Do not mix signed & unsigned variables/constants in expressions, assignment statements or in comparisons --rule=Av_signed_unsigned_mismatch - -//Bit-width of operands of a logical operator must match --rule=Av_width_mismatch_expr - --rule=Av_case_default_missing // A case statement(or selected signal assignment) does not have a default clause - --rule=Av_width_mismatch_expr03 // Unequal length in arithmetic comparison operator - --rule=Av_width_mismatch_expr02 // Unequal length operands in bit wise logical/arithmetic/relational operator - --rule=Av_dontcare_mismatch // Use of don't-care except in case labels may lead to simulation/synthesis mismatch - --rules Av_case_default_redundant // A case statement marked full_case or a priority/unique case statement have a default clause. - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl_debug_help.htm deleted file mode 100644 index 4c48398..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/adv_lint/lint_functional_rtl_debug_help.htm +++ /dev/null @@ -1,72 +0,0 @@ - - - - - - - - - - adv_lint_verify - - - - - - - - - - - - - -
- -
-

-adv_lint_verify -

-

-The aim of this goal is to analyze width related problems in the design. This runs all the functional rules of the Advanced Lint policy. -The violations can be debugged and fixed in the following order -

-
    -
  1. Analyze and resolve assignment width mismatch in the design reported by the rules Av_width_mismatch_assign.
    2. -
  2. Analyze and resolve case expression width mismatch in the design reported by the rules Av_width_mismatch_case
    3. -
  3. Fix the width mismatch in arguments of functional calls and port connection in instantiation reported by Av_width_mismatch_port and Av_width_mismatch_function rules.
    4. -

    -
- - - - -
- -
- - - -
- - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/.submethodology_help deleted file mode 100644 index 7acb53e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/.submethodology_help +++ /dev/null @@ -1,3 +0,0 @@ -The aim of this goal is to check the simulation readiness of the design. At this stage the designer is typically interested in the following - * The designs meets basic connectivity checks such as floating inputs, width mismatch - * The design meets basic simulation prerequisites that can cause functional errors or possible race conditions diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract.spq deleted file mode 100644 index 1bbfcd8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract.spq +++ /dev/null @@ -1,93 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : cdc_abstract -// Version: 1.7.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 26-Apr-2013 5.1 Parameter enable_handshake removed -// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, enable_fifo=strict removed -// Setup_port01, Setup_blackbox01 added -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.10.2 23-Feb-2015 5.4.1 Parameter decompile_block_constraints added -// Parameter sdc_generate_cfp added -// Rule FalsePathSetup added -// 1.13.0 03-Feb-2017 2017.03 Parameter reset_reduce_pessimism added -// 1.14.0 26-Apr-2017 2017.03-SP1 Parameters check_multiclock_bbox, cdc_qualifier_depth, clock_reduce_pessimism, reset_reduce_pessimism, cdc_reduce_pessimism, include_block_interface, use_block_interface added - -// 1.15.0 18-July-2017 2017.12 Parameter use_inferred_abstract_port added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -cdc_abstract mixed -* -Abstraction of a block for CDC verification at a higher level of hierarchy -* -This step is used to abstract a block which is to be used at higher level of -hierarchy for CDC verification. The abstracted model helps in following: - - Less run-time at top-level - - Less noise at top-level as no violations will be reported inside the blocks - - Perform this step after doing CDC verification of block. -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_mux_sync=all //MUX Synchronization schemes --enable_and_sync=yes //Enables the AND Gate Synchronization Scheme --distributed_fifo=yes //Enables detection of FIFOs based on distributed memories --fa_disable_sync_fifo=yes //Specifies whether functional analysis should be performed on synchronous FIFO structures --strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --block_abstract //Generates relevant CDC constraints for block abstraction --sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains --decompile_block_constraints // Create merged abstract model --reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules - --include_block_interface=abstract //Put SV interface information into the abstract model --use_block_interface //Use the SV internface information in the abstract model --check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored --cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers --clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain --cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue. --use_inferred_abstract_port=yes - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Setup_port01 //Reports unconstrained ports summary for top design unit - --rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes - --rules Ac_abstract01 //Generates relevant SpyGlass CDC constraints for block abstraction - --rules Info_Case_Analysis // Constant propagation in schematic display - --rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract_debug_help.htm deleted file mode 100644 index 6f9b275..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_abstract_debug_help.htm +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - cdc_abstract - - - - - - - - - - - - - -
- -
-

-cdc_abstract -

-

-The aim of this goal is to generate abstract model of a block. This goal reports an informational message by rule Ac_abstract01, which points to the SGDC file containing abstract model. - - -

-
  • Use generated abstract models of blocks at SoC level for CDC verification and abstraction validation checks. You can provide the generated abstract model just with the RTL interface of blocks, without full definitions of blocks.
    • -

    - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup.spq deleted file mode 100644 index 6013c10..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup.spq +++ /dev/null @@ -1,69 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : cdc_setup -// Version: 1.7.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.12.0 18-Nov-2015 5.6.0 Parameter handle_combo_arc=yes added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -cdc_setup mixed -* -Define Clocks and Resets -* -This step is used to find the clocks and resets in a design. Follow steps below -to complete initial clocks and resets constraints creation: - 1- Understand your design clocks architecture by exploring clocks and resets - as identified by rules run in this template. Black box clocks need to be - resolved by assuming path through black boxes (use assume_path constraint) - 2- Copy autoclocks.sgdc and autoresets.sgdc into a new constraint file and - edit the clocks to provide valid clock/reset sources and remove all - non clocks/resets signals from the file - In addition you can also add known case-analysis under which you want to do CDC analysis. -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --handle_combo_arc=yes //propagate clocks through lib cells - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Setup_clock01 // Generates information needed for Clock Setup - --rules Clock_info01 // Clock candidates in the design - --rules Reset_info01 // Asynchronous and synchronous preset and clear candidates in the design - --rules Info_Case_Analysis // Constant propagation in schematic display - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check.spq deleted file mode 100644 index 8d3689e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check.spq +++ /dev/null @@ -1,137 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : cdc_setup_check -// Version: 1.12.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 05-Oct-2013 5.2 Rule Clock_check10 added -// 1.4.0 12-Feb-2014 5.2.1 Clock_info18 removed -// Ar_converge01, Setup_req01, Setup_port01, Setup_blackbox01 added -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed -// 1.10.2 23-Feb-2015 5.4.1 Rule FalsePathSetup added -// Rule Setup_library01 added -// Parameter sdc_generate_cfp added -// Rule Ac_clockperiod01 removed -// Rule Ac_clockperiod02 removed -// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed -// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset -// 1.14.0 26-Apr-2017 2017.03-SP1 Rules Clock_info05c, Clock_info01, Reset_info01 added -// Rule Reset_check10 removed -// 1.15.0 18-July-2017 2017.12 Parameter use_inferred_abstract_port added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// 1.18.0 04-Dec-2018 2018.09 QualifierSetup rule removed due to unneccessary noise STAR #9001291972 -// -// Copyright Atrenta Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -cdc_setup_check mixed -* -Clocks and Resets Setup Checks -* -This step is used to check setup correctness and completeness; it is very -important to fix all violations reported in this step to avoid false violations -due to incorrect/incomplete setup . Some examples, - 1- Ensure all flops are receiving a clock - 2- Ensure case analysis is defined preventing multiple clocks controlling - the same flop - 3- Ensure multiple clocks are not defined on the same clock path - 4- Periods, edge-list and domains are defined properly for clocks - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains --report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer --use_inferred_abstract_port=yes - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Clock_info03a // Reports unconstrained clock nets --overloadrules Clock_info03a+severity=Error - --rules Clock_info05 // MUX descriptions where two or more clock signals converge --overloadrules Clock_info05+severity=Error - -## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection --overloadrules Clock_info05a+severity=Error - --rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge --overloadrules Clock_info05b+severity=Error - --rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file --overloadrules Ac_resetvalue01+severity=Error - --rules Reset_info09a // Reports Unconstrained asynchronous reset nets --overloadrules Reset_info09a+severity=Error - --rules Clock_converge01 // Clocks whose multiple fan-outs converge --overloadrules Clock_converge01+severity=Error - --rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge - --rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously --overloadrules Reset_check03+severity=Error - --rules Reset_check11 //Asynchronous resets used as both active-high and active-low --overloadrules Reset_check11+severity=Error - --rules Reset_check12 // Flops that do not get active reset during power on reset --overloadrules Reset_check12+severity=Error - --rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value - --rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant --overloadrules Clock_info03c+severity=Error - --rules Setup_port01 //Reports unconstrained ports summary for top design unit - --rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes - --rules Clock_check10 // Reports clocks being used as data - --rules Clock_info15 // Generates clock domain information for primary ports - --rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode - --rules Info_Case_Analysis // Constant propagation in schematic display - --rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs - --rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design - --rules Setup_library01 //Reports incomplete definition of library pins for CDC - --rules Clock_info01 // Clock candidates in the design - --rules Reset_info01 // Asynchronous and synchronous preset and clear candidates in the design - --ignorerules QualifierSetup //Removed due to unneccessary noise -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check_debug_help.htm deleted file mode 100644 index 77bec19..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_check_debug_help.htm +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - - cdc_setup_check - - - - - - - - - - - - - -
    - -
    -

    -cdc_setup_check -

    -

    -The aim of this goal is to check setup correctness and completeness. To avoid false analysis due to incorrect/incomplete setup, the user should fix all violations reported during this step. The violations can be debugged and fixed in the following order: -

    -
      -
    1. Analyze and fix clock setup issues reported by the following rules:
      2. -

      -Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05c, Clock_info05b, Clock_info01, Reset_info01, Clock_converge01, Ar_converge01, FalsePathSetup, Setup_library01 -

      -
    2. Analyze and fix reset setup issues reported by the following rules:
      3. -

      -Reset_info09a, Ac_resetvalue01, Ar_syncrst_setupcheck01 -

      -
    3. Analyze and fix basic issues in reset logic reported by the following rules:
      4. -

      -Reset_check03, Reset_check11, Reset_check12 -

      -
    4. Review report and SGDC file generated by rules Clock_info15, Setup_port01, Setup_blackbox01 to ensure all IOs are properly constrained
      5. -

      -
    5. Review and prune the quasi_static constraints in SGDC file generated by Setup_quasi_static01 rule and provide the SGDC file in CDC verification goals
      6. -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_debug_help.htm deleted file mode 100644 index 591f6f4..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_setup_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - cdc_setup - - - - - - - - - - - - - -
    - -
    -

    -cdc_setup -

    -

    -The aim of this goal is to help the user in finding the clocks and resets. Review clocks and resets reported by Clock_info01, and Reset_info01. -

    -

    -For an in-depth analysis and understanding of clocks architecture, the user can look at Setup_clock01. For viewing constant propagation in the design, the user can look at Info_Case_Analysis. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify.spq deleted file mode 100644 index 79f5add..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify.spq +++ /dev/null @@ -1,245 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : cdc_verify -// Version: 1.14.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 26-Apr-2013 5.1 Rule Ar_syncrst_setupcheck01 added -// Parameter enable_handshake removed -// 1.2.0 06-Aug-2013 5.1.1 Rules Ac_handshake01 and Ac_handshake02 removed -// 1.3.0 04-Oct-2013 5.2 Rule Clock_check10 added -// Rules Ac_coherency01a, Ac_coherency02a added -// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, Ac_fifo01, Ac_cdc08, enable_fifo removed -// Ar_converge01, Setup_req01, Ac_conv04, Ac_conv05, Ac_coherency06, Setup_port01, Setup_blackbox01 added -// 1.5.0 16-Apr-2014 5.3 Rules Ac_coherency01a and Ac_coherency02a deleted -// 1.6.0 30-Apr-2014 5.3 Rule Clock_sync09 removed -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.8.0 21-Jul-2014 5.3.1 Enabled Ac_glitch03, allow_combo_logic -// 1.8.1 08-Aug-2014 5.3.1 Removed Ac_conv05. Ac_conv04 description updated -// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed -// 1.10.2 23-Feb-2015 5.4.1 Parameter cdc_reduce_pessimism=ignore_multi_domain added -// Parameter reset_reduce_pessimism=remove_overlap added -// Parameter sdc_generate_cfp added -// Rule FalsePathSetup added -// Rule Setup_library01 added -// 1.11.0 11-Jun-2015 5.5.0 Rule parameter cdc_qualifier_depth added -// 1.11.1 31-Aug-2015 5.5.1 Parameter fa_disable_sync_fifo=yes removed -// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed -// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset -// 1.14.0 26-Apr-2017 2017.03-SP1 Rules Clock_info05c, Clock_glitch05, Clock_info01, Reset_info01 added -// Parameters check_multiclock_bbox, cdc_qualifier_depth, conv_sync_seq_depth, conv_sync_seq_depth_opt, clock_reduce_pessimism, allow_merged_qualifier added -// Overloaded rule severity for rules Clock_sync05, Clock_sync06, Reset_sync02 -// Removed rules Reset_check10, Reset_info02, Clock_info02 -// 1.15.0 18-July-2017 2017.12 Rule Ac_glitch04, Clock_sync05a, Clock_sync06a added -// Parameter conv_sync_as_src added -// Parameter use_inferred_abstract_port added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// -// Copyright Atrenta Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -cdc_verify mixed -* -Clock Domain Crossing Verification -* -This step is used to verify all aspects of clock domain crossings; main CDC -issues covered are: - 1- Metastability - 2- Data hold with regard to destination clock and enable - 3- Coherency problem on reconvergent crossings - 4- Functional correctness of FIFOs - 5- Ensure all synchronous resets follow convention specified by reset_sync_style - constraint - In this step any change that may affect the setup will also be monitored and -any setup issues (e.g. converging clocks, missing clocks definition) will be -reported. - For faster CDC verification closure, it is recommended to address structural -violations by running cdc_verify_struct prior to this step. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_mux_sync=all //MUX Synchronization schemes --enable_and_sync=yes //Enables the AND Gate Synchronization Scheme --distributed_fifo=yes //Enables detection of FIFOs based on distributed memories --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops --fa_vcdfulltrace=allnets //Specifies the type of data that is to be dumped to the VCD file --fa_msgmode=all //Specifies the type of assertions --reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules --cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue. --sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains --report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer --use_inferred_abstract_port=yes --conv_sync_as_src=yes - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Ac_clockperiod01 // Missing -period or -edge fields of the clock constraint defined in an SGDC file --overloadrules Ac_clockperiod01+severity=Error - --rules Ac_clockperiod02 //Clocks whose periods are rounded off by SpyGlass for lower design cycle for faster functional analysis - --rules Ac_clockperiod03 // Clocks with design cycles greater than the threshold value --overloadrules Ac_clockperiod03+severity=Error - --rules Clock_info03a // Reports unconstrained clock nets --overloadrules Clock_info03a+severity=Error - --rules Clock_info05 // MUX descriptions where two or more clock signals converge --overloadrules Clock_info05+severity=Error - -## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection --overloadrules Clock_info05a+severity=Error - --rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge --overloadrules Clock_info05b+severity=Error - --rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file --overloadrules Ac_resetvalue01+severity=Error - --rules Reset_info09a // Reports Unconstrained asynchronous reset nets --overloadrules Reset_info09a+severity=Error - --rules Clock_converge01 // Clocks whose multiple fan-outs converge --overloadrules Clock_converge01+severity=Error - --rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge - --rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously --overloadrules Reset_check03+severity=Error - --rules Reset_check11 //Asynchronous resets used as both active-high and active-low --overloadrules Reset_check11+severity=Error - --rules Reset_check12 // Flops that do not get active reset during power on reset --overloadrules Reset_check12+severity=Error - --rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value - --rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant --overloadrules Clock_info03c+severity=Error - --rules Setup_port01 //Reports unconstrained ports summary for top design unit - --rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes - --rules Clock_check10 // Reports clocks being used as data - --rules Ac_initstate01 // Reports a valid state of the design from which the formal analysis would actually start - --rules Ar_syncrstactive01 // Polarity on synchronous reset usage mismatches with -active field in sync_reset_style constraint - --rules Ar_syncrstcombo01 // Combinational logic in synchronous reset path mismatches with -combo field in sync_reset_style constraint - --rules Ar_syncrstload01 // Load on synchronous reset less than the specified max load - --rules Ar_syncrstload02 // Load on synchronous reset exceeds the specified min load - --rules Ar_syncrstpragma01 // Pragma specification on synchronous reset usage mismatches with -pragma field in sync_reset_style constraint - --rules Ar_syncrstrtl01 // Reports if synchronous reset is not detected in condition of first if statement - --rules Ac_unsync01 // Asynchronous clock domain crossings for scalar signals that have at least one unsynchronized source - --rules Ac_unsync02 // Asynchronous clock domain crossings for vector signals having at least one unsynchronized source - --rules Clock_sync05 // Checks for multi-sample inputs --overloadrules Clock_sync05+severity=Error - --rules Clock_sync05a //Reports primary inputs (for which domain is auto-inferred using abstract_module constraint) sampled by multiple clock domains --rules Clock_sync06 // Checks for multi-transition outputs --overloadrules Clock_sync06+severity=Error - --rules Clock_sync06a // Reports primary outputs (for which domain is auto-inferred using abstract_module constraint) driven by multiple clock domain flip-flops or latches --rules Ar_unsync01 // Reports unsynchronized reset signals in the design - --rules Ar_asyncdeassert01 // Reports if reset signal is asynchronously de-asserted - --rules Reset_sync02 // Asynchronous resets used in a clock domain and generated in one of its asynchronous clock domains --overloadrules Reset_sync02+severity=Error - --rules Reset_sync04 //Asynchronous resets synchronized more than once in the same clock domain - --rules Ac_datahold01a // Reports synchronized data clock domain crossings where data can be unstable - --rules Ac_conv01 //same domain signals synchronized in same destination domain, converge after any number of sequential elements - --rules Ac_conv02 //same-domain signals synchronized in same destination domain and converge before sequential elements. - --rules Ac_conv03 // Convergence of synchronized signals from different source domains - --rules Ac_conv04 //For all control-bus clock domain crossings that do not converge, checks for uniform synchronization schemes and further checks gray encoding when formal is enabled - --rules Ac_coherency06 //Reports signals synchronized more than once in the same clock domain - --rules Ac_glitch03 // Reports clock domain crossings subject to glitches --allow_combo_logic=yes //allows combinational logic between crossings only if the logic is within the modules specified using this constraint. --rules Ac_glitch04 // Reports clock domain crossings subject to glitches - --rules Ac_cdc01a // Checks data loss from fast to slow multi-flop or sync-cell synchronized clock domain crossings - --rules Ac_crossing01 // Generate spreadsheet for Crossing Matrix view - --rules Ac_sync01 // Asynchronous clock domain crossings for scalar signals that have all the sources synchronized - --rules Ac_sync02 // Asynchronous clock domain crossings for vector signals that have all sources synchronized - --rules Ar_sync01 // Reports synchronized reset signals in the design - --rules Ar_syncdeassert01 // Reports if reset signal is synchronously de-asserted or not de-asserted at all - --rules Clock_info15 // Generates clock domain information for primary ports - --rules Setup_quasi_static01 // Reports likely quasi-static candidates in the design - --rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode - --rules Info_Case_Analysis // Constant propagation in schematic display - --rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs - --rules Clock_glitch05 //Flags asynchronous sources that converge with different domain clocks - --check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored --cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers --conv_sync_seq_depth=1 //Default to only checking Ac_conv01 to 1 flop. User can override to go deeper --conv_sync_seq_depth_opt=yes //Optimizes Ac_conv runtime when depth=1 --clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain --allow_merged_qualifier=strict - --rules Clock_info01 //Reports likely clock signals - --rules Reset_info01 //Reports likely asynchronous and synchronous preset and clear signals - --rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design - --rules Setup_library01 //Reports incomplete definition of library pins for CDC - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_debug_help.htm deleted file mode 100644 index fefe56a..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_debug_help.htm +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - - - - cdc_verify - - - - - - - - - - - - - -
    - -
    -

    -cdc_verify -

    -

    -The aim of this goal is to verify all aspects of clock domain crossings. Review and fix each category of CDC problems separately. The violations can be debugged and fixed in the following order -

    -
      -
    1. Ensure that the setup is clean: analyze and fix violations reported by the following rules
      2. -

      -Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05b, Clock_converge01, Ar_converge01, Reset_info09a, Ac_resetvalue01, Ac_clockperiod01, Ac_clockperiod02, Ac_clockperiod03, Clock_info15, Setup_port01, Setup_blackbox01, Reset_check03, Reset_check10, Reset_check11, Reset_check12, Ar_syncrstactive01, Ar_syncrstcombo01, Ar_syncrstload01, Ar_syncrstload02, Ar_syncrstpragma01, Ar_syncrstrtl01, FalsePathSetup, Setup_library01 -

      -
    2. Ensure that the design has been properly initialized: Review Ac_initstate01 to ensure at least 80% of flops are initialized and uninitialized flops are not important for functional verification (e.g. sometimes memories are not initialized and are initialized during the execution of the design).
      3. -
    3. Analyze and fix the unsynchronized crossings reported by Ac_unsync01 and Ac_unsync02 rules
      4. -
    4. Analyze and fix other clock and reset synchronization issues reported by the following rules:
      5. -

      -Clock_sync05, Clock_sync06, Ar_unsync01, Ar_asyncdeassert01, Reset_sync02, Reset_sync04 -

      -
    5. Analyze and fix convergence issues reported by following rules
      6. -

      -Ac_conv01, Ac_conv02, Ac_conv03, Ac_conv04, Ac_coherency06 -

      -
    6. Ensure that crossings functionality is correct: Analyze and fix following rules
      7. -

      -Ac_cdc01a, Ac_datahold01a -

      -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct.spq deleted file mode 100644 index ab74f67..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct.spq +++ /dev/null @@ -1,244 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : cdc_verify_struct -// Version: 1.14.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 26-Apr-2013 5.1 Rules Ac_datahold01a, Ac_cdc01a, Ac_cdc08 removed -// Rule Ar_syncrst_setupcheck01 added -// Parameter enable_handshake removed -// 1.2.0 06-Aug-2013 5.1.1 Rules Ac_handshake01 and Ac_handshake02 removed -// 1.3.0 04-Oct-2013 5.2 Rule Clock_check10 added -// Rules Ac_coherency01a, Ac_coherency02a added -// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, Ac_fifo01, enable_fifo removed -// Ar_converge01, Setup_req01, Ac_conv04, Ac_conv05, Ac_coherency06, Ac_abstract_validation01, SGDC_abstract_mapping01, validate_reduce_pessimism, abstract_validate_express,Setup_port01,Setup_blackbox01 added -// 1.5.0 16-Apr-2014 5.3 Rules Ac_coherency01a and Ac_coherency02a deleted -// 1.6.0 30-Apr-2014 5.3 Rule Clock_sync09 removed -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.8.0 21-Jul-2014 5.3.1 Enabled Ac_glitch03, allow_combo_logic -// 1.8.1 08-Aug-2014 5.3.1 Removed Ac_conv05. Ac_conv04 description updated -// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed -// 1.10.2 23-Feb-2015 5.4.1 Parameter cdc_reduce_pessimism=ignore_multi_domain added -// Parameter reset_reduce_pessimism=remove_overlap added -// Parameter sdc_generate_cfp added -// Rule FalsePathSetup added -// Rule Setup_library01 added -// Rule Ac_clockperiod01 removed -// Rule Ac_clockperiod02 removed -// 1.11.0 11-Jun-2015 5.5.0 Rule parameter cdc_qualifier_depth added -// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed -// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset -// 1.14.0 26-Apr-2017 2017.03-SP1 Rule Ac_abstract_validation01 removed and Ac_abstract_validation02 added -// Rules Clock_info05c, Clock_glitch05, Clock_info01, Reset_info01 added -// Parameters autofix_abstract_port, check_multiclock_bbox, cdc_qualifier_depth, conv_sync_seq_depth, conv_sync_seq_depth_opt, clock_reduce_pessimism, allow_merged_qualifier added -// Overloaded rule severity for rules Clock_sync05, Clock_sync06, Reset_sync02 -// Removed rules Ac_clockperiod01, Ac_clockperiod02, Ac_clockperiod03, Reset_check10, Reset_info02, Clock_info02 -// 1.15.0 18-July-2017 2017.12 Rule Ac_glitch04, Clock_sync05a, Clock_sync06a added -// Parameter conv_sync_as_src added -// Parameter use_inferred_abstract_port added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// -// Copyright Atrenta Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -cdc_verify_struct mixed -* -Clock Domain Crossing Verification -* -This step is used to verify all aspects of clock domain crossings; main CDC -issues covered are: - 1- Metastability - 2- Coherency problem on reconvergent crossings - 3- Ensure all synchronous resets follow convention specified by reset_sync_style - constraint - In this step any change that may affect the setup will also be monitored and -any setup issues (e.g. converging clocks, missing clocks definition) will be -reported. -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_mux_sync=all //MUX Synchronization schemes --enable_and_sync=yes //Enables the AND Gate Synchronization Scheme --distributed_fifo=yes //Enables detection of FIFOs based on distributed memories --fa_disable_sync_fifo=yes //Specifies whether functional analysis should be performed on synchronous FIFO structures --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops --fa_vcdfulltrace=allnets //Specifies the type of data that is to be dumped to the VCD file --fa_msgmode=none //Specifies the type of assertions --reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules --sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains --cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue. --report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer --use_inferred_abstract_port=yes --conv_sync_as_src=yes - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - -#-rules Ac_clockperiod03 // Clocks with design cycles greater than the threshold value - --rules Clock_info03a // Reports unconstrained clock nets --overloadrules Clock_info03a+severity=Error - --rules Clock_info05 // MUX descriptions where two or more clock signals converge --overloadrules Clock_info05+severity=Error - -## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection --overloadrules Clock_info05a+severity=Error - --rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge --overloadrules Clock_info05b+severity=Error - --rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file --overloadrules Ac_resetvalue01+severity=Error - --rules Reset_info09a // Reports Unconstrained asynchronous reset nets --overloadrules Reset_info09a+severity=Error - --rules Clock_converge01 // Clocks whose multiple fan-outs converge --overloadrules Clock_converge01+severity=Error - --rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge - --rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously --overloadrules Reset_check03+severity=Error - -#-rules Reset_check10 // Asynchronous resets used as non-reset signals -#-overloadrules Reset_check10+severity=Error - --rules Reset_check11 //Asynchronous resets used as both active-high and active-low --overloadrules Reset_check11+severity=Error - --rules Reset_check12 // Flops that do not get active reset during power on reset --overloadrules Reset_check12+severity=Error - --rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value - --rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant --overloadrules Clock_info03c+severity=Error - --rules Setup_port01 //Reports unconstrained ports summary for top design unit - --rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes - --rules Clock_check10 // Reports clocks being used as data - --rules Ac_initstate01 // Reports a valid state of the design from which the formal analysis would actually start - --rules Ar_syncrstactive01 // Polarity on synchronous reset usage mismatches with -active field in sync_reset_style constraint - --rules Ar_syncrstcombo01 // Combinational logic in synchronous reset path mismatches with -combo field in sync_reset_style constraint - --rules Ar_syncrstload01 // Load on synchronous reset less than the specified max load - --rules Ar_syncrstload02 // Load on synchronous reset exceeds the specified min load - --rules Ar_syncrstpragma01 // Pragma specification on synchronous reset usage mismatches with -pragma field in sync_reset_style constraint - --rules Ar_syncrstrtl01 // Reports if synchronous reset is not detected in condition of first if statement - --rules Ac_unsync01 // Asynchronous clock domain crossings for scalar signals that have at least one unsynchronized source - --rules Ac_unsync02 // Asynchronous clock domain crossings for vector signals having at least one unsynchronized source - --rules Clock_sync05 // Checks for multi-sample inputs --overloadrules Clock_sync05+severity=Error - --rules Clock_sync05a //Reports primary inputs (for which domain is auto-inferred using abstract_module constraint) sampled by multiple clock domains --rules Clock_sync06 // Checks for multi-transition outputs --overloadrules Clock_sync06+severity=Error - --rules Clock_sync06a // Reports primary outputs (for which domain is auto-inferred using abstract_module constraint) driven by multiple clock domain flip-flops or latches --rules Ar_unsync01 // Reports unsynchronized reset signals in the design - --rules Ar_asyncdeassert01 // Reports if reset signal is asynchronously de-asserted - --rules Reset_sync02 // Asynchronous resets used in a clock domain and generated in one of its asynchronous clock domains --overloadrules Reset_sync02+severity=Error - --rules Reset_sync04 //Asynchronous resets synchronized more than once in the same clock domain - --rules Ac_conv01 //same domain signals synchronized in same destination domain, converge after any number of sequential elements - --rules Ac_conv02 //same-domain signals synchronized in same destination domain and converge before sequential elements. - --rules Ac_conv03 // Convergence of synchronized signals from different source domains - --rules Ac_conv04 //For all control-bus clock domain crossings that do not converge, checks for uniform synchronization schemes and further checks gray encoding when formal is enabled - --rules Ac_coherency06 //Reports signals synchronized more than once in the same clock domain - --rules Ac_glitch03 // Reports clock domain crossings subject to glitches --allow_combo_logic=yes //allows combinational logic between crossings only if the logic is within the modules specified using this constraint. --rules Ac_glitch04 //Reports clock domain crossings subject to glitches - --rules Ac_crossing01 // Generate spreadsheet for Crossing Matrix view - --rules Ac_sync01 // Asynchronous clock domain crossings for scalar signals that have all the sources synchronized - --rules Ac_sync02 // Asynchronous clock domain crossings for vector signals that have all sources synchronized - --rules Ar_sync01 // Reports synchronized reset signals in the design - --rules Ar_syncdeassert01 // Reports if reset signal is synchronously de-asserted or not de-asserted at all - --rules Clock_info15 // Generates clock domain information for primary ports - --rules Setup_quasi_static01 // Reports likely quasi-static candidates in the design - --rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode - --rules Info_Case_Analysis // Constant propagation in schematic display - --rules Ac_abstract_validation02 //Reports block abstraction mismatch with top level design - --rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs - --rules Clock_glitch05 //Flags asynchronous sources that converge with different domain clocks - --rules Clock_info01 //Reports likely clock signals - --rules Reset_info01 //Reports likely asynchronous and synchronous preset and clear signals - --validate_reduce_pessimism=all //ignore reporting on the block ports that are hanging, or have a constant or quasi static signal reaching on them --abstract_validate_express=no //Enables low noise and low effort validation checks for hierarchical SoC flow --autofix_abstract_port=no //Used to turn on|off autofix feature --check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored --cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers --conv_sync_seq_depth=1 //Default to only checking Ac_conv01 to 1 flop. User can override to go deeper --conv_sync_seq_depth_opt=yes //Optimizes Ac_conv runtime when depth=1 --clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain --allow_merged_qualifier=strict - --rules SGDC_abstract_mapping01 //Reports clock mapping of an abstracted instance - --rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design - --rules Setup_library01 //Reports incomplete definition of library pins for CDC - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct_debug_help.htm deleted file mode 100644 index b0fc1b1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/cdc_verify_struct_debug_help.htm +++ /dev/null @@ -1,80 +0,0 @@ - - - - - - - - - - cdc_verify_struct - - - - - - - - - - - - - -
    - -
    -

    -cdc_verify_struct -

    -

    -The aim of this goal is to verify structural aspects of clock domain crossings. Review and fix each category of CDC problems separately. The violations can be debugged and fixed in the following order: -

    -
      -
    1. Ensure that the setup is clean: analyze and fix violations reported by the following rules:
      2. -

      -Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05b, Clock_converge01, Ar_converge01, Reset_info09a, FalsePathSetup, Setup_library01, Ac_resetvalue01, Clock_info15, Setup_port01, Setup_blackbox01, Reset_check03, Reset_check11, Reset_check12, Ar_syncrstactive01 Ar_syncrstcombo01 Ar_syncrstload01 Ar_syncrstload02 Ar_syncrstpragma01 Ar_syncrstrtl01 Clock_info05c Clock_glitch05 Clock_info01 Reset_info01 -

      -
    2. Analyze and fix the unsynchronized crossings reported by Ac_unsync01 and Ac_unsync02 rules
      3. -
    3. Analyze and fix other clock and reset synchronization issues reported by the following rules:
      4. -

      -Clock_sync05, Clock_sync06, Ar_unsync01, Ar_asyncdeassert01, Reset_sync02, Reset_sync04 -

      -
    4. Analyze and fix convergence issues reported by the following rules:
      5. -

      -Ac_conv01, Ac_conv02, Ac_conv03, Ac_conv04, Ac_coherency06, Ac_abstract_validation02, SGDC_abstract_mapping01 -

      -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity.spq deleted file mode 100644 index 8b57e37..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity.spq +++ /dev/null @@ -1,117 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : clock_reset_integrity -// Version: 1.14.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.4.0 12-Feb-2014 5.2.1 Ar_converge01 added -// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency -// 1.10.1 22-Dec-2014 5.4.1 Adding starc2005 policy since STARC05-1.4.3.2 requires it -// 1.12.0 18-Nov-2015 5.6.0 Parameter handle_combo_arc=yes added -// 1.13.0 26-Apr-2017 2017.03 Removed timing policy and corresponding rule ClockEnableRace -// -//1.14.0 13-July-2017 2017.12 Overloaded rule severity for Reset_check12 -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// 1.18.0 04-Dec-2018 2018.09 QualifierSetup rule removed due to unneccessary noise STAR #9001291972 -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -clock_reset_integrity mixed -* -Sanity check of Clocks and Resets -* -This step ensures that clocks and resets trees are properly designed and they -are free of glitches, races, and other hazards. - Note that most of the checks require the clocks and resets to be defined. If -you do not have the clocks and resets definitions, you must run the setup for -this step to define them before proceeding with verification. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset -// -policy=starc2005 -// -policy morelint - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --handle_combo_arc=yes //propagate clocks through lib cells - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Clock_info05b //detect clock signals converging on a combinational gate other than a MUX - --rules Clock_check01 //detect unexpected cells, such as latch, tristate, or XOR/XNOR gates in a clock tree - --rules Clock_check04 //Reports the usage of both the edges (positive and negative) of a clock - --rules Reset_check01 //Reports reset signals that are used in a different mode from their respective synthesis pragmas - --rules Reset_check02 //Reports latches, tristate signals, or XOR/XNOR gates in a reset tree - --rules Reset_check03 //Reports synchronous reset signals that are used as active high as well as active low - --rules Reset_check04 //Reports reset signals that are used asynchronously as well as synchronously for different flip-flops - --rules Reset_check06 //Reports high fan-out reset nets that are not driven by placeholder cells - --rules Reset_check07 //Reports asynchronous reset pins driven by a combinational logic - --rules Clock_Reset_info01 //Generates the Clock-Reset Matrix - --rules Clock_glitch02 //Reports clocks that are gated without latching their enable signal properly --overloadrules Clock_glitch02+severity=Warning - --rules Clock_glitch03 //Reports clock signals that pass through a MUX and reconverge back on the same MUX --overloadrules Clock_glitch03+severity=Warning - --rules Clock_glitch04 //Reports flip-flops that converge on a clock pin of a flip-flop through a combinational logic --overloadrules Clock_glitch04+severity=Warning - --rules Clock_Reset_check02 //Reports potential race conditions between flip-flop output and its clock/reset pin - --rules Clock_Reset_check01 //Reports unwanted cells found in clock or reset networks - --rules Clock_Reset_check03 //Reports potential race condition between flip-flop clock and reset pins - --rules Clock_converge01 //Reports the clock signal for which multiple fan-outs converge - --rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge - --rules Info_Case_Analysis //Constant propagation in schematic display - -// -rules STARC05-1.4.3.2 -//-overloadrules STARC05-1.4.3.2+severity=Warning - -// -rules Clock_check02 # high fanout clocks needed only for netlist audit - -// -rules Clock_check03 # bus bits used as clocks not a design problem -// -rules ResetFlop-ML # All the flip-flops should have either synchronous set/reset or asynchronous set/reset - -// -rules Reset_check12 # Reports flops that do not receive active reset when specified reset is active --overloadrules Reset_check12+severity=Error+msgLabel=NORMAL_WARNING --overloadrules Reset_check12+severity=Info+msgLabel=CORNER_WARNING - --ignorerules QualifierSetup //Removed due to unneccessary noise -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity_debug_help.htm deleted file mode 100644 index c7dc839..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/cdc/clock_reset_integrity_debug_help.htm +++ /dev/null @@ -1,79 +0,0 @@ - - - - - - - - - - clock_reset_integrity - - - - - - - - - - - - - -
    - -
    -

    -clock_reset_integrity -

    -

    -The aim of this goal is to check the integrity of clock and reset logic in a design. The violations can be analyzed in the following order: -

    -
      -
    1. Analyze and fix basic clock issues reported by the following rules:
      2. -

      -Clock_check01, Clock_check04, Clock_info05b, Clock_converge01, Ar_converge01 -

      -
    2. Analyze and fix race and glitch issues reported by the following rules:
      3. -

      -Clock_glitch02, Clock_glitch03, Clock_glitch04, Clock_Reset_check01, Clock_Reset_check02, Clock_Reset_check03 -

      -
    3. Analyze and fix basic issues in reset logic reported by the following rules:
      4. -

      -Reset_check01, Reset_check02, Reset_check03, Reset_check04, Reset_check06, Reset_check07 -

      -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/connectivity_verify/connectivity_verification.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/connectivity_verify/connectivity_verification.spq deleted file mode 100644 index ce8e6c6..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/connectivity_verify/connectivity_verification.spq +++ /dev/null @@ -1,94 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare3.0-EarlyAdopter Goal File -// -// Goal Name : connectivity_verification -// Version : 5.5.0 -// -// Revision History: -// Ver Date Comments -// 5.5.0 18-Jun-2015 Initial version -// -// Copyright Atrenta Inc, 2017. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -connectivity_verification -* -Easy capture of connectivity inten across IPs/SoCs and static checks to -suppliment simulation based verification -* - Easy Capture of Connectivity-Intent across IP/SoC - - 1. Compact & portable constraints - 2. Verify 1:1, 1:many, many:1 connections - 3. Checking for illegal conditions - 4. Conditional connectivity - 5. Validate design methodology consistency across blocks and reuse at SoC level - - Static Checks Supplements Simulation Based Verification - - 1. Fast performance to quickly find basic connectivity bugs - 2. Supports regression use model - 3. Violations clearly state the failure root-cause - 4. GUI based design analysis - - For more details about this goal, please refer to the -SpyGlass_ConnectivityVerify_Rules_Reference.pdf file in the doc -subdirectory of your SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=dft_dsm,dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Soc_01 // Expected node value must be achieved - --rules Soc_02 // Paths between user specified nodes must exist - --rules Soc_07 // Structure between user specified nodes exists - --rules Soc_08 // Paths between user specified nodes exists or not - --rules Soc_09 // Path between user specified nodes must not exist - --rules Soc_10 // Specific value on user specified nodes must not exist - --rules Soc_11 // Node must satisfy the specified constraint message tag expression - --rules Soc_12 // Node must not have the specified constraint message tag expression - --rules Atspeed_21 // Check required pulse pattern at specified node - --rules Soc_01_Info // Expected node value is achieved - --rules Soc_02_Info // Connection between user specified nodes exists - --rules Soc_07_Info // Structure between user specified nodes exists - --rules Soc_04 // Show design state for a given tag - --rules Info_Atspeed_21 // Expected pulse pattern at specified node is achieved - --rules Info_testmode // Display testmode simulation results - --rules Diagnose_testmode // Display instances that blocks testmode propagation - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/.submethodology_help deleted file mode 100644 index 7706531..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/.submethodology_help +++ /dev/null @@ -1,10 +0,0 @@ -At RTL stage, the user may have two kind of issues -1) Generate SDC from scratch -2) Have the ability to check the correctness, consistency and completeness of the constraint to factilitate synthesis. This includes - - * Consistency of Clocks and Generated clock - * Overwritten or Duplicate Constraints - * Consistency of Input/Output delays, clock latency, clock uncertainty - * Analysis of Feedthrough paths - * Verify structural connectivity of exceptions - * Compare two SDCs for the same design diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract.spq deleted file mode 100644 index 99410ec..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract.spq +++ /dev/null @@ -1,41 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_abstract -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_abstract -* -Generate Abstract Port for a design -* -Generates the abstract port for a design - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ --block_abstract //for block abstraction - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ --rules CONS_abstract01 // rule that generate abstract port for a design -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract_debug_help.htm deleted file mode 100644 index bb04f02..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_abstract_debug_help.htm +++ /dev/null @@ -1,14 +0,0 @@ - - -

    - SDC Abstract -

    - - -

    The purpose of this Goal is to generate abstract port for a design. - The abstracted view can be used in verifying the timing at system level.

    -

    The abstraction of the block is performed in correlation with the SDC -constraints specified through sdc_data constraints. All such sdc_data constraints are processed and corresponding abstract_port constraints generated by the rule. The mode field of the abstract_port constraint specifies the corresponding sdc_data constraint. These constraints are output into sgdc file. The sgdc file path is highlighted in the message given by the rule.

    - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit-setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit-setup.sgs deleted file mode 100644 index c251335..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit-setup.sgs +++ /dev/null @@ -1,121 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.2 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# 1.1 28-Jul-2008 Fixed documentation issues and incorrect headers -# (31071) -# 1.2 23-Dec-2008 Fixed incorrect use of parameters (35516) -# -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## -########################################################################## -# Register Variables to be used in the script here -########################################################################## -# Variable to check if user has SGDC file that he wants to use -register_variable Q_ASK_FOR_SGDC 0 -# Variable to check if user has sdc file and no sgdc file -register_variable Q_ASK_FOR_SDC 0 -#variable for sdc file name -register_variable Q_SDC_FILE "" -#variable for Last Setup -register_variable Q_LAST_SETUP 0 -#Ask for current_design -register_variable Q_CURRENT_DESIGN "" -# Check if File Exists -register_variable Q_FILE_EXISTS 0 -# Global SGDC File Name - Eventually to be use tagging -register_variable Q_GLOBAL_SGDC "$PRJFILES_DIR/constraints.sgdc" - -set_property -show_index -set_property -hide_step_numbering - -sgsSet Q_FILE_EXISTS 0 -get_property system.fileExists $Q_GLOBAL_SGDC -result_variable Q_FILE_EXISTS -sgsIf { $Q_FILE_EXISTS == 1 } { - set_header_state "Configure SpyGlass Design Constraint File" complete -} - -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -sgsIf { $Q_FILE_EXISTS == 1 } { - create_form -label "CONFIGURE LAST SETUP" { - get_bool -text "A SGDC file from previous setup was detected. Do you want to use the last setup?" -result_variable Q_LAST_SETUP -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 } - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Analyze_the_Flavor_of_SDC.htm - } -} sgsElse { -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Analyze_the_Flavor_of_SDC.htm -} -set_header_state "Before You Start" complete - -set_property -step_header "Configure SpyGlass Design Constraint File" -sgsIf { $Q_LAST_SETUP == 0} { - create_form -label "CONFIGURE SGDC FILE" { - get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 } - get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 } - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - } - set_property -disable_next_button - sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } { - show_text "You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate." - } - - sgsIf { $Q_ASK_FOR_SGDC == 1 } { - set_property -enable_next_button - get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file" - sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } } - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - } sgsElse { - sgsIf {$Q_ASK_FOR_SDC == 1 } { - set_property -enable_next_button - create_form -label "CONFIGURE SDC FILE" { - get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE -text "Please select the SDC file" - set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - #get_property console.top -result_variable Q_CURRENT_DESIGN - #set_sgdc_curr_design -text "Please select the Top Design Unit" -result_variable Q_CURRENT_DESIGN - #get_string -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN - } - - sgsIf {$Q_SDC_FILE == ""} { - set_property -disable_next_button - show_text " You have not selected the SDC file. Please click back and select the SDC file" - } - sgsIf {$Q_CURRENT_DESIGN == ""} { - set_property -disable_next_button - show_text " No current design has been specified or selected. Please click back and select the current design " - } - - set_property -enable_next_button - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE} >> {get_variable $Q_GLOBAL_SGDC} } - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - } sgsElse { - set_property -enable_next_button - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - } - } - - set_header_state "Configure SpyGlass Design Constraint File" complete -} sgsElse { - set_header_state "Configure SpyGlass Design Constraint File" skipped - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm -} - -set_property -step_header "Setup Closure" -sgsSet Q_FILE_EXISTS 0 -get_property system.fileExists $Q_GLOBAL_SGDC -result_variable Q_FILE_EXISTS -sgsIf { $Q_FILE_EXISTS == 1 } { -set_header_state "Setup Closure" complete -show_text " Setup is complete and verified " -} sgsElse { - set_property -disable_next_button -show_text " Setup is incomplete. SGDC file is missing or corrupted. Please Restart or click Back button " -} - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit.spq deleted file mode 100644 index 37f547e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit.spq +++ /dev/null @@ -1,52 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_audit -// Version: 1.0.1 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 1.0.1 19-mar-2014 rule SDC_DataSheet added -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -sdc_audit Constraints Mixed -* -This goal gives designers the ability to compute Design Coverage and report uncovered objects. -* -This audit goal gives designers the ability to compute Design Coverage and reports uncovered design objects. The goal will generate a report providing a health card for the SDC, which will include ports and registers that are not constrainted and the reason why constraints are missing on these design objects. - -In addition, the goal is to extract the domain information from SDC Commands. Extracted information is checked for consistency with the SGDC domain information. It informs the user about the conflicting clock domain classifications in SDC. A SGDC file is generated containing all the clock_group information inferred from the SDC constraints, which can be used for further analysis. Generated clocks' corresponding to source clocks are reported in a tabular format. - - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --mixed - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules SDC_Coverage // Reports how well SDC covers the design - --rules DomainAnalysis //extract domain infromation from the SDC constraints --rules DomainError //Flags clock domain errors extracted from SDC commands --rules DomainInfo //Generate domain information for interacting clocks from SDC commands --rules Domain_SGDC_Consis //clock_group specified in SGDC not consistent with clock_group extracted from SDC constraints - --rules SDC_Report01 //Prints table of Generated clocks versus source clocks --rules SDC_DataSheet //VI-85162 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit_debug_help.htm deleted file mode 100644 index d476e54..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_audit_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - sdc_audit - - - - - - - - - - - - - -
    - -
    -

    -sdc_audit -

    -

    -This goal gives designers the ability to compute Constraints Coverage and report uncovered objects. Coverage is reported in terms of design objects left uncovered by the specified constraints. Design objects of interest for the rule are ports and registers. An uncovered design object is an indication of missing constraints. -

    -

    -The report will identify objects not covered by any constraints and reasons for lack of coverage. If registers are not constrained, run clock_consis goal to get more details. If ports are not constrained, run io_delay goal to get more details. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check.spq deleted file mode 100644 index aacbdcb..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check.spq +++ /dev/null @@ -1,108 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_check -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_check-mixed -* -Basic Consistency and Clean Clock Definition -* -The objective of this step is to detect the inconsistencies in specification of clocks, generated clocks, and perform basic checks on overwritten and conflicting constraints. Without the clean clock definitions, rest of the constraint validation and exception verification would be ineffective. Overwritten and conflicting constraints may not capture the design intent correctly. - -The step also detects the inconsistencies in specification of input/output delays, clock latency, clock uncertainty. Such inconsistencies not only result in synthesis or static timing analysis to produce incorrect results, they can potentially allow these tools to assume a greater slack than available. This translates to insufficient or incomplete optimization by synthesis, which directly affects the QoR. - -Finally this goal checks that all combinational paths are constrained correctly. If a combination path is unconstrained or incorrectly constrained, then tool will perform no timing check on these paths. As a result a device's -operation at any specified speed can not be guaranteed. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ - --mixed - - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --tc_ignore_te=no --ignore_io_if_fp=yes - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - -// Check for Clock Issues --rules Const_Struct04a // Overwritten constraint detected --rules Const_Struct05 // Conflicting constraints detected --overloadrules Const_Struct05+severity=Warning --rules Clk_Gen01a // Clock not driven by a clock constraint --overloadrules Clk_Gen01a+severity=Error --rules Clk_Gen01b // Clock driven by a constant value or hanging --rules Clk_Gen02 // Constrained clock not used as a clock --overloadrules Clk_Gen02+severity=Info --rules Clk_Gen03 // A generated clock is not in the fanout of it source clock --overloadrules Clk_Gen03+severity=Error --rules Clk_Gen05 // Some clocks in the same clock domain have a different root clock --rules Clk_Gen06 // Multiple paths exist from the clock pin of a sequential cell to different clock sources --rules Clk_Gen08 // Object on which clock is generated should not be a port --rules Clk_Gen09 // Clock source pin is in the fanout of another clock, but is not generated by that clock --overloadrules Clk_Gen09+severity=Error --rules Clk_Gen22 // set_input_delay/set_output_delay has been specified on a clock port --rules Clk_Gen23 // Incorrectly defined generated clock -//-rules Clk_Gen23a //Formal rule for Incorrectly defined Generated clock --overloadrules Clk_Gen23+severity=Error - --rules SDC_Methodology66 // set_case_analysis applied on a design object conflicts with the propagated value due to other set_case_analysis commands --rules SDC_Methodology67 // set_case_analysis applied on the output of a flop conflicts with the value propagated at its input --rules Clk_Lat08 // set_clock_latency is set to negative value --rules Clk_Uncert01 // Clock_uncertainty constraint set on an object which is not a real or generated clock --rules Clk_Uncert03 // Inter clock uncertainty not defined between synchronous clocks --rules Clk_Uncert06 // set_clock_uncertainty is set to negative value - -// Check for I/O Delay Issues --rules Inp_Del01b // Input not constrained by set_input_delay --overloadrules Inp_Del01b+severity=Error --rules Inp_Del03a // Input constraint associated with wrong (or, incomplete set of) clocks --overloadrules Inp_Del03a+severity=Error --rules Inp_Del08 // set_input_delay is set on the same input relative to multiple clocks but -add_delay missing --overloadrules Inp_Del08+severity=Error --rules Op_Del01b // Output has no set_output_delay constraint --overloadrules Op_Del01b+severity=Error --rules Op_Del03a // Output constraint associated with wrong (or, incomplete set of) clocks --overloadrules Op_Del03a+severity=Error --rules Op_Del08 // set_output_delay is set on the same output relative to multiple clocks but -add_delay is missing --overloadrules Op_Del08+severity=Error --rules Load02a // Load values are outside technology limits --overloadrules Load02a+severity=Error --rules Inp_Trans01a // Input transition or drive or driving cell is not defined for input --overloadrules Inp_Trans01a+severity=Error --rules SDC_Methodology07 // Delay value for constraint set_max_time_borrow is not within the clock period of the clock driving the latch - -// Check for Combinational Path Issues --rules Combo_Paths01 // Combinational port to port path is unconstrained --overloadrules Combo_Paths01+severity=Error --rules Combo_Paths02 // Path specified in sdc file (through set_max_delay/set_min_delay) has max_delay < min_delay --rules Combo_Paths03 // Combinational path has output_delay+input_delay > clock period or output_delay+input_delay > set_max_delay --overloadrules Combo_Paths03+severity=Error --rules Show_Case_Analysis --rules Show_Clock_Propagation -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_debug_help.htm deleted file mode 100644 index 3ff9f1c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_debug_help.htm +++ /dev/null @@ -1,16 +0,0 @@ - - - sdc_check -

    SDC Check

    - - -

    The objective of this step is to detect the inconsistencies in specification of clocks, generated clocks, and perform basic checks on overwritten and conflicting constraints. Without the clean clock definitions, rest of the constraint validation and exception verification would be ineffective. Overwritten and conflicting constraints may not capture the design intent correctly.

    -

    The step also detects the inconsistencies in specification of input/output delays, clock latency, clock uncertainty. Such inconsistencies not only result in synthesis or static timing analysis to produce incorrect results, they can potentially allow these tools to assume a greater slack than available. This translates to insufficient or incomplete optimization by synthesis, which directly affects the QoR.

    -

    Finally this goal checks that all combinational paths are constrained correctly. If a combination path is unconstrained or incorrectly constrained, then tool will perform no timing check on these paths. As a result a device's - operation at any specified speed can not be guaranteed

    - -

    To debug issues with this goal, first debug all the SDC Parse violations. Such violations lead to incomplete parsing of the SDC file, and many constraints needed could have been ignored due to Parse errors

    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_setup.sgs deleted file mode 100644 index f8a0422..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_check_setup.sgs +++ /dev/null @@ -1,17 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.0 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## - -set_property -step_header "SDC Checks for Clocks, I/O and Feedthroughs" -set_parameters {pt chip clk_gen01_generate_report strict tc_ignore_latch_enable tc_ignore_te ignore_io_if_fp} - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv.spq deleted file mode 100644 index 5619ad7..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv.spq +++ /dev/null @@ -1,41 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_equiv -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_equiv-mixed -* -Constriants Equivalece Checking -* -The objective of this step is to ensure that versions of constraints file are equivalent for the same design. As design goes through iterations, so does constraints. This steps helps designers to ensure that design intent is preserved on account of such iterations. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=const_mgmt,constraints - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Equiv_SDC // Check equivalence between two SDCs for the same design --rules Show_Clock_Propagation --rules Show_Case_Analysis -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_debug_help.htm deleted file mode 100644 index f89ec09..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_debug_help.htm +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - - - - sdc_equiv - - - - - - - - - - - - - -
    - -
    -

    -sdc_equiv -

    -

    -The objective of this step is to ensure that versions of constraints file are equivalent for the same design. As design goes through iterations, so does constraints. This steps helps designers to ensure that design intent is preserved on account of such iterations. -

    -

    -This debug of this rule is typically iterative. The user would need to resolve equivalence issues in the following order - set_case_analysis, clocks (primary and generated), I/O Delay, Timing Exceptions and other constraints. Unless you fix set_case_analysis issues, you won't see clock related issues. This order is important to prevent noise from being reported in the equivalence. Consider the following example -

    -
    -SDC1 -
    -
    -create_clock -name c1 -period 10 -source [a/b/clk] 
-set_input_delay 10 -clock [c1] [get_ports {in1}] 
-
    -
    -SDC2 -
    -
    -create_clock -name c2 -period 11 -source [a/b/clk] 
-set_input_delay 10 -clock [c2] [get_ports {in1}] 
-
    -

    -In this example clocks C1 and C2 are not equivalent. If clocks are not checked before set_input_delay, the equivalence will unnecessarily report the input delays to be not equivalent. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_setup.sgs deleted file mode 100644 index 6945fa9..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_equiv_setup.sgs +++ /dev/null @@ -1,96 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.1 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# 1.1 05-Aug-2010 Proper Setup manager for sdc_equiv -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## -register_variable Q_ASK_FOR_SGDC 0 -register_variable Q_ASK_FOR_SDC 0 -register_variable Q_FLOW_TYPE 0 -register_variable Q_SDC_FILE_1 -register_variable Q_SDC_FILE_2 -register_variable Q_BLOCK_NAME "" -register_variable Q_CURRENT_DESIGN "" -register_variable Q_GLOBAL_SGDC "$WDIR/constraints.sgdc" - -set_property -show_index -set_property -hide_step_numbering -#This step will show the help -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/sdc_equivalence_before_you_start.htm -set_header_state "Before You Start" complete -#In this step we get the type of flow and sdc/sgdc files -set_property -step_header "Configure SpyGlass Design Constraint File" -prereq {"Before You Start"} - -create_form -label "CONFIGURE SGDC FILE" { -# show_text "If you have a SGDC file already added to the setup, then select no for both the options" - get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 } - get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 } - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm -} -set_property -disable_next_button -sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } { - show_text "You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate." -} - -sgsIf { $Q_ASK_FOR_SGDC == 1 } { - set_property -enable_next_button - get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file" - sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } } - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm -} sgsElse { - sgsIf {$Q_ASK_FOR_SDC ==1} { - set_property -enable_next_button -# get_bool -text "Choose Yes if you would like to do block top equivalence, and no if you like to do reference implement equivalence for same top" -buttons {"Yes" "No"} -result_variable Q_FLOW_TYPE -auto_proceed -geometry { -side bottom -expand 0 } - - sgsIf {$Q_FLOW_TYPE == 1} { - create_form -label "Configure SDC File" { - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the SDC file(s) for top module" - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the SDC file(s) for block" - set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN - get_string -text "Please enter the block name" -result_variable Q_BLOCK_NAME - } - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo block -name {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode flatTop >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode block >> {get_variable $Q_GLOBAL_SGDC} } - } sgsElse { - create_form -label "Configure SDC File" { - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the reference SDC file(s)" - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the implement SDC file(s)" - set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN - } - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode reference >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode implement >> {get_variable $Q_GLOBAL_SGDC} } - } - } sgsElse { - - show_text "Please add a SGDC file or enable previously selected SGDC files" - set_constraints - } -} - -set_header_state "Configure SpyGlass Design Constraint File" complete - - -set_property -step_header "Set Parameters" -prereq {"Configure SpyGlass Design Constraint File"} -set_parameters {equiv_sdc_ambiguous_clock_file equiv_sdc_constraint_file equiv_sdc_tolerance} -set_header_state "Set Parameters" complete - -set_property -step_header "Setup Closure" -prereq {"Before You Start" "Configure SpyGlass Design Constraint File"} -show_text "Please review the SGDC files created in this setup" -set_constraints $Q_GLOBAL_SGDC -show_text "Setup is complete and verified" -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct.spq deleted file mode 100644 index 146bf11..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct.spq +++ /dev/null @@ -1,53 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_exception_struct -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 1.0.1 28-Feb-2014 VI-84582 (SCG01 to SCG05 rules are added to guideware2.0) -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_exception_struct-mixed -* -Check Timing Exceptions Structurally -* -The objective of this step is to check that Timing Exceptions specified in a constraints file as are on paths which are structurally connected. This step is a pre-requisite, before the paths can be verified formally to be correct. Exceptions set on paths that are structurally not connected are redundant and increase the runtime of implementation tools. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules False_Path01 // False path reference points are not connected --rules False_Path09 // False path uses same clock in its -from and -to lists --rules MCP01 // Multi cycle path reference points are not connected --rules MCP05 // set_multicycle_path setup/hold over or under defined --rules TE_Conflict01 // Overlap between different timing exceptions commands - --rules Show_Case_Analysis --rules Show_Clock_Propagation - --rules SCG01 //SCG01 to SCG05 added for VI-84582 --rules SCG02 --rules SCG03 --rules SCG04 --rules SCG05 -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_debug_help.htm deleted file mode 100644 index f9e20d3..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - sdc_exception_struct - - - - - - - - - - - - - -
    - -
    -

    -sdc_exception_struct -

    -

    -The objective of this step is to check that Timing Exceptions specified in a constraints file are on paths which are structurally connected. This step is a pre-requisite, before the paths can be verified formally to be correct. Exceptions set on paths that are structurally not connected are redundant and indicate the possibility of typos in specifying the exceptions. -

    -

    -Before debugging this goal ensure that goal clock_consis has been cleaned. Incomplete/incorrect clock can result in noise to be generated for rules in this goal. The rules in this goal can be debugged in any order. To debug False_Path01 and MCP01, open the incremental schematic and try to traverse from the start point to see where the path is broken or blocked that causes the exceptions not to be structurally connected. If there are violations from TE_Conflict01, remove overlapping exceptions. Even though tools provide a well defined order of precedence when exceptions overlap (False Path > Multi Cycle Path > Max/Min Delay), however that order may not be what the designer intended. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_setup.sgs deleted file mode 100644 index 1b1ff09..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_exception_struct_setup.sgs +++ /dev/null @@ -1,16 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.0 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## - -set_property -step_header "Check for Structual Correctness of Exceptions" -set_parameters {tc_ignore_clk_to_clk tc_clk_pairs_for_fp strict} diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen.spq deleted file mode 100644 index 2092c66..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen.spq +++ /dev/null @@ -1,48 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_gen -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Generates Constraints Mixed -* -This goal gives designers the ability to create SDC templates from RTL or netlist. -* -This goal gives designers the ability to create SDC templates from RTL or netlist. This requires the users to identify correct clock sources (in the .sgdc file) - -This goal is useful if you have an RTL, but, don't have the associated SDC. The template will help create a bare-bone structure, where, the actual numbers can be filled up later by the user. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - -// The following rules belongs to constraints policy --rules SDC_GenerateIncr // Generate a template constraints file for a block - -//The following rules belong to clock-reset policy and may be needed for debug -//-policies=clock-reset -//-rules Info_Case_Analysis -//-sdc2sgdc - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_debug_help.htm deleted file mode 100644 index c08f36a..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_debug_help.htm +++ /dev/null @@ -1,15 +0,0 @@ - - - sdc_gen -

    SDC Generation

    - - - -

    This goal gives designers the ability to create SDC templates from RTL or netlist. This requires the users to identify correct clock sources (in the .sgdc file)

    - -

    This goal is useful if you have an RTL, but, don't have the associated SDC. The template will help create a bare-bone structure, where, the actual numbers can be filled up later by the user.

    - -

    For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.

    - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_setup.sgs deleted file mode 100644 index 907f822..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_gen_setup.sgs +++ /dev/null @@ -1,234 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.4 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# 1.1 28-Jul-2008 1) Fixed incorrect documentation in setup -# (29544, 31450) -# 2) Fixed redundancy in steps (31170) -# 3) Enhanced to edit gensdcConstraintsfile.txt (31468) -# 1.2 15-Dec-2008 1) New CDC Setup Manager integrated -# 2) Console Setup improved -# 1.3 24-Dec-2008 1) register output file issues fixed in Console -# 2) Added comments -# 1.4 20-Jan-2009 1) Fixed VIs 36448, 35958 -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the SGS script to setup Constraints Generation -########################################################################## -########################################################################## -# Register Variables to be used in the script here -########################################################################## -# Variable to check if clock has been saved in SGDC -register_variable Q_SGDC_MOD 0 -# Variable to check if clock setup has been run once -register_variable Q_RUN_ONCE 0 -# Variable to check if user wants to run clock setup -register_variable Q_RUN_CLK_SETUP 0 -# Variable to check if file exists -register_variable Q_FILE_EXISTS 0 -# Variable to check, if user has SGDC that he wants to user instead of clock setup -register_variable Q_ASK_FOR_SGDC 0 -# Variable to check, if user want parametrized SDC -register_variable Q_ASK_FOR_PARAM 0 -# Variable to check, SDC Generation has been run once. This way when user hits back button -# and comes back to the step again, it will load the exisiting run -register_variable Q_SDC_GEN_ONCE 0 -# Variable to check, SDC Generation has been run once incrementall. This way when user hits back button -# and comes back to the step again, it will load the exisiting run -register_variable Q_SDC_GEN_INCR 0 -# Variable to store whether last run was with Param or not -register_variable Q_LAST_RUN_WITH_PARAM 0 - -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs - -########################################################################## -# Common Procedures -########################################################################## -## Before you start -set_property -show_index -set_property -hide_step_numbering - -register_variable USE_DESIGN_CLOCKS 1 -register_variable USE_BBOX_RESOLUTION 1 -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs - -set_property -step_header "Before You Start" -show_index -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Constraints_Generation_Setup.htm -set_header_state "Before You Start" complete -## Resolve Blackboxes -source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -########################################################################## -# Setup Step 1 ................... -# Identify all clocks using CDC Setup -########################################################################## - -source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs - -# Add generated SGDC file to the project with recommended constraint as clocks - set_constraints $PRJFILES_DIR/cdc_setup_clocks.sgdc -constraints {clock} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Copy_and_Modify_autoclocks.sgdc.htm -label "Identified Clocks" - -# set_header_state "Review Clocks" complete -#} sgsElse { -## User would have reached this when he created SGDC file and hence Review of Clock Setup Wizard setup is skipped -# set_header_state "Review Clocks" skipped -#} - -########################################################################## -# Setup Step 2 ................... -# Use the SGDC file and generate all clocks in SDC format -########################################################################## - -set_property -step_header "Choose Constraints" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" } - -# Copy the default gensdcConstraintsFile.txt from installation and let the user edit it -#sgsExec { /bin/cp $SPYGLASS_HOME/policies/constraints/gensdcConstraintsFile.txt $WDIR/gensdcConstraintsFile.txt } - sgsCopyFile -file $SPYGLASS_HOME/policies/constraints/gensdcConstraintsFile.txt -target $WDIR/gensdcConstraintsFile.txt -edit_file $WDIR/gensdcConstraintsFile.txt -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Generating_Clocks.htm - -set_header_state "Choose Constraints" complete - -# Now Run the Generation. Ask the user if he/she wants parameterized SDC -set_property -step_header "Generate SDC file" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints"} -set_sgdc_state -enable {get_variable $SETUP_CLOCKS_SGDC} -create_form -label "ASK_FOR_PARAMETRIZATION" { - get_bool -text "Do you create parametrizable SDC? (Default is No)" -result_variable Q_ASK_FOR_PARAM -button {"Yes" "No"} -auto_proceed -geometry { -side bottom } - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Generate_SDC_Template.htm -} -sgsIf { $Q_SDC_GEN_ONCE == 0 || $Q_ASK_FOR_PARAM != $Q_LAST_RUN_WITH_PARAM } { - sgsSet Q_SDC_GEN_ONCE 1 - sgsIf { $Q_ASK_FOR_PARAM == 0} { - sgsSet Q_LAST_RUN_WITH_PARAM 0 - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -auto_run -must_run -text "Running Goal Gen_Constraints to generate the chosen constraints." -auto_proceed - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } sgsElse { - sgsSet Q_LAST_RUN_WITH_PARAM 1 - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -auto_run -must_run -text "Running Goal Gen_Constraints to generate the chosen constraints." -auto_proceed - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } -} sgsElse { - sgsIf { $Q_ASK_FOR_PARAM == 0} { - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } sgsElse { - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } -} - - -set_header_state "Generate SDC file" complete -########################################################################## -# Setup Step 3 ................... -# Use the seed file from Step 2 to add generate more constraints -# This step is same as step2, except that SGDC input is different -########################################################################## -set_property -step_header "Choose More Constraints" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file"} - -# Set the constraints, so that user can now setup the seed file for a future run -#set_constraints -constraints {"sdc_data"} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm -# Copy the file generated in the last run, into the run directory so that user can specify the seed, without any -# references to the path -#sgsExec { /bin/cp $WDIR/spyglass_reports/constraints/*.sdc $PRJFILES_DIR/ } -# -register_variable ALL_OLD_FILE_LIST -get_property console.SGDClist -result_variable ALL_OLD_FILE_LIST -set_sgdc_state -disable { get_variable $ALL_OLD_FILE_LIST } - -register_variable Q_SDC_INCR_FILE -register_variable Q_CURRENT_DESIGN -create_form -label "CONFIGURE SDC FILE" { - get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_INCR_FILE -text "Please select the SDC file generated from the gen_sdc run along with seed sdc file" - set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm - } -sgsIf {$Q_SDC_INCR_FILE == ""} { - set_property -disable_next_button - show_text " You have not selected the SDC file. Please click back and select the SDC file" -} -sgsIf {$Q_CURRENT_DESIGN == ""} { - set_property -disable_next_button - show_text " No current design has been specified or selected. Please click back and select the current design " -} -set_property -enable_next_button -register_variable Q_INCREMENTAL_SGDC "$PRJFILES_DIR/incr.sgdc" -sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_INCREMENTAL_SGDC} } -sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_INCREMENTAL_SGDC} } -sgsExec { echo sdc_data -file {get_variable $Q_SDC_INCR_FILE} -mode seed >> {get_variable $Q_INCREMENTAL_SGDC} } -set_constraints $Q_INCREMENTAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - -# Edit the side file constaining constraints to be generated -edit_file $WDIR/gensdcConstraintsFile.txt -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Choose_Constraints_to_be_added_incrementally.htm - -set_header_state "Choose More Constraints" complete - -set_property -step_header "Generate SDC incrementally" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file" "Choose More Constraints"} -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm -# Now Run the Generation again. Based on what user chose last time, the option to generate parametrized SDC will be -# jsut inherited from the last run -sgsIf { $Q_SDC_GEN_INCR == 0 || $Q_ASK_FOR_PARAM != $Q_LAST_RUN_WITH_PARAM } { - sgsSet Q_SDC_GEN_INCR 1 - sgsIf { $Q_ASK_FOR_PARAM == 0} { - sgsSet Q_LAST_RUN_WITH_PARAM 0 - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -must_run -auto_run -text "Running Goal Gen_Constraints to generate the chosen constraints." - } sgsElse { - sgsSet Q_LAST_RUN_WITH_PARAM 1 - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -must_run -auto_run -text "Running Goal Gen_Constraints to generate the chosen constraints." - } -} sgsElse { - sgsIf { $Q_ASK_FOR_PARAM == 0} { - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } sgsElse { - run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -text "Running Goal Gen_Constraints to generate the chosen constraints." - } -} - -register_variable Q_FINAL_SGDC "$PRJFILES_DIR/final.sgdc" -register_variable Q_FINAL_SGDC_EXISTS 0 -register_variable Q_LAST_SETUP 0 -get_property console.SGDClist -result_variable ALL_OLD_FILE_LIST -set_sgdc_state -disable { get_variable $ALL_OLD_FILE_LIST } - -get_property system.fileExists { get_variable $Q_FINAL_SGDC } -result_variable Q_FINAL_SGDC_EXISTS -## Here we ask the user to again create an SGDC file from last runs generated files. This will be the final SGDC file which will be used during actual goal run - -sgsIf { $Q_FINAL_SGDC_EXISTS == 1 } { - create_form -label "CONFIGURE LAST SETUP" { - get_bool -text "Final SGDC File already exists, do you want to re-use it?" -result_variable Q_LAST_SETUP -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 } - } -} - -sgsIf {$Q_LAST_SETUP == 0} { - create_form -label "CONFIGURE SDC FILE" { - get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_INCR_FILE -text "Please select the SDC file generated from the gen_sdc run along with seed sdc file" - set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm - } - sgsIf {$Q_SDC_INCR_FILE == ""} { - set_property -disable_next_button - show_text " You have not selected the SDC file. Please click back and select the SDC file" - } - sgsIf {$Q_CURRENT_DESIGN == ""} { - set_property -disable_next_button - show_text " No current design has been specified or selected. Please click back and select the current design " - } - set_property -enable_next_button - - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_FINAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_FINAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_INCR_FILE} -mode seed >> {get_variable $Q_FINAL_SGDC} } -} -#sgsExec { /bin/cp $WDIR/spyglass_reports/constraints/*.sdc $PRJFILES_DIR/ } -set_header_state "Generate SDC incrementally" complete - -set_property -step_header "Setup Closure" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file" "Choose More Constraints" "Generate SDC incrementally" } -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/gen_sdc_setup_closure.htm -set_constraints $Q_FINAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm - -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv.spq deleted file mode 100644 index ed4e52f..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv.spq +++ /dev/null @@ -1,42 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_hier_equiv -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_hier_equiv-mixed -* -Hierarchical Constriants Checking -* -The objective of this step is to ensure that constraints are consistent across block hierarchies. This step will help you to check consistency of Block level constraint with sub-chip/chip level constraints for clocks, I/O delays. E.g. a block may have been synthesized with a lower frequency clock (bigger clock period), but at chip level is being driven by a higher frequency clock (smaller clock period). The block may not function correctly. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints,const_mgmt - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules IO_Consis04 // Sum of input delay and output delay should not exceed clock period --rules Equiv_SDC_Block // Check Equivalence between Top and Block level SDC --rules Show_Case_Analysis --rules Show_Clock_Propagation -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_debug_help.htm deleted file mode 100644 index 916032f..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_debug_help.htm +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - - - - sdc_hier_equiv - - - - - - - - - - - - - -
    - -
    -

    -sdc_hier_equiv -

    -

    -The objective of this step is to ensure that constraints are consistent across block hierarchies. This step will help you to check consistency of Block level constraint with sub-chip/chip level constraints for clocks, I/O delays. E.g. a block may have been synthesized with a lower frequency clock (bigger clock period), but at chip level is being driven by a higher frequency clock (smaller clock period). The block may not function correctly. -

    -

    -This debug of this rule is typically iterative. The user would need to resolve equivalence issues in the following order - set_case_analysis, clocks (primary and generated), I/O Delay, Timing Exceptions and other constraints. Unless you fix set_case_analysis issues, you won't see clock related issues. This order is important to prevent noise from being reported in the equivalence. Consider the following example -

    -
    -SDC1 at Top -
    -
    -create_clock -name c1 -period 10 -source [clk] 
-set_input_delay 10 -clock [c1] [get_ports {in1}] 
-
    -
    -SDC2 at Block -
    -
    -create_clock -name c1 -period 11 -source [block/clk] 
-set_input_delay 10 -clock [c1] [get_ports {block/in1}] 
-
    -

    -In this example clocks C1 (in top) and C1 (in block) are not equivalent. If clocks are not checked before set_input_delay, the equivalence will unnecessarily report the input delays to be not equivalent. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_setup.sgs deleted file mode 100644 index 6843945..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_hier_equiv_setup.sgs +++ /dev/null @@ -1,96 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.1 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# 1.1 05-Aug-2010 Proper Setup manager for sdc_equiv -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## -register_variable Q_ASK_FOR_SGDC 0 -register_variable Q_ASK_FOR_SDC 0 -register_variable Q_FLOW_TYPE 1 -register_variable Q_SDC_FILE_1 -register_variable Q_SDC_FILE_2 -register_variable Q_BLOCK_NAME "" -register_variable Q_CURRENT_DESIGN "" -register_variable Q_GLOBAL_SGDC "$WDIR/constraints.sgdc" - -set_property -show_index -set_property -hide_step_numbering -#This step will show the help -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/hierarchical_check_before_you_start.htm -set_header_state "Before You Start" complete -#In this step we get the type of flow and sdc/sgdc files -set_property -step_header "Configure SpyGlass Design Constraint File" -prereq {"Before You Start"} - -create_form -label "CONFIGURE SGDC FILE" { -# show_text "If you have a SGDC file already added to the setup, then select no for both the options" - get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 } - get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 } - show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm -} -set_property -disable_next_button -sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } { - show_text "You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate." -} - -sgsIf { $Q_ASK_FOR_SGDC == 1 } { - set_property -enable_next_button - get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file" - sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } } - set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm -} sgsElse { - sgsIf {$Q_ASK_FOR_SDC ==1} { - set_property -enable_next_button -# get_bool -text "Choose Yes if you would like to do block top equivalence, and no if you like to do reference implement equivalence for same top" -buttons {"Yes" "No"} -result_variable Q_FLOW_TYPE -auto_proceed -geometry { -side bottom -expand 0 } - - sgsIf {$Q_FLOW_TYPE == 1} { - create_form -label "Configure SDC File" { - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the SDC file(s) for top module" - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the SDC file(s) for block" - set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN - get_string -text "Please enter the block name" -result_variable Q_BLOCK_NAME - } - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode flatTop >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo block -name {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode block >> {get_variable $Q_GLOBAL_SGDC} } - } sgsElse { - create_form -label "Configure SDC File" { - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the reference SDC file(s)" - get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the implement SDC file(s)" - set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN - } - sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode reference >> {get_variable $Q_GLOBAL_SGDC} } - sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode implement >> {get_variable $Q_GLOBAL_SGDC} } - } - } sgsElse { - - show_text "Please add a SGDC file or enable previously selected SGDC files" - set_constraints - } -} - -set_header_state "Configure SpyGlass Design Constraint File" complete - - -set_property -step_header "Set Parameters" -prereq {"Configure SpyGlass Design Constraint File"} -set_parameters {equiv_sdc_ambiguous_clock_file equiv_sdc_constraint_file equiv_sdc_tolerance} -set_header_state "Set Parameters" complete - -set_property -step_header "Setup Closure" -prereq {"Before You Start" "Configure SpyGlass Design Constraint File"} -show_text "Please review the SGDC files created in this setup" -set_constraints $Q_GLOBAL_SGDC -show_text "Setup is complete and verified" -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy.spq deleted file mode 100644 index 2bf0128..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy.spq +++ /dev/null @@ -1,63 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : sdc_redundancy -// Version: 1.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -sdc_redundancy-mixed -* -Check for Redundancy in Constraints -* -The objective of this step is to remove any redundancy in the constraints and perform checks that might facilitate better retargeting. This is an optional step and solely the discretion of the design group. - -For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=constraints - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules High_Fan03 // High fanout net identified - --rules False_Path04a // False path specification excludes a large number of paths - --rules MCP04a // Multicycle path specification covers a large number of paths - --rules Disable_Timing02 // Clock path blocked by set_disable_timing - --rules SDC_Report01 // Prints table of generated clocks versus source clocks - --rules Clk_Gen21 // set_propagated_clock set on a virtual clock --rules Clk_Uncert07 // No crossing exists between clocks for which inter-clock uncertainty is defined --rules Clk_Trans16 // set_clock_transition set on virtual clocks - --rules False_Path03 // Unnecessary use of through in false-path --rules MCP03 // Unnecessary use of through in multi-cycle path - --rules Inp_Del07a // Input constraints are incorrect relative to a range of clock period --rules Op_Del07a // Output constraints are incorrect relative to a range of clock period --rules Inp_Del09 // Not all pins on the same bus have the same input delay --rules Op_Del09 // Not all pins on the same bus have the same output delay - --rules Show_Case_Analysis --rules Show_Clock_Propagation - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_debug_help.htm deleted file mode 100644 index f7bb15a..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_debug_help.htm +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - sdc_redundancy - - - - - - - - - - - - - -
    - -
    -

    -sdc_redundancy -

    -

    -The objective of this step is to remove any redundancy in the constraints and perform checks that might facilitate better retargeting. -

    -

    -Before debugging this goal ensure that goals clock_consis, io_delay, combo_path, and structural_exception have been cleaned. -

    -

    -This is an optional step and solely the discretion of the design group. Rules can be debugged in no particular order. Rule debug is similar to the other goals described in the Methodology. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_setup.sgs deleted file mode 100644 index 4472bc5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/constraints/sdc_redundancy_setup.sgs +++ /dev/null @@ -1,16 +0,0 @@ -########################################################################## -# SpyGlass Constraints Methodology -# -# Version: 1.0 -# -# Revision History: -# Ver Date Comments -# 1.0 18-Jun-2008 Initial version -# -# Copyright Atrenta Inc, 2008. All rights reserved. -########################################################################## -# This is the setup file for SDC Validation -########################################################################## - -set_property -step_header "Check for Constraints Redundant Constraints" -set_parameters {clk_gen01_generate_report ignore_io_if_fp inp_percent_max inp_percent_min op_percent_max op_percent_min num_falsepath_max num_mcpath_max tc_ignore_latch_enable tc_ignore_te} diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/.submethodology_help deleted file mode 100644 index 9a54500..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/.submethodology_help +++ /dev/null @@ -1,8 +0,0 @@ -The need for DFT-optimized design: - -Manufacturing test is performed by patterns automatically -generated by ATPG (automatic test pattern generation) tools. -To operate effectively, these tools require that the circuits -be correctly designed for testing. - -This and subsequent steps directly address this issue. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract.spq deleted file mode 100644 index 5250913..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract.spq +++ /dev/null @@ -1,57 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// Goal Name : dft_abstract -// Version : 5.3.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// Added: Short description of rules and parameters -// 5.3.0 20-Jun-2014 Guidware 2.0 Content Consistency -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_abstract -* -Generate abstract view of the design. -* - This goal includes rules which will create the abstract view of design: - - For more details about this goal, please refer to the -SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your -SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --block_abstract // Enables abstraction setup rules - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --dftTreatBBoxAsScanwrapped=on // Treat all black-boxes as scan-wrapped - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Soc_00 // This rule creates abstract view of current design - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract_debug_help.htm deleted file mode 100644 index 7ffd75c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_abstract_debug_help.htm +++ /dev/null @@ -1,69 +0,0 @@ - - - - - - - - - - dft_abstract - - - - - - - - - - - - - -
    - -
    -

    -dft_abstract -

    -
      -
    • The goal helps in creating an Abstract Model for a Block.
      • -
    • SpyGlass DFT supports a hierarchical SoC methodology in which a simplified abstract model of the block can be created when rule checking the block. The model can then be used in lieu of the original RTL for efficient rule checking at the top/SoC level.
      • -
    • The creation of the abstract model is done by running the dft_abstract goal on the block.
      • -
    • When using abstract models for one or more lower level blocks in a design, the dft_abstract_validate goal verifies that the constraints under which the abstraction was done are met in the current design.
      • -
    • The use of the hierarchical SoC methodology for DFT is described in greater detail in the SpyGlass SoC Methodology User Guide.
      • -
    - - - - -
    - -
    - - - -
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b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_best_practice.spq deleted file mode 100644 index 7a2cf32..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_best_practice.spq +++ /dev/null @@ -1,200 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// Goal Name : dft_best_practice -// Version : 5.5.0 -// -// Revision History: -// Ver Date Comments -// 5.5.0 11-Jun-2015 Initial version -// Added: Coverage_audit -// Added: Info_coverage -// Added: Async_07 -// Added: Async_08 -// Added: Clock_11 -// Added: Clock_11_capture -// Added: Clock_26 -// Added: Scan_22 -// Added: Scan_24 -// Added: Scan_25 -// Added: Scan_26 -// Added: Soc_04 -// Added: TA_09 -// Added: Diagnose_testclock -// Added: Diagnose_testmode -// Added: Info_forcedScan -// Added: Info_inferredNoScan -// Added: Info_noScan -// Added: Info_scanchain -// Added: Info_scanwrap -// Added: Info_testmode_conflict_01 -// Added: Info_uncontrollable -// Added: Info_undetectCause -// Added: Info_unobservable -// Added: Info_untestable -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_best_practice -* -Check the design for best practices to find issues that may -decrease ATPG effectiveness -* - ATPG tools typically cannot effectively handle structures such -as asynchronous combinatorial loops, testclock also being used -as data, tristate enables that are not one-hot encoded, flops -having large fanin cones, large timing paths, etc. Due to these -structures, often, there is negative impact on the ATPG tools -in terms of runtime or inadequate coverage achievement. - -Similarly, latches should be made transparent when the capture -mode conditions are simulated with testclocks at their -"return to" state. - - Designers can avoid these pitfalls by discovering such structural -issues at the RTL coding stage. Designers may use this template -to check their designs for best practrices even without testmode -setup knowledge. - - For more details about this goal, please refer to the -SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your -SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Coverage_audit // Analyze coverage for circuit - --rules Info_coverage // Estimate fault and test coverage - --rules Async_02_capture // FF set or reset fanin cone must not contain ffs, latches or bboxes in capture mode - --rules Async_03 // Verifies that all async pins can go to their inactive state at the same time - --rules Async_07 // Asynchronous set/reset sources should be inactive during shift mode --overloadrules Async_07+msgLabel=Async_07_M1+severity=Error - --rules Async_08 // Asynchronous set/reset pins of all the flops should be fully controllable during capture. - --rules Async_11 // Avoid using set/reset signal as data signal in capture mode - --rules BIST_01 // Restrict input cone width for BIST (with appropriate -flopInFaninCount=) - --rules Clock_04 // Do not use clock signals as data signals - --rules Clock_08 // No merging of test clocks - --rules Clock_09 // No logic in common with clock and data - --rules Clock_11 // All clock sources must be testclock controlled in shift mode --overloadrules Clock_11+msgLabel=Clock_11_M1+severity=Error - --rules Clock_11_capture // All clock sources must be testclock controlled in capture mode - --rules Clock_16 // Capture FFs must not have any data paths from FFs capturing on opposite edge of the same clock - --rules Clock_17 // Capture clocks must not be gated by flip-flops capturing on the same clock - --rules Clock_21 // Clocks must not drive flip-flop set or reset pins - --rules Clock_26 // Testclock constraint must not be applied on sensitized fanout of another test clock in Shift or Capture mode - --rules Clock_27 // Detects edge inconsistency between CGC and driven flip-flops - --rules Clock_28 // No combinational reconvergence to flip-flops clock pins - --rules Latch_02 // No combinational loops from transparent latches - --rules Latch_08 // Latches should be transparent in capture mode --overloadrules Latch_08+msgLabel=Latch_08_WRN_01+severity=Error - --rules Latch_10 // All latch enables must be combinationally derived from root level inputs - --rules Scan_07 // No registered (sequentially derived) or combinationally derived internal test_mode signals - --rules Scan_22 // Scan chains must have lockup latches at domain crossing - --rules Scan_24 // All flip-flops should be part of some scan chain - --rules Scan_25 // Scan chains must not contain invertors in scan path - --rules Scan_26 // Scan chains must contain lockup latch at chain end - --rules Soc_04 // Show design state for a given tag - --rules TA_09 // Suggests test points to improve controllability and observability - --rules Topology_01 // Combinational loops are not allowed - --rules Topology_02 // No asynchronous port to port paths - --rules Topology_03 // Avoid sequentially derived asynchronous signals with common clock - --rules Topology_05 // Wire-OR and Wire-AND are not allowed - --rules Topology_10 // Avoid long logic paths (with appropriate -pathDepth=) - --rules Topology_13 // No combinational reconvergence to flip-flops asynchronous pins - --rules Tristate_06 // Tristate bus enables must be fully decoded so that exactly one driver is active at any time - --rules Tristate_07_shift // All Inout ports are inputs only in shift mode - --rules Diagnose_testclock // Display instances that blocks testclock propagation - --rules Diagnose_testmode // Display instances that blocks testmode propagation - --rules Info_forcedScan // Displays all registers and flip-flops specified as 'scan' - --rules Info_inferredNoScan // Displays all flip-flops which have been inferred as no_scan - --rules Info_noFault // Reports all the instances which are specified as no fault or inferred as no fault - --rules Info_noScan // Displays all registers and flip-flops specified as 'no_scan' - --rules Info_scanchain // Displays all properly stitched scanchains - --rules Info_scanwrap // Report scanwrap related information - --rules Info_synthRedundant // Display pins that are likely to be absent in an optimized netlist - --rules Info_testclock // Display test clock propagation - --rules Info_testmode // Display testmode simulation results - --rules Info_testmode_conflict_01 // Display conflict in user specified testmode with respect to simulation result of fanin cone - --rules Info_uncontrollable // Shows nets with imperfect controllability - --rules Info_undetectCause // Display undetectable fault information - --rules Info_unobservable // Shows all unobservable pins - --rules Info_untestable // Display untestable faults caused by test mode - --rules Info_unused // Display faults having no effect on system function - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_best_practice_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_best_practice_debug_help.htm deleted file mode 100644 index d4bd55c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_best_practice_debug_help.htm +++ /dev/null @@ -1,79 +0,0 @@ - - - - - - - - - - dft_best_practice - - - - - - - - - - - - - -
    - -
    -

    -dft_best_practice -

    -

    -Review the violation messages, have better understanding about the issue by bringing up the schematic if appropriate and fix the design issue. Note the fix for these issues may be very design-specific. -

    -

    -Make Latches Transparent (One of the objectives of this goal) -

    -
      -
    • Latch_08 violations (see the description of Latch_08 in the SpyGlass DFT User Guide section on Latch Rules) detect latches that are not transparent in capture mode. Non-transparent latches can be diagnosed with Info_testmode for capture.
      • -
    • Select a Latch_08 violation and display in the IS.
      • -
    • If the latch enable has a non-X but an inactive value then either a test_mode constraint should have the complementary value, or some device in the fan-in to this latch enable should produce the complementary value.
      • -
    • If the latch enable has no value, then either the logic feeding this enable should be modified so that the enable is forced active during capture or new test_mode constraints must be defined.
      • -

      -
      -
      - -

      -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_bist_ready.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_bist_ready.spq deleted file mode 100644 index 94c9a82..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_bist_ready.spq +++ /dev/null @@ -1,39 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// dft_bist_ready -// Version: 5.4.0 -// -// Revision History: -// Ver Date Comments -// 5.4.0 12-Nov-2014 Version as in 5.4.0 -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_bist_ready -* -Make design amicable to bist and test-compression -* - This "bist ready" step provides value not only for designs with Logic BIST -(Built-In-Self-Test) but also for designs with ATPG Compression, as the rules -report on various forms of X-propagation which is detrimental to both. - - This "bist ready" step is designed to ensure that design is aligned with -bist and test-compression requirements. SpyGlass DFT does not do the bist or -compression insertion but rather deals with X-propagation and large fanin cone. - - For more details about this goal, please refer to the -SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your -SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --policies=dft --rules BIST_01 --rules BIST_02 --rules BIST_03 --rules BIST_04 --rules BIST_05 - --rules Info_testmode --rules Info_testclock diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice.spq deleted file mode 100644 index efc2b1b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice.spq +++ /dev/null @@ -1,151 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// Goal Name : dft_dsm_best_practice -// Version : 5.5.0 -// -// Revision History: -// Ver Date Comments -// 5.5.0 11-Jun-2015 Initial version -// Added: Atspeed_07 -// Added: Atspeed_11 (and moved to top) -// Added: Atspeed_14 -// Added: Atspeed_22 -// Added: Atspeed_30 -// Added: CG_01_shift -// Added: CG_01_capture -// Added: CG_01_atspeed -// Added: CG_02_capture -// Added: CG_02_atspeed -// Added: CG_03_capture -// Added: CG_03_atspeed -// Added: CG_07 -// Added: CG_generateReport -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_dsm_best_practice -* -High stuck at coverage is a necessary but not sufficient -condition to achieving high transition coverage. This -template contains rules that address the special needs of -such topics as d-pin controllability, test clock domains -and path issues. -* - DFT for stuck at testing involved a scan and a low speed -capture clock. The purpose of scan was to create a state -that both exercised and observed specific faults. -Transition testing requires two vectors and two clocks -fired at system speed. The first clock pulse causes a -state transition which imposes additional DFT requirements -beyond stuck at DFT. The second clock pulse must be from -the same clock source as the first pulse which also imposes -special DFT considerations. - - Since transition tests are performed with high speed clocks, -false paths and multicycle paths must be taken into account -since various faults along such paths cannot be transition -tested. - - This template contains rules that address these issues, -rules that help diagnose transition rule violations. - - For more details about this goal, please refer to the -SpyGlass-DFT-DSM-Methodology.pdf file in the doc -subdirectory of your SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=dft_dsm,dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Info_transitionCoverage_audit // Analyze transition coverage for circuit - --rules Info_transitionCoverage // Evaluate transition coverage for design - --rules Atspeed_11 // All clock sources must be controlled by an atspeed clock --overloadrules Atspeed_11+severity=Error - --rules Atspeed_03 // Async logic in the functional mode should not interact synchronously in the capture at-speed mode - --rules Atspeed_04 // Synchronously interacting logic in the functional mode should not be clocked by asynchronous clocks in the capture at-speed mod - --rules Atspeed_05 // All false paths or multicycle paths in the functional mode should be blocked in the capture at-speed mode - --rules Atspeed_06 // All paths crossing asynchronous clock domains should be blocked - --rules Atspeed_07 // Clock gating for each domain in the capture at-speed mode should be done using a separate signal - --rules Atspeed_09 // Data pin of scan flip-flop must be fully controllable - --rules Atspeed_14 // Test clocks must not be used as data signals - --rules Atspeed_19 // Latches should be transparent in capture/captureatspeed mode or when testclocks/atspeed clocks are off - --rules Atspeed_20 // Asynchronous set/reset pins of all the flops should be fully controllable during capture atspeed mode - --rules Atspeed_22 // No merging of atspeed clocks in capture atspeed mode - --rules Atspeed_25 // No combinational reconvergence to flip-flops asynchronous pins - --rules Atspeed_30 // No combinational reconvergence to flip-flops clock pins - --rules CG_01_shift // Clock gating cell enables should be enabled in shift mode --overloadrules CG_01_shift+severity=Error - --rules CG_01_capture // Clock gating cell enables should be controllable to on state in capture mode --overloadrules CG_01_capture+severity=Error - --rules CG_01_atspeed // Clock gating cell enables should be controllable to on state in atspeed mode --overloadrules CG_01_atspeed+severity=Error - --rules CG_02_capture // CGC enables should be controllable to off state in capture mode - --rules CG_02_atspeed // CGC enables should be controllable to off state in atspeed mode - --rules CG_03_capture // System enable pins on clock gating cell should be observable in capture mode - --rules CG_03_atspeed // System enable pins on clock gating cell should be observable in atspeed mode - --rules CG_07 // Detects edge inconsistency between CGC and driven flip-flops - --rules CG_generateReport // Generate a text report with details of all clock gating cells in design - --rules Diagnose_02 // At-speed paths must not be blocked by testmode signals - --rules Diagnose_03 // Faults blocked by false paths or multi-cycle paths - --rules Diagnose_04 // Faults in paths crossing clock domains cannot be tested - --rules Info_atSpeedClock // Displays at-speed test clock propagation - --rules Info_noAtspeed // Displays all registers and flip-flops specified as 'no_atspeed' - --rules Info_synthRedundant // Display pins that are likely to be absent in an optimized netlist - --rules Info_testclock // Display test clock propagation - --rules Info_testmode // Display testmode simulation results - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice_debug_help.htm deleted file mode 100644 index b81e58e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_best_practice_debug_help.htm +++ /dev/null @@ -1,204 +0,0 @@ - - - - - - - - - - dft_dsm_best_practice - - - - - - - - - - - - - -
    - -
    -

    -dft_dsm_best_practice -

    -
      -
    • Select an Atspeed_09 violation in IS.
      • -
        -
      • If the cause is a combinational loop, then review in the schematic viewer if a test_mode is missing or has been improperly declared. Otherwise, the design may have to be modified to allow use of a test_mode to break the loop.
        • -
      • If the case is a multiple driven net/floating net, review if a test_mode is missing or has been improperly declared.
        • -
      • If the case is a black box, then create a scan wrapper for the
        module.
        • -
      • If the case is a non-lockup/Non-transparent latch, then review if a test_mode is missing or has been improperly declared.
        • -
      • If the case is a non-scan flip-flop then reconsider the reasons for this to not be scannable. Create a "scan" constraint for this flip-flop to determine the coverage impact.
        • -
      • If the case is a constant value net has been reached, then review if a test_mode is missing or has been improperly declared.
        • -
      -
    • Select an Atspeed_19 violation in the IS. Display the enable fan-in cone back to primary inputs to see if or how this logic should be enabled in captureATspeed mode.
      • -
    • Select an Atspeed_03 violation in the IS. Display the clock fan-in cone back to primary inputs for both flip-flops. If the root level system clocks that feed these flip-flops are synchronous, then add -domain <xx> to each of the clock constraints. If the clocks are not synchronous, then redesign the switching logic or the test_mode constraints so that the clocks are not combined in captureATspeed mode.
      • -
    • Select an Atspeed_04 violation in the IS. Display the clock fan-in cone back to primary inputs for both flip-flops. If the root level clocks that feed these flip-flops are declared asynchronous but shouldn't be, then remove or change -domain <xx> to each of the clock constraints so the clocks are in different domains. If the clocks are synchronous, then redesign the switching logic so that the clocks are combined in captureATspeed mode.
      • -
    • Diagnose_04 can be used to display faults that cannot be tested but use caution since numbers of faults may be involved.
      • -
    • Select an Atspeed_05 violation in IS mode to see paths that declared as multi-cycle or false-path in the SDC file or in SGDC file. If any path should be considered for transition testing, then remove that path from the constraint file.
      • -
    • Select an Atspeed_06 violation in IS mode to see paths that cross clock domains.
      • -
        -
      • If the domains should be considered as synchronous, then add domain <xx> to the atspeed clocks
        • -
      • If the domains are asynchronous, then consider blocking the path with a design change.
        • -
      -
    • Diagnose_03 may be used to view faults that are involved in false path or multi-cycle paths.
      • -
    -

    -Estimate Coverage -

    -
      -
    • Info_transitionCoverage may be used to estimate the transition fault coverage if ATPG were run based on the current circuit and SGDC constraints.
      • -
    • If the coverage estimate reported falls below expectation, run Info_transitionCoverage_audit to find the major causes of low atspeed test (transition delay) coverage.
      • -
    -

    -Improve Coverage -

    -

    -Info_transitionCoverage_audit issues a report of the major causes of low atspeed test (transition delay) coverage. The rule is not intended to diagnose these causes. Instead, the at-speed rules corresponding to a particular cause should be used for diagnosis. -

    -
    -Method -
    -

    -For each cause, the rule will find the cause and list the coverage that would be obtained if that cause were fixed. After the incremental coverage improvement for each cause is computed, the new total coverage is listed. This total coverage will be an increasing value that approaches 100%. -

    -

    -The following categories are the primary reason for coverage data not reaching 100%: -

    -
      -
    • Non scan flip-flops
      • -

      -Assume all flip-flops are scannable. Force all flip-flops, except flip-flops declared with no_scan constraint, to be considered scannable. -

      - - - - - - - - - - - - - - - - - - - - - - - - - - - -
      NOTE: Flip-flops that are declared as no_scan, will not be forced scannable.
      - - - - - - - - - - - - - - - - - - - - - - - - - - - -
      NOTE: Flip-flops that are inferred as no_scan, will be forced as scannable.
      -
    • At speed domains of scan flip-flops
      • -

      -Assume all scannable flip-flops are at-speed clocked. Force all scannable flip-flops that are not clocked by an -atspeed testclock, to be launch points for transition testing. -

      -
    • Uncontrollable data of scan flip-flops
      • -

      -Assume the d-pins of scannable flip-flops are fully controllable. -

      -
    • Feedback flip-flops
      • -

      -Assume all scannable q to d Feedback flip-flops can launch both transitions. -

      -
    • Combinational reconvergence
      • -

      -Assume all combinational reconvergences are broken. -

      -
    • Uncontrollable logic due to hanging terminals
      • -

      -Assume all hanging terminals are fully controllable. -

      -
    • Tristate enable used for capture
      • -

      -Assume enable pin of tristate as a capture node for all domains. -

      -
    • Untestable faults on SCANENABLE/SET/RESET
      • -

      -Assume both transitions can be detected on SE/SET/RESET control logics. -

      -
    • PI and PO used for launch and capture
      • -

      -Assume PIs and POs are used for Launch and Capture nodes, respectively. -

      -
    • Clock domain crossing
      • -

      -Assume all scannable flip-flops are in the same domain. -

      -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_random_resistance.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_random_resistance.spq deleted file mode 100644 index d693ab4..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_dsm_random_resistance.spq +++ /dev/null @@ -1,58 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// Goal Name : dft_dsm_random_resistance -// Version : 5.5.0 -// -// Revision History: -// Ver Date Comments -// 5.5.0 11-Jun-2015 Initial version -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_dsm_random_resistance -* -Reduce the random resistance of the design -* - For both stuck-at and transition faults, the presence of hard to detect -faults has a substantial impact on overall ATPG performance. The ability -to measure the density of hard to detect faults in a design early at the -RTL stage is valuable. It gives the opportunity to make design changes -to address the issue, and enables to quickly measure the impact of the -changes. One of the best predictors of the presence of hard to detect -faults is the random resistance of a design. This template contains -rules that address the special needs of such topics - - For more details about this goal, please refer to the -SpyGlass-DFT-DSM-Methodology.pdf file in the doc -subdirectory of your SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=dft_dsm,dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Info_random_resistance // Does the random resistive analysis for the circuit - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready-08.jpg b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready-08.jpg deleted file mode 100644 index f4247cebaf6757bd9a790489ffb622aa4a613d85..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 73154 zcmbrl2T)Ug*De}FMFd5q7m3oVNbf{Nx`6af{)%(~>76JDNR4!*BfU!r9U@&oMF ze}Ib_fa>3G|D(@eA^#%*e^0*n2Dp8Vg71 zT%x>ugzP*17NoRmnbMHFI}d*a^>=6^3kE>-vO6zU%7K%{P9(KgBMg>o(vN2 zk_xVIKdI|xG#tb7NWSz6r@qd_%)-jX%f~MuC?q8DgbqC;*iI<+6Vp_P^P6 zn{3ym%a5^rPtVX zCLSpaFYd2t|FZ1=n_=PqzbyMN!~P$;Pykv=3Nm<_Q z^gTyuew?dLo3R`bqUMgpxD`Jf;&F_AnkuZo$@g|KI>`+MZ1t5WMDch4|<*`q6 zJ>Y&y?1bI0vz{b~UjVM9t)!P?T73C&SB{S2dSCp5@*!C}{`fTnZ!AdIb$hCDiA&Z? z+*}5XHL%KxYpKrbxjta=;K?W1^nELX`ns`|>kCY51sw-QRLhC19BY>mE;APZGj`MY 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    - -
    -

    -dft_scan_ready -

    -
      -
    • Run the dft_scan_ready goal.
      • -
    • A flip-flop is considered as scannable if during scanshift:
      • -
        -
      • Its clock can be controlled by a testclock (checked by DFT rule Clock_11) and
        • -
      • Its set and reset pins (if any) are forced inactive (checked by DFT rule Async_07)
        • -
      -
    • These two rules may be violated either because test logic has not yet been designed in or because the constraint file has missing or incorrect entries. If there are violations of either rule, then diagnostic rules Diagnose_testclock and Diagnose_testmode can be used to diagnose the cause.
      • -
    • Any non-scannable flip-flop will reduce the coverage for logic that only feeds that flip-flop as well as logic that is only driven by that flip-flop.
      • -
    • The dft_scan_ready goal also checks that testmode signals that only control asynchronous set or reset pins should be unrestricted during capture. (checked by DFT rule Async_08)
      • -
        -
      • Restricting such a dedicated signal would result in the set/reset nets not being tested thoroughly.
        • -
      • Such a violation can be fixed by adding the -scanshift argument to the test_mode constraint to indicate that the constraint only applies during shifting and is a don't care otherwise.
        • -
      -
    -

    -Clock_11 Debug -

    -

    -Clock_11 violations detect clock sources (see the description of Clock_11 in the SpyGlass DFT User Guide section on Clock Rules) that are not controlled by test clocks. Each violation indicates the number of flip-flops clocked by this source. Selecting any violation will highlight the source on the schematic. Following is an example shown in the Incremental Schematic. -

    -

    -

    -

    - -

    -

    -The testclock propagation through the 'Show Case Analysis' mechanism appears automatically in the schematic. -

    -

    -You will realize that the testclock propagation stops somewhere in the design: -

    -

    -

    -

    - -

    -

    -In this example it is clear that the other input of the AND gate should be held at '1' to enable the clock to pass through. The designer applies a 'test_mode' constraint to rectify the situation. -

    -

    -Async_07 Debug -

    -

    -Async_07 violations detect async sources (see the description of Async_07 in the SpyGlass DFT User Guide section on Asynchronous Rules) that are not rendered inactive during scanshift. -

    -
      -
    • Select a violation and display in the MS.
      • -
    • The testmode value propagation appears automatically on the schematic.
      • -
    • Visually find out the root cause why the async source of the flip-flops is held at 'X' or at the active value. This will lead to the conclusion about how possibly a test_mode constraint can be applied to rectify the Async_07 violation.
      • -
    -

    -In the example below, the schematic shows no constraint was applied on the rst input pin of the design: -

    -

    -

    -

    - -

    -

    -Viewing the estimate of fault coverage of the design -

    -

    -The rule Info_coverage estimates the fault/test coverage of the design. The generated reports help in understanding the test health of the design. The following fault browser helps understand the relative testability scores achieved in the design. -

    -

    -

    -

    - -

    -

    -The following summary reported generated at this stage helps understand the fault status. -

    -

    -

    -

    - -

    -

    -One may also, optionally, generate a detailed fault report, similar to ATPG, as follows. This report generation is under the control of a switch. Enable this by specifying the following parameter: -

    -

    -set_parameter dftGenerateStuckAtFaultReport all -

    -

    -

    -

    - -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_setup.sgs deleted file mode 100644 index 3e533ac..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_setup.sgs +++ /dev/null @@ -1,5 +0,0 @@ -set_property -step_header "Testclocks for scan" -set_constraints -constraints {clock test_mode} -html $SPYGLASS_HOME/.Methodology/DFT/doc/DFT3121.htm -##### -set_property -step_header "Asynchronous sets and resets for scan" -set_constraints -constraints {test_mode} -html $SPYGLASS_HOME/.Methodology/DFT/doc/DFT3122.htm diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/.submethodology_help deleted file mode 100644 index 8217a1b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/.submethodology_help +++ /dev/null @@ -1,23 +0,0 @@ -lint_rtl - This goal checks; - - Basic connectivity issues in the design, such as floating input, width mismatch, etc. - - Simulation issues such as incomplete sensitivity list, incorrect use of blocking/non-blocking - assignments, potential functional errors possible simulation hang cases, and simulation race cases - - Structural issues in the design that affect the post-implementation functionality or - performance of the design. Examples include multiple drivers, high fan-in mux, and - synchronous/asynchronous use of resets. - - Synthesizable constructs in the design and code which can cause RTL vs. gate simulation mismatch. - - Ideally this goal should be run before checking in new RTL changes. - -design_audit (Optional) - This goal provides design audit information. The aim of this goal is to gather statistics - of the design. These may include information on the Top level design, Black/Gray Boxes, - Parameters/Generics etc, and information on the design size, control signals etc. - -clock_reset_integrity -The aim of this goal is to check the integrity of clock and reset architecture in the design. -Such as the following; - * Possible race condition between clock and enable of FFs - * Complex Issues like Gated Clock or deep ripple clock divider - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit.spq deleted file mode 100644 index d6a57dd..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit.spq +++ /dev/null @@ -1,126 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : design_audit -// Version: 2.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 31-May-2013 5.1 Removed Following Rules: -// Audit2Stats2 -// Added following Rules: -// Audit2Stats3 -// 2.0.0 30-May-2014 5.3 Guidware 2.0 Content Consistency -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint/design_audit -* -Reports informational data related to design - -* -This goal helps in profiling the block, as well as gathering some useful -statistics for the design. It may not be needed when RTL is still being actively -coded. However, when RTL is somewhat complete, this information is useful to get -an overall profile of the design. -In later stages of RTL development, a sudden change in design characteristics -(say, number of FFs) may point to unintended or non-optimal bug-fix. This -goal should be run once per week. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=Audits,area,erc,clock-reset,spyglass,starc,lint,morelint - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --sel_case_analysis_mode="direct" - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Audit2Stats7a // Gives the libraries that are declared but not used in the design unit --overloadrules Audit2Stats7a+severity=Info - --rules Audit2ID // Gathers stats for design. Do not select this rule directly --overloadrules Audit2ID+severity=Data - --rules Audit2Stats // Evaluates the number of input, output and inout ports in a module --overloadrules Audit2Stats+severity=Data - --rules Audit2Stats3 // Evaluates the sum total of each of one-dimensional and multi-dimensionalbuses used in a design on rtl level --overloadrules Audit2Stats3+severity=Data - --rules Audit2Stats4 // Dumps the generic used per entity. --overloadrules Audit2Stats4+severity=Info - --rules Audit2Stats7b // Gives all the libraries declared for entity and architecture. --overloadrules Audit2Stats7b+severity=Info - --rules Audit2Stats8 // Evaluates the number of times each blackbox is instantiated. --overloadrules Audit2Stats8+severity=Info - --rules Audit4ID // Gathers stats for design. Do not select this rule directly --overloadrules Audit4ID+severity=Data - --rules DirectiveCheck-ML // Rule dumps information about ifdef, undef and include directives used in design --overloadrules DirectiveCheck-ML+severity=Data - --rules PragmaComments-ML // Pragma Comments have been detected. --overloadrules PragmaComments-ML+severity=Data - --rules STARC-1.6.6.3 // Do not directly instantiate cells in the design --overloadrules STARC-1.6.6.3+severity=Info - --rules Audit2Stats5 // Dumps the data regarding line of codes, lines of comment, per architecture. --overloadrules Audit2Stats5+severity=Data - --rules Audit2Stats6 // Dumps the data regarding line of codes, lines of comment, for entire design --overloadrules Audit2Stats6+severity=Data - --rules Audit2FileNameDump // Dumps the information regarding which module is defined in which file. --overloadrules Audit2FileNameDump+severity=Data - --rules ReportPortInfo-ML // Generate a report of all ports of top level block and black-box instances. --overloadrules ReportPortInfo-ML+severity=Data - --rules RegInputOutput-ML // Module output and input port should be registered --overloadrules RegInputOutput-ML+severity=Data --chkTopModule="yes" // Rule checkign will be done only for top module - --rules W438 // Tri-state used below top-level of design --overloadrules W438+severity=Info - --rules GateCount // Reports Gate count and Instance Count for the complete hierarchy of design --overloadrules GateCount+severity=Data --rptallmodulegatecount="yes" // This parameter helps user to dump gate count of all modules in vdb file. - --rules Audit4Dump // Dumps the information regarding number of flip-flops, latches and tristates(evaluated in rule Audit4count) on stdout. --overloadrules Audit4Dump+severity=Data - --rules AuditReportCell // Dumps the information regarding library cells - --rules listTristateBuses // List all tristate busses used in the design. - --rules Clock_info01 // Reports likely clock signals - --rules Reset_info01 // Reports likely asynchronous and synchronous preset and clear signals - --rules Setup_clock01 // Generates information needed for Clock Setup - --rules Audit4Count // Evaluates the number of Flip-flops, latches and tristates in a moduleThis is done on flat level netlist --overloadrules Audit4Count+severity=Data diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit_debug_help.htm deleted file mode 100644 index d6817e4..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/design_audit_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - block_profile - - - - - - - - - - - - - -
    - -
    -

    -block_profile -

    -

    -This goal helps in profiling the block, as well as gathering some useful statistics for the design. It may not be needed when RTL is still being actively coded. However, when RTL is somewhat complete, this information is useful to get an overall profile of the design. In later stages of RTL development, a sudden change in design characteristics (say, number of FFs) may point to unintended or non-optimal bug-fix. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract.spq deleted file mode 100644 index a1f85c7..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract.spq +++ /dev/null @@ -1,46 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : lint_abstract -// Version: 2.0.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 2.0.0 30-May-2014 5.3 Guidware 2.0 Content Consistency -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_abstract -* -Generates relevant base policy(lint) constraints for block abstraction -* -This goal helps in generating an abstracted model of a block. The abstracted -model will be used during SoC-level validation and verification. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=lint - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --block_abstract --rules LINT_abstract01 // Generates relevant base policy constraints for block abstraction diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract_debug_help.htm deleted file mode 100644 index d5377b8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_abstract_debug_help.htm +++ /dev/null @@ -1,69 +0,0 @@ - - - - - - - - - - lint_abstract - - - - - - - - - - - - - -
    - -
    -

    -lint_abstract -

    -

    -The aim of this goal is to generate abstract model of a block. This goal reports an informational message by rule LINT_abstract01, which points to the SGDC file containing abstract model. - -

    -

    -Use generated abstract models of blocks at SoC level for lint verification and abstraction validation checks. You can provide the generated abstract model just with the RTL interface of blocks, without full definitions of blocks. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_functional_rtl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_functional_rtl.spq deleted file mode 100644 index c33863c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_functional_rtl.spq +++ /dev/null @@ -1,81 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : lint_functional_rtl -// Version: 5.6.1 -// -// Revision History: -// Ver Date Comments -// 1.0.0 26-Nov-2014 Initial version -// 5.4.1 04-Mar-2015 Made following changes -// Removed arg: +syntharg -ignoreHanginFF -// Added use_inferred_clocks & use_inferred_resets -// -// 5.5.0 16-Apr-2015 Added Av_signed_unsigned_mismatch and Av_width_mismatch_expr -// -// 5.6.0 18-Nov-2015 5.6 Added Following Rules -// Rule Name Policy GW Type -// =============================================== -// Av_width_mismatch_expr02 auto-verify MUST -// Av_width_mismatch_expr03 auto-verify MUST -// Av_dontcare_mismatch auto-verify MUST -// Av_case_default_missing auto-verify MUST -// Av_case_default_redundant auto-verify MUST -// -// 5.6.1 29-Mar-2015 Removed use_inferred_resets & use_inferred_clocks -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_functional_rtl mixed -* -Helps identify width related issues in assignment, case expression-select, instance -port connection and function arguments using functional analysis -* -This goal uses functional analysis to identify width related issues in the design. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ --policies=auto-verify - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ --nocheckoverflow='yes' // Width will be calculated as per LRM rather best fit. - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ --rule=Av_Info_Case_Analysis // Highlights case-analysis settings - --rule=Av_width_mismatch_assign // LHS width is less than RHS width of assignment (Truncation) - --rule=Av_width_mismatch_case // Case expression width does not match case select expression width - --rule=Av_width_mismatch_port // Instance port connection has different width compared to the port definition - --rule=Av_width_mismatch_function // Bit-width of function call arguments must match bit-width of the corresponding function definition arguments - -// Do not mix signed & unsigned variables/constants in expressions, assignment statements or in comparisons --rule=Av_signed_unsigned_mismatch - -//Bit-width of operands of a logical operator must match --rule=Av_width_mismatch_expr - --rule=Av_case_default_missing // A case statement(or selected signal assignment) does not have a default clause - --rule=Av_width_mismatch_expr03 // Unequal length in arithmetic comparison operator - --rule=Av_width_mismatch_expr02 // Unequal length operands in bit wise logical/arithmetic/relational operator - --rule=Av_dontcare_mismatch // Use of don't-care except in case labels may lead to simulation/synthesis mismatch - --rules Av_case_default_redundant // A case statement marked full_case or a priority/unique case statement have a default clause. - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl.spq deleted file mode 100644 index ea8301f..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl.spq +++ /dev/null @@ -1,611 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : lint_rtl -// Version: 5.6.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 31-May-2013 5.1 Severity of following rules changed to Data: -// PragmaComments-ML -// ReportPortInfo-ML -// RegInputOutput-ML -// 2.0.0 30-May-2014 5.3 Guidware 2.0 Content Consistency -// 2.1.0 30-Sep-2014 5.4 Removed rule ArrayEnumIndex -// 5.4.1 26-Feb-2015 5.4.1 Added enable_fast_traversal switch for better performance of synthesis based rules. -// -// 5.6.0 18-Nov-2015 5.6 Added Following Rules -// Rule Name Policy GW Type -// =============================================== -// STARC05-2.10.1.4a starc2005 MUST -// STARC05-2.10.1.4b starc2005 MUST -// W156 lint MUST -// STARC05-2.3.3.1 starc2005 MUST -// W415a lint OPTIONAL -// W287b lint OPTIONAL -// W224 lint OPTIONAL -// W287a lint OPTIONAL -// W528 lint OPTIONAL -// mixedsenselist lint OPTIONAL -// W339a lint OPTIONAL -// STARC05-2.10.3.2a starc2005 OPTIONAL -// Removed Following Rules -// Rule Name Policy GW Type -// =============================================== -// DuplicateCaseLabel-ML morelint MUST -// STARC05-2.3.4.2 starc2005 OPTIONAL -// -// 2018.09 10-Sep-2018 2018.09 Added Following Rules -// Rule Name Policy GW Type -// =============================================== -// NoFeedThrus-ML morelint MUST -// STARC05-2.8.3.3 starc2005 MUST -// UndrivenOutTermNLoaded-ML morelint MUST -// UndrivenOutPort-ML morelint MUST -// W146 lint MUST -// W188 lint MUST -// W401 lint MUST -// W402b lint MUST -// W468 lint MUST -// W527 lint MUST -// W576 lint MUST -// CheckShiftOperator-ML morelint OPTIONAL -// HangingInstOutput-ML morelint OPTIONAL -// ResetFlop-ML morelint OPTIONAL -// SelfDeterminedExpr-ML morelint OPTIONAL -// UndrivenNet-ML morelint OPTIONAL -// UnrecSynthDir-ML morelint OPTIONAL -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_rtl -* -Checks the design for basic Connectivity issues -Checks the design for basic Simulation issues -Checks the design for recommended design practices and Structural issues -Checks the design for basic Synthesis issues - -* -This goal checks basic connectivity issues in the design, such as floating -input, width mismatch, etc. These checks should be run after every change in -RTL code prior to code check-in. -This goal checks simulation issues in the design, such as - - incomplete sensitivity list - - incorrect use of blocking/ non-blocking assignments - - potential functional errors - - possible simulation hang cases, and - - simulation race cases -These checks should be run, and reported messages should be reviewed prior to -all simulation runs. -This goal identifies the structural issues in the design that affect the -post-implementation functionality or performance of the design. Examples include -multiple drivers, high fan-in mux, and synchronous/asynchronous use of resets. -These checks should be run once every week and before handoff to implementation. -This goal reports unsynthesizable constructs in the design and code which can -cause RTL vs. gate simulation mismatch. These checks should be run twice a week, -and before handoff to synthesis team. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=openmore,starc,starc2005,erc,simulation,lint,latch,spyglass,morelint,timing - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ --enable_fast_traversal - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --strict=W342,W343 // Rules will do strict checking --new_flow_width='yes' // Enable all nex fixes made in width rules --nocheckoverflow='yes' // Width will be calculated as per LRM rather best fit. --report_inferred_cell="yes" // if parameter set to "yes" then rules will flag for only inferred flops and not for instantiated flops. - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - -//-rules AllocExpr // Allocator expression may not be synthesizable - --rules badimplicitSM1 // Unsynthesizable modeling style for a sequential logic. Clock and reset cannot be inferred - --rules badimplicitSM2 // Unsynthesizable implicit sequential logic: states can only be updated on same clock phase - --rules badimplicitSM4 // Unsynthesizable implicit sequential logic: event control expression may not have more than one edge - --rules BlockHeader // PORT/GENERIC used in block statement header may be unsynthesizable - --rules bothedges // Both edges of the same variable are not allowed in the event control list - -//-rules DisconnSpec // Disconnect specification is ignored by synthesis tools. - -//-rules ForLoopWait // WAIT statements used inside a FOR-loop may be unsynthesizable - -//-rules IncompleteType // Incomplete type declaration may not be synthesizable - -//-rules Info_Case_Analysis // Highlights case-analysis settings - -//-rules IntGeneric // Non-integer type used in the declaration of a generic may be unsynthesizable - -//-rules LinkagePort // Linkage port may not be synthesizable - -//-rules LoopBound // For loop range bounds should either be locally static or globally static -//-rules NoTimeOut // Timeout expression in wait statement may not be synthesizable - -//-rules PortType // Port of unconstrained type detected. This may not be synthesizable - -//-rules PreDefAttr // Use of certain pre-defined attributes may not be synthesizable - -//-rules ResFunction // Resolution functions may not be synthesizable - --rules STARC05-2.1.6.5 // For an array index x and z should not be used --overloadrules STARC05-2.1.6.5+severity=Warning - --rules STARC05-2.3.1.2c // Do not use unsynthesizable User-Defined Primitives (UDPs). --overloadrules STARC05-2.3.1.2c+severity=Error - -//-rules UserDefAttr // Use of user-defined attribute may not be synthesizable - -//-rules W182g // tri0 declarations may not be synthesizable - -//-rules W182h // tri1 declarations are not synthesizable - -//-rules W182k // trireg declarations are not synthesizable - -//-rules W182n // Switches such as cmos, pmos & nmos are not synthesizable - --rules W421 // Always block/process does not have event control --overloadrules W421+severity=Error - --rules W442a // Reset sequence may not be synthesizable. First statement in block mustbe an if statement - --rules W442b // Reset sequence may not be synthesizable. The reset condition is too complex - --rules W442c // Reset sequence may not be synthesizable. Reset can only be modified by! or ~ in the if condition - --rules W442f // The specified reset sequence may not be synthesizable. Only binary operators that canbe used in 'if' are '==' and '!=' - -//-rules SignedUnsignedExpr-ML // Do not mix signed & unsigned variables/constants in expressions, assignment statements or in comparisons. - -//-rules sim_race01 // Assignment and use of signal in same simulation cycle (Read-Write Race) -//-overloadrules sim_race01+severity=Warning - --rules sim_race02 // Multiple assignments to a signal --overloadrules sim_race02+severity=Warning - --rules W110a // Use same port index bounds in component instantiation and entity declaration - -//-rules W239 // Hierarchical references may not be synthesizable - --rules W416 // Range of return type and return value of a function should be same --overloadrules W416+severity=Error - -//-rules BothPhase // Process has a clock driving it on both edges - may not be synthesizable - --rules CheckDelayTimescale-ML // Delay used without timescale compiler directive - -//-rules ClockStyle // A clocking style is used which may not be synthesizable - -//-rules DiffTimescaleUsed-ML // Design should not have different timescales for different modules - -//-rules MultipleWait // Multiple wait statements having same clock expression may not be synthesizableby some synthesis tools - -//-rules NoSigCaseX-ML // Design should not use signals in casex and casez constructs - --rules PragmaComments-ML // Pragma Comments have been detected. --overloadrules PragmaComments-ML+severity=Data - -//-rules SetBeforeRead-ML // Variable may not be set before being read - -//-rules SigVarInit // Initial values of signals and variables will be ignored by some synthesis tools - -//-rules STARC05-2.1.2.5v // Do not use attribute enum_encoding - -//-rules STARC05-2.1.8.6 // Global signals must not be read in a subprogram description - --rules STARC05-2.10.2.3 // Global signals must not be read in a subprogram description --overloadrules STARC05-2.10.2.3+severity=Warning - -//-rules STARC05-2.10.3.7 // Global signals must not be read in a subprogram description - --rules STARC05-2.11.3.1 // Global signals must not be read in a subprogram description --overloadrules STARC05-2.11.3.1+severity=Warning - -//-rules STARC05-2.3.1.4 // Paths other than flip-flop data paths must not have delays - --rules STARC05-2.3.1.5b // Delay values must be non-negative. --overloadrules STARC05-2.3.1.5b+severity=Error - -//-rules STARC05-2.3.2.4 // Variables if used, must be assigned to a signal before the end of the process - -//-rules SynthIfStmt // IF-statement may not be synthesizable - -//-rules W127 // Delay values should not contain X(unknown value) or Z(high-impedance state) - -//-rules W129 // Variable delay values should be avoided - -//-rules W182c // time declarations are not synthesizable - -//-rules W189 // Nested Synopsys translate_off comments - -//-rules W190 // Task or procedure declared but not used - -//-rules W213 // PLI Task/Functions are not synthesizable - --rules W215 // Inappropriate bit select for integer or time variable - --rules W216 // Inappropriate range select for integer or time variable - -//-rules W226 // Case select expression is constant - -//-rules W245 // Probably intended "or", not "|" or "||" in sensitivity list - -//-rules W250 // The disable statement may not be synthesizable - -//-rules W253 // Data event has an edge - -//-rules W254 // Reference event does not have an edge - -//-rules W280 // A delay has been specified in a non-blocking assignment - --rules W289 // A real operand is being used in a logical comparison --overloadrules W289+severity=Error - --rules W292 // Comparison of Real operands is not recommended - --rules W293 // A function returns a real value, which is unsynthesizable --overloadrules W293+severity=Error - -//-rules W294 // Real variables are unsynthesizable - --rules W317 // Assignment to a supply net - --rules W352 // The condition inside a "for" statement is constant --overloadrules W352+severity=Error - --rules W398 // A case choice is covered more than once in a case statement --overloadrules W398+severity=Error - --rules W422 // Unsynthesizable process: event control has more than one clock --overloadrules W422+severity=Error - --rules W424 // Function or subprogram sets a global signal/variable - -//-rules W425 // Function or sub-program uses a global signal/variable - --rules W426 // Task sets a global variable - -//-rules W427 // Task uses a global variable - -//-rules W430 // The "initial" statement is not synthesizable - -//-rules W443 // 'X' value used -//-overloadrules W443+severity=Warning - -//-rules W444 // 'Z' or '?' value used -//-overloadrules W444+severity=Warning - -//-rules W464 // Unrecognized synthesis directive used in the design - --rules W467 // Use of don't-care except in case labels may lead to simulation/synthesis mismatch - --rules W480 // Loop index is not of type integer - --rules W481a // Possibly unsynthesizable loop: step variable differs from variable used in condition - --rules W481b // Unsynthesizable loop: step variable differs from variable used in initialization - --rules W496a // Comparison to a tristate in a condition expression is treated as false in synthesis. - --rules W496b // Comparison to a tristate in a case statement is treated as false in synthesis. - --rules W71 // A case statement(or selected signal assignment) does not have a default orOTHERS clause --overloadrules W71+severity=Error - -//-rules WhileInSubProg // While statements used inside subprograms may be unsynthesizable - -//-rules ArrayIndex // Bus signals are declared with low-order bit first --checkalldimension="yes" // Rule will check all dimensions of signal packed and unpacked. - -//-rules DisallowCaseX-ML // Design should not use casex constructs - -//-rules DisallowCaseZ-ML // Design should not use casez constructs - -//-rules DisallowXInCaseZ-ML // casez statement should not use "x" - --rules NoAssignX-ML // RHS of the assignment contains 'X' - --rules NoXInCase-ML // Case expression and case choices should not have 'X' - -//-rules ParamOverrideMismatch-ML // Mismatch in the number of parameter over-rides and number of parameters in theinstantiated module -//-overloadrules ParamOverrideMismatch-ML+severity=Warning - --rules ParamWidthMismatch-ML // Parameter width does not match with the value assigned --overloadrules ParamWidthMismatch-ML+severity=Warning - --rules ReportPortInfo-ML // Generate a report of all ports of top level block and black-box instances. --overloadrules ReportPortInfo-ML+severity=Data - --rules STARC05-2.1.3.1 // Bit-width of function arguments must match bit-width of the correspondingfunction inputs. --overloadrules STARC05-2.1.3.1+severity=Warning - --rules STARC05-2.1.5.3 // Conditional expressions should evaluate to a scalar. --overloadrules STARC05-2.1.5.3+severity=Warning - --rules STARC05-2.2.3.3 // Do not assign over the same signal in an always construct for sequential circuits --overloadrules STARC05-2.2.3.3+severity=Warning - --rules STARC05-2.3.1.6 // Same logic level of reset signal must be checked as specified in the sensitivitylist of the always block. --overloadrules STARC05-2.3.1.6+severity=Warning - -//-rules STARC05-2.3.2.2 // Do not use blocking and non-blocking assignments together in same alwaysblock. - --rules W110 // An instance port connection has incompatible width compared to the port definition --overloadrules W110+severity=Error - -//-rules W111 // Not all elements of an array are read - --rules W116 // Unequal length operands in bit wise logical/arithmetic/relational operator - --rules W122 // A signal is read inside a combinational process but is not included in the sensitivity list --overloadrules W122+severity=Error - --rules W123 // A signal or variable has been read but is not set --overloadrules W123+severity=Error --ignoreModuleInstance="yes" // Ignore signals which are unset but used in port mapping. - -//-rules W159 // Condition contains a constant expression - -//-rules W164a // LHS width is less than RHS width of assignment (Truncation) -//-overloadrules W164a+severity=Warning - -//-rules W164b // LHS width is greater than RHS width of assignment (Extension) - --rules W19 // Truncation of extra bits --overloadrules W19+severity=Error - -//-rules W210 // Number of connections made to an instance does not match number of ports on master -//-overloadrules W210+severity=Warning - --rules W218 // Multi-bit signal used in sensitivity list --overloadrules W218+severity=Error - --rules W240 // An input has been declared but is not read --checkfullbus="yes" --checkfullrecord="yes" - -//-rules W241 // Output is never set - --rules W263 // A case expression width does not match case select expression width - --rules W337 // Illegal value (e.g. real) being used or X, Z or ? being used inappropriately asa case item - -//-rules W342 // Constant will be X-extended - -//-rules W343 // Constant will be Z-extended - --rules W362 // Unequal length in arithmetic comparison operator - -//-rules W423 // A port with a range is redeclared with a different range - -//-rules W446 // Output port signal is being read (within the module) -//-overloadrules W446+severity=Error - -//-rules W456a // A signal is included in the sensitivity list of a combinational process blockbut none of its bits is read in that block - --rules W486 // Shift overflow - some bits may be lost - -//-rules W491 // Constant will be ?-extended - --rules W499 // Not all bits of a function are set in the function - --rules W502 // A variable in sensitivity list is modified inside the always block - --rules W505 // Value assigned inconsistently - may not be synthesizable --overloadrules W505+severity=Error - -//-rules W551 // A case statement marked full_case or a priority/unique case statement have a default clause. - --rules W66 // Unsynthesizable repeat loop because repeat expression is not constant --overloadrules W66+severity=Error - --rules InferLatch // Latch inferred --overloadrules InferLatch+severity=Error - --rules RegInputOutput-ML // Module output and input port should be registered --overloadrules RegInputOutput-ML+severity=Data --chkTopModule="yes" // Rule checkign will be done only for top module - --rules STARC05-2.3.4.1v // Flip-flop output must not have initial value in signal/variable declaration --overloadrules STARC05-2.3.4.1v+severity=Warning - -//-rules STARC05-2.3.6.1 // Do not mix descriptions of flip-flops with asynchronous reset and flip-flopswithout asynchronous reset in the same process/always block - --rules STARC05-2.5.1.7 // Tri State output should not be used in the conditional expression of if statement --overloadrules STARC05-2.5.1.7+severity=Warning - --rules STARC05-2.5.1.9 // Tri State output should not be entered in the selection expression of casex and casez statement --overloadrules STARC05-2.5.1.9+severity=Warning - --rules STARC05-2.10.3.2a // Bit-width of operands of a logical operator must match. - -//-rules UseMuxBusses // Tristate nets detected -//-overloadrules UseMuxBusses+severity=Warning - --rules W336 // Blocking assignment should not be used in a sequential block (may lead to shoot through) --overloadrules W336+severity=Error - --rules W414 // Use of non-blocking assignment in a combinational block --overloadrules W414+severity=Error --treat_latch_as_combinational="yes" // Always block inferring latch will be treated as combinational block. - -//-rules W428 // Task called in a combinational block - --rules W450L // Multi-bit expression used as latch enable may not be synthesizable --overloadrules W450L+severity=Warning - --rules UndrivenInTerm-ML // Undriven but loaded input terminal of an instance detected --overloadrules UndrivenInTerm-ML+severity=Error --checkInHierarchy="yes" // Rule will dive down the hierarchy to look for driver --checkRTLCInst='yes' // Rule will report violation for RTLC instances - -//-rules UndrivenNUnloaded-ML // Undriven and Unloaded nets/terminals detected in the design - -//-rules UnloadedInPort-ML // Unloaded but driven input port of a module detected - -//-rules LogicDepth // Logic depth exceeds specified number of levels (using parameter delaymax/delaymax_memtoflop/delaymax_floptomem/delaymax_memtomem/delaymax_err/delaymax_inputtoflop/delaymax_floptoflop/delaymax_inputtooutput/delaymax_floptooutput) -//-delaymax=500 - --rules BufClock // Clock buffer detected --overloadrules BufClock+severity=Warning - --rules checkPinConnectedToSupply // IO-ports or Output ports of cells/modules may not be connected to supply signals. --overloadrules checkPinConnectedToSupply+severity=Error - -//-rules ClockEdges // Do not use both levels of the clock to drive latches - --rules CombLoop // Combinational loop exists --overloadrules CombLoop+msgLabel=CombLoop+severity=Error --enableE2Q="yes" // Report comb loop from Enable to Q pin of flop. - -//-rules DisabledAnd // And/Nand gate is disabled - -//-rules DisabledOr // Or/Nor gate is disabled - --rules FlopClockConstant // Flip-flop clock pin driven by a constant value --overloadrules FlopClockConstant+msgLabel=FlopClockConstant+severity=Error - -//-rules FlopDataConstant // Flip-flop data pin driven by a constant value - --rules FlopEConst // Flip-flop enable pin is permanently disabled or enabled - --rules FlopSRConst // Flip-flop set or reset pin is permanently enabled - -//-rules IntReset // Internally generated reset detected -//-overloadrules IntReset+msgLabel=IntReset+severity=Warning - -//-rules LatchDataConstant // Latch data pin driven by a constant value - -//-rules LatchEnableConstant // Latch enable pin driven by a constant value - --rules LatchFeedback // There should not be a combinational feedback path from a latch output to data or enable of the same latch. --overloadrules LatchFeedback+severity=Error - -//-rules LatchGatedClock // Do not use gated/internally generated clock to drive latches -//-overloadrules LatchGatedClock+msgLabel=LatchGatedClock+severity=Warning - -//-rules LatchReset // Reset pin should not be used both synchronously and asynchronously - -//-rules LogNMux // LogN mux with large number of inputs detected - potential performance problem -//-logmux_max=5 - -//-rules MuxSelConst // Mux select is constant. - -//-rules RegOutputs // Some outputs from a top module are not registered -//-overloadrules RegOutputs+severity=Warning --reportundrivenout='no' // Rule will not report violation for undriven outputs. - -//-rules SetResetConverge-ML // Fanin cone of Set and Reset pin of a flop/latch converge - --rules STARC05-1.2.1.2 // Do not create a RS latch using primitive cells such as AND, OR --overloadrules STARC05-1.2.1.2+severity=Error - --rules STARC05-1.3.1.3 // Asynchronous reset/preset signals must not be used as non-reset/preset orsynchronous reset/preset signals --overloadrules STARC05-1.3.1.3+severity=Warning - -//-rules STARC05-1.3.1.7 // A flip-flop must not have both asynchronous set and asynchronous reset - --rules STARC05-1.4.3.4 // Flip-flop clock signals must not be used as non-clock signals --overloadrules STARC05-1.4.3.4+severity=Warning - --rules STARC05-2.1.4.5 // Flip-flop clock signals must not be used as non-clock signals --overloadrules STARC05-2.1.4.5+severity=Warning - --rules STARC05-2.4.1.5 // Do not use two level latches in the same phase clock --overloadrules STARC05-2.4.1.5+severity=Error - --rules STARC05-2.5.1.2 // Logic must not exist in tristate enable conditions - -//-rules STARC05-2.5.1.4 // A tristate bus should not be driven by more than the specified number of drivers -//-overloadrules STARC05-2.5.1.4+severity=Warning - -//-rules TristateConst // Tristate gate enable is constant - -//-rules W391 // Design has a clock driving it on both edges - --rules W392 // Do not use a reset or set with both positive and negative polarity within the samedesign unit - --rules W415 // Variable/signal that does not infer a tristate and has multiple simultaneous drivers --overloadrules W415+msgLabel=W415+severity=Error --assume_driver_load="yes" // Rule will report violation for unloaded signals/variables. --checkconstassign="yes" // Rule will report violation for constant assignments - -//-rules W422L // Multiple clocks in the event control list of latch is not allowed -//-overloadrules W422L+msgLabel=W422L+severity=Warning - --rules STARC05-2.10.1.4a // Signals must not be compared with X or Z. - --rules STARC05-2.10.1.4b // Signals must not be compared with values containing X or Z. - --rules W156 // Do not connect buses in reverse order - --rules STARC05-2.3.3.1 // Do not use multiple clock signals in a single process block - --rules W415a // Signal may be multiply assigned (beside initialization) in the same scope. - --rules W287b // Output port of an instance is not connected - --rules W224 // Multi-bit expression found when one-bit expression expected - --rules W287a // Some inputs to instance are not driven or unconnected - --rules W528 // A signal or variable is set but never read - --rules mixedsenselist // Mixed conditions in sensitivity list may not be synthesizable - --rules W339a // Case equal operator (===) and case not equal (!==) operators may not be synthesizable - --rules NoFeedThrus-ML // Block should not contain feed-throughs - --rules STARC05-2.8.3.3 // Do not use //synopsys full_case pragma when all conditions are not described as case clause or the default clause is missing - --rules UndrivenOutTermNLoaded-ML // Undriven output pins connected to instance input - --rules UndrivenOutPort-ML // Undriven but loaded output port of a module detected - --rules W146 // Use named-association rather than positional association to connect to an instance - --rules W188 // Do not write to input ports - --rules W401 // Clock signal is not an input to the design unit - --rules W402b // Asynchronous set/reset signal is not an input to the module - --rules W468 // Index variable is too short - --rules W527 // Dangling else in sequence of if conditions. Make sure nesting is correct - --rules W576 // Logical operation on a vector - -// -rules CheckShiftOperator-ML // Logical and arithmetic shift operation detection on signed and unsigned operand(s) or expression(s) respectively - -// -rules HangingInstOutput-ML // Net connected to output port of instance is unconnected - -// -rules ResetFlop-ML // All the flip-flops should have either asynchronous set/reset or synchronous set/reset - -// -rules SelfDeterminedExpr-ML // Self-determined expression present in the design - -// -rules UndrivenNet-ML // Undriven but loaded net is detected in the design - -// -rules UnrecSynthDir-ML // Synthesis directive is not recognized - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_custom.tcl b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_custom.tcl deleted file mode 100644 index 0d4d338..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_custom.tcl +++ /dev/null @@ -1,114 +0,0 @@ -current_goal lint/lint_rtl -scenario optional -set_goal_option addrules AllocExpr -set_goal_option addrules DisconnSpec -set_goal_option addrules ForLoopWait -set_goal_option addrules IncompleteType -set_goal_option addrules Info_Case_Analysis -set_goal_option addrules IntGeneric -set_goal_option addrules LinkagePort -set_goal_option addrules LoopBound -set_goal_option addrules NoTimeOut -set_goal_option addrules PortType -set_goal_option addrules PreDefAttr -set_goal_option addrules ResFunction -set_goal_option addrules UserDefAttr -set_goal_option addrules W182g -set_goal_option addrules W182h -set_goal_option addrules W182k -set_goal_option addrules W182n -set_goal_option addrules SignedUnsignedExpr-ML -set_goal_option addrules sim_race01 -set_goal_option overloadrules sim_race01+severity=Warning -set_goal_option addrules W239 -set_goal_option addrules BothPhase -set_goal_option addrules ClockStyle -set_goal_option addrules DiffTimescaleUsed-ML -set_goal_option addrules MultipleWait -set_goal_option addrules NoSigCaseX-ML -set_goal_option addrules SetBeforeRead-ML -set_goal_option addrules SigVarInit -set_goal_option addrules STARC05-2.1.2.5v -set_goal_option addrules STARC05-2.1.8.6 -set_goal_option addrules STARC05-2.10.3.7 -set_goal_option addrules STARC05-2.3.1.4 -set_goal_option addrules STARC05-2.3.2.4 -set_goal_option addrules STARC05-2.3.4.2 -set_goal_option addrules SynthIfStmt -set_goal_option addrules W127 -set_goal_option addrules W129 -set_goal_option addrules W182c -set_goal_option addrules W189 -set_goal_option addrules W190 -set_goal_option addrules W213 -set_goal_option addrules W226 -set_goal_option addrules W245 -set_goal_option addrules W250 -set_goal_option addrules W253 -set_goal_option addrules W254 -set_goal_option addrules W280 -set_goal_option addrules W294 -set_goal_option addrules W425 -set_goal_option addrules W427 -set_goal_option addrules W430 -set_goal_option addrules W443 -set_goal_option overloadrules W443+severity=Warning -set_goal_option addrules W444 -set_goal_option overloadrules W444+severity=Warning -set_goal_option addrules W464 -set_goal_option addrules WhileInSubProg -set_goal_option addrules ArrayIndex -set_goal_option addrules DisallowCaseX-ML -set_goal_option addrules DisallowCaseZ-ML -set_goal_option addrules DisallowXInCaseZ-ML -set_goal_option addrules ParamOverrideMismatch-ML -set_goal_option overloadrules ParamOverrideMismatch-ML+severity=Warning -set_goal_option addrules STARC05-2.3.2.2 -set_goal_option addrules W111 -set_goal_option addrules W159 -set_goal_option addrules W164a -set_goal_option overloadrules W164a+severity=Warning -set_goal_option addrules W164b -set_goal_option addrules W210 -set_goal_option overloadrules W210+severity=Warning -set_goal_option addrules W241 -set_goal_option addrules W342 -set_goal_option addrules W343 -set_goal_option addrules W423 -set_goal_option addrules W446 -set_goal_option overloadrules W446+severity=Error -set_goal_option addrules W456a -set_goal_option addrules W491 -set_goal_option addrules W551 -set_goal_option addrules STARC05-2.3.6.1 -set_goal_option addrules UseMuxBusses -set_goal_option overloadrules UseMuxBusses+severity=Warning -set_goal_option addrules W428 -set_goal_option addrules UndrivenNUnloaded-ML -set_goal_option addrules UnloadedInPort-ML -set_goal_option addrules LogicDepth -set_parameter delaymax 500 -set_goal_option addrules ClockEdges -set_goal_option addrules DisabledAnd -set_goal_option addrules DisabledOr -set_goal_option addrules FlopDataConstant -set_goal_option addrules IntReset -set_goal_option overloadrules IntReset+msgLabel=IntReset+severity=Warning -set_goal_option addrules LatchDataConstant -set_goal_option addrules LatchEnableConstant -set_goal_option addrules LatchGatedClock -set_goal_option overloadrules LatchGatedClock+msgLabel=LatchGatedClock+severity=Warning -set_goal_option addrules LatchReset -set_goal_option addrules LogNMux -set_parameter logmux_max 5 -set_goal_option addrules MuxSelConst -set_goal_option addrules RegOutputs -set_goal_option overloadrules RegOutputs+severity=Warning -set_goal_option addrules SetResetConverge-ML -set_goal_option addrules STARC05-1.3.1.7 -set_goal_option addrules STARC05-2.5.1.4 -set_goal_option overloadrules STARC05-2.5.1.4+severity=Warning -set_goal_option addrules TristateConst -set_goal_option addrules W391 -set_goal_option addrules W422L -set_goal_option overloadrules W422L+msgLabel=W422L+severity=Warning -current_goal none diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_debug_help.htm deleted file mode 100644 index c25be63..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_rtl_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - lint_rtl - - - - - - - - - - - - - -
    - -
    -

    -lint_rtl -

    -

    -This goal checks basic RTL lint issues in the design, such as floating input, width mismatch, etc. These checks should be run after every change in RTL code prior to code check-in. -

    -

    -To debug these issues, cross probe the violation to the HDL code. The code fragment will have to be analyzed to figure out the root cause of width mismatch issues. For issues relating to floating inputs will have to be debugged in the schematic. On the schematic, the user would be directed to the floating input, and in some cases fanin/fanout analysis would have to done to find out the actual source of problem. If there are violations reported by the Info_Case_Analysis rule, review the set_case_analysis settings as these may impact the lint checks. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl.spq deleted file mode 100644 index 439471c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl.spq +++ /dev/null @@ -1,566 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : lint_turbo_rtl -// Version: 5.6.1 -// -// Revision History: -// Ver Date SG Ver Comments -// 5.4.1 26-Feb-2015 5.4.1 Initial version with following incremental changes over lint_rtl Goal: -// Added enable_fast_traversal switch for better performance of synthesis based rules. -// Added 4 new formal rules. -// SpyGlass Turbo Mode enabled. -// Goal will run under smart_rule_execution mode. -// -// 5.5.0 16-April-2015 5.5.0 Added Av_signed_unsigned_mismatch -// -// 5.6.0 18-Nov-2015 5.6 Added Following Rules -// Rule Name Policy GW Type -// =============================================== -// STARC05-2.10.1.4a starc2005 MUST -// STARC05-2.10.1.4b starc2005 MUST -// W156 lint MUST -// STARC05-2.3.3.1 starc2005 MUST -// W415a lint OPTIONAL -// W287b lint OPTIONAL -// W224 lint OPTIONAL -// W287a lint OPTIONAL -// W528 lint OPTIONAL -// mixedsenselist lint OPTIONAL -// W339a lint OPTIONAL -// STARC05-2.10.3.2a starc2005 OPTIONAL -// Av_width_mismatch_expr02 auto-verify MUST -// Av_width_mismatch_expr03 auto-verify MUST -// Av_dontcare_mismatch auto-verify MUST -// Av_case_default_missing auto-verify MUST -// Av_case_default_redundant auto-verify OPTIONAL -// Removed Following Rules -// Rule Name Policy GW Type -// =============================================== -// DuplicateCaseLabel-ML morelint MUST -// STARC05-2.3.4.2 starc2005 OPTIONAL -// -// 5.6.1 29-March-2016 5.6.1 Removed use_inferred_resets and use_inferred_clocks -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_turbo_rtl -* -Checks the design for basic Connectivity issues -Checks the design for basic Simulation issues -Checks the design for recommended design practices and Structural issues -Checks the design for basic Synthesis issues - -* -This goal checks basic connectivity issues in the design, such as floating -input, width mismatch, etc. These checks should be run after every change in -RTL code prior to code check-in. -This goal checks simulation issues in the design, such as - - incomplete sensitivity list - - incorrect use of blocking/ non-blocking assignments - - potential functional errors - - possible simulation hang cases, and - - simulation race cases -These checks should be run, and reported messages should be reviewed prior to -all simulation runs. -This goal identifies the structural issues in the design that affect the -post-implementation functionality or performance of the design. Examples include -multiple drivers, high fan-in mux, and synchronous/asynchronous use of resets. -These checks should be run once every week and before handoff to implementation. -This goal reports unsynthesizable constructs in the design and code which can -cause RTL vs. gate simulation mismatch. These checks should be run twice a week, -and before handoff to synthesis team. - -Few rules in this goals perform formal analysis before reporting violations. Also -goal run under turbo mode for better and optimized analysis. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=openmore,starc,starc2005,erc,simulation,lint,latch,spyglass,morelint,timing,auto-verify - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ --enable_fast_traversal --turbo --smart_rule_execution - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --strict=W342,W343 // Rules will do strict checking --new_flow_width='yes' // Enable all nex fixes made in width rules --nocheckoverflow='yes' // Width will be calculated as per LRM rather best fit. --report_inferred_cell="yes" // if parameter set to "yes" then rules will flag for only inferred flops and not for instantiated flops. - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - -//-rules AllocExpr // Allocator expression may not be synthesizable - --rules badimplicitSM1 // Unsynthesizable modeling style for a sequential logic. Clock and reset cannot be inferred - --rules badimplicitSM2 // Unsynthesizable implicit sequential logic: states can only be updated on same clock phase - --rules badimplicitSM4 // Unsynthesizable implicit sequential logic: event control expression may not have more than one edge - --rules BlockHeader // PORT/GENERIC used in block statement header may be unsynthesizable - --rules bothedges // Both edges of the same variable are not allowed in the event control list - -//-rules DisconnSpec // Disconnect specification is ignored by synthesis tools. - -//-rules ForLoopWait // WAIT statements used inside a FOR-loop may be unsynthesizable - -//-rules IncompleteType // Incomplete type declaration may not be synthesizable - -//-rules Info_Case_Analysis // Highlights case-analysis settings - -//-rules IntGeneric // Non-integer type used in the declaration of a generic may be unsynthesizable - -//-rules LinkagePort // Linkage port may not be synthesizable - -//-rules LoopBound // For loop range bounds should either be locally static or globally static -//-rules NoTimeOut // Timeout expression in wait statement may not be synthesizable - -//-rules PortType // Port of unconstrained type detected. This may not be synthesizable - -//-rules PreDefAttr // Use of certain pre-defined attributes may not be synthesizable - -//-rules ResFunction // Resolution functions may not be synthesizable - --rules STARC05-2.1.6.5 // For an array index x and z should not be used --overloadrules STARC05-2.1.6.5+severity=Warning - --rules STARC05-2.3.1.2c // Do not use unsynthesizable User-Defined Primitives (UDPs). --overloadrules STARC05-2.3.1.2c+severity=Error - -//-rules UserDefAttr // Use of user-defined attribute may not be synthesizable - -//-rules W182g // tri0 declarations may not be synthesizable - -//-rules W182h // tri1 declarations are not synthesizable - -//-rules W182k // trireg declarations are not synthesizable - -//-rules W182n // Switches such as cmos, pmos & nmos are not synthesizable - --rules W421 // Always block/process does not have event control --overloadrules W421+severity=Error - --rules W442a // Reset sequence may not be synthesizable. First statement in block mustbe an if statement - --rules W442b // Reset sequence may not be synthesizable. The reset condition is too complex - --rules W442c // Reset sequence may not be synthesizable. Reset can only be modified by! or ~ in the if condition - --rules W442f // The specified reset sequence may not be synthesizable. Only binary operators that canbe used in 'if' are '==' and '!=' - -//-rules SignedUnsignedExpr-ML // Do not mix signed & unsigned variables/constants in expressions, assignment statements or in comparisons. - -//-rules sim_race01 // Assignment and use of signal in same simulation cycle (Read-Write Race) -//-overloadrules sim_race01+severity=Warning - --rules sim_race02 // Multiple assignments to a signal --overloadrules sim_race02+severity=Warning - --rules W110a // Use same port index bounds in component instantiation and entity declaration - -//-rules W239 // Hierarchical references may not be synthesizable - --rules W416 // Range of return type and return value of a function should be same --overloadrules W416+severity=Error - -//-rules BothPhase // Process has a clock driving it on both edges - may not be synthesizable - --rules CheckDelayTimescale-ML // Delay used without timescale compiler directive - -//-rules ClockStyle // A clocking style is used which may not be synthesizable - -//-rules DiffTimescaleUsed-ML // Design should not have different timescales for different modules - -//-rules MultipleWait // Multiple wait statements having same clock expression may not be synthesizableby some synthesis tools - -//-rules NoSigCaseX-ML // Design should not use signals in casex and casez constructs - --rules PragmaComments-ML // Pragma Comments have been detected. --overloadrules PragmaComments-ML+severity=Data - -//-rules SetBeforeRead-ML // Variable may not be set before being read - -//-rules SigVarInit // Initial values of signals and variables will be ignored by some synthesis tools - -//-rules STARC05-2.1.2.5v // Do not use attribute enum_encoding - -//-rules STARC05-2.1.8.6 // Global signals must not be read in a subprogram description - --rules STARC05-2.10.2.3 // Global signals must not be read in a subprogram description --overloadrules STARC05-2.10.2.3+severity=Warning - -//-rules STARC05-2.10.3.7 // Global signals must not be read in a subprogram description - --rules STARC05-2.11.3.1 // Global signals must not be read in a subprogram description --overloadrules STARC05-2.11.3.1+severity=Warning - -//-rules STARC05-2.3.1.4 // Paths other than flip-flop data paths must not have delays - --rules STARC05-2.3.1.5b // Delay values must be non-negative. --overloadrules STARC05-2.3.1.5b+severity=Error - -//-rules STARC05-2.3.2.4 // Variables if used, must be assigned to a signal before the end of the process - -//-rules SynthIfStmt // IF-statement may not be synthesizable - -//-rules W127 // Delay values should not contain X(unknown value) or Z(high-impedance state) - -//-rules W129 // Variable delay values should be avoided - -//-rules W182c // time declarations are not synthesizable - -//-rules W189 // Nested Synopsys translate_off comments - -//-rules W190 // Task or procedure declared but not used - -//-rules W213 // PLI Task/Functions are not synthesizable - --rules W215 // Inappropriate bit select for integer or time variable - --rules W216 // Inappropriate range select for integer or time variable - -//-rules W226 // Case select expression is constant - -//-rules W245 // Probably intended "or", not "|" or "||" in sensitivity list - -//-rules W250 // The disable statement may not be synthesizable - -//-rules W253 // Data event has an edge - -//-rules W254 // Reference event does not have an edge - -//-rules W280 // A delay has been specified in a non-blocking assignment - --rules W289 // A real operand is being used in a logical comparison --overloadrules W289+severity=Error - --rules W292 // Comparison of Real operands is not recommended - --rules W293 // A function returns a real value, which is unsynthesizable --overloadrules W293+severity=Error - -//-rules W294 // Real variables are unsynthesizable - --rules W317 // Assignment to a supply net - --rules W352 // The condition inside a "for" statement is constant --overloadrules W352+severity=Error - --rules W398 // A case choice is covered more than once in a case statement --overloadrules W398+severity=Error - --rules W422 // Unsynthesizable process: event control has more than one clock --overloadrules W422+severity=Error - --rules W424 // Function or subprogram sets a global signal/variable - -//-rules W425 // Function or sub-program uses a global signal/variable - --rules W426 // Task sets a global variable - -//-rules W427 // Task uses a global variable - -//-rules W430 // The "initial" statement is not synthesizable - -//-rules W443 // 'X' value used -//-overloadrules W443+severity=Warning - -//-rules W444 // 'Z' or '?' value used -//-overloadrules W444+severity=Warning - -//-rules W464 // Unrecognized synthesis directive used in the design - --rules W467 // Use of don't-care except in case labels may lead to simulation/synthesis mismatch - --rules W480 // Loop index is not of type integer - --rules W481a // Possibly unsynthesizable loop: step variable differs from variable used in condition - --rules W481b // Unsynthesizable loop: step variable differs from variable used in initialization - --rules W496a // Comparison to a tristate in a condition expression is treated as false in synthesis. - --rules W496b // Comparison to a tristate in a case statement is treated as false in synthesis. - --rules W71 // A case statement(or selected signal assignment) does not have a default orOTHERS clause --overloadrules W71+severity=Error - -//-rules WhileInSubProg // While statements used inside subprograms may be unsynthesizable - -//-rules ArrayIndex // Bus signals are declared with low-order bit first --checkalldimension="yes" // Rule will check all dimensions of signal packed and unpacked. - -//-rules DisallowCaseX-ML // Design should not use casex constructs - -//-rules DisallowCaseZ-ML // Design should not use casez constructs - -//-rules DisallowXInCaseZ-ML // casez statement should not use "x" - --rules NoAssignX-ML // RHS of the assignment contains 'X' - --rules NoXInCase-ML // Case expression and case choices should not have 'X' - -//-rules ParamOverrideMismatch-ML // Mismatch in the number of parameter over-rides and number of parameters in theinstantiated module -//-overloadrules ParamOverrideMismatch-ML+severity=Warning - --rules ParamWidthMismatch-ML // Parameter width does not match with the value assigned --overloadrules ParamWidthMismatch-ML+severity=Warning - --rules ReportPortInfo-ML // Generate a report of all ports of top level block and black-box instances. --overloadrules ReportPortInfo-ML+severity=Data - --rules STARC05-2.1.3.1 // Bit-width of function arguments must match bit-width of the correspondingfunction inputs. --overloadrules STARC05-2.1.3.1+severity=Warning - --rules STARC05-2.1.5.3 // Conditional expressions should evaluate to a scalar. --overloadrules STARC05-2.1.5.3+severity=Warning - --rules STARC05-2.2.3.3 // Do not assign over the same signal in an always construct for sequential circuits --overloadrules STARC05-2.2.3.3+severity=Warning - --rules STARC05-2.3.1.6 // Same logic level of reset signal must be checked as specified in the sensitivitylist of the always block. --overloadrules STARC05-2.3.1.6+severity=Warning - -//-rules STARC05-2.3.2.2 // Do not use blocking and non-blocking assignments together in same alwaysblock. - --rules W110 // An instance port connection has incompatible width compared to the port definition --overloadrules W110+severity=Error - -//-rules W111 // Not all elements of an array are read - --rules W116 // Unequal length operands in bit wise logical/arithmetic/relational operator - --rules W122 // A signal is read inside a combinational process but is not included in the sensitivity list --overloadrules W122+severity=Error - --rules W123 // A signal or variable has been read but is not set --overloadrules W123+severity=Error --ignoreModuleInstance="yes" // Ignore signals which are unset but used in port mapping. - -//-rules W159 // Condition contains a constant expression - -//-rules W164a // LHS width is less than RHS width of assignment (Truncation) -//-overloadrules W164a+severity=Warning - -//-rules W164b // LHS width is greater than RHS width of assignment (Extension) - --rules W19 // Truncation of extra bits --overloadrules W19+severity=Error - -//-rules W210 // Number of connections made to an instance does not match number of ports on master -//-overloadrules W210+severity=Warning - --rules W218 // Multi-bit signal used in sensitivity list --overloadrules W218+severity=Error - --rules W240 // An input has been declared but is not read --checkfullbus="yes" --checkfullrecord="yes" - -//-rules W241 // Output is never set - --rules W263 // A case expression width does not match case select expression width - --rules W337 // Illegal value (e.g. real) being used or X, Z or ? being used inappropriately asa case item - -//-rules W342 // Constant will be X-extended - -//-rules W343 // Constant will be Z-extended - --rules W362 // Unequal length in arithmetic comparison operator - -//-rules W423 // A port with a range is redeclared with a different range - -//-rules W446 // Output port signal is being read (within the module) -//-overloadrules W446+severity=Error - -//-rules W456a // A signal is included in the sensitivity list of a combinational process blockbut none of its bits is read in that block - --rules W486 // Shift overflow - some bits may be lost - -//-rules W491 // Constant will be ?-extended - --rules W499 // Not all bits of a function are set in the function - --rules W502 // A variable in sensitivity list is modified inside the always block - --rules W505 // Value assigned inconsistently - may not be synthesizable --overloadrules W505+severity=Error - -//-rules W551 // A case statement marked full_case or a priority/unique case statement have a default clause. - --rules W66 // Unsynthesizable repeat loop because repeat expression is not constant --overloadrules W66+severity=Error - --rules InferLatch // Latch inferred --overloadrules InferLatch+severity=Error - --rules RegInputOutput-ML // Module output and input port should be registered --overloadrules RegInputOutput-ML+severity=Data --chkTopModule="yes" // Rule checkign will be done only for top module - --rules STARC05-2.3.4.1v // Flip-flop output must not have initial value in signal/variable declaration --overloadrules STARC05-2.3.4.1v+severity=Warning - -//-rules STARC05-2.3.6.1 // Do not mix descriptions of flip-flops with asynchronous reset and flip-flopswithout asynchronous reset in the same process/always block - --rules STARC05-2.5.1.7 // Tri State output should not be used in the conditional expression of if statement --overloadrules STARC05-2.5.1.7+severity=Warning - --rules STARC05-2.5.1.9 // Tri State output should not be entered in the selection expression of casex and casez statement --overloadrules STARC05-2.5.1.9+severity=Warning - -//-rules UseMuxBusses // Tristate nets detected -//-overloadrules UseMuxBusses+severity=Warning - --rules W336 // Blocking assignment should not be used in a sequential block (may lead to shoot through) --overloadrules W336+severity=Error - --rules W414 // Use of non-blocking assignment in a combinational block --overloadrules W414+severity=Error --treat_latch_as_combinational="yes" // Always block inferring latch will be treated as combinational block. - -//-rules W428 // Task called in a combinational block - --rules W450L // Multi-bit expression used as latch enable may not be synthesizable --overloadrules W450L+severity=Warning - --rules UndrivenInTerm-ML // Undriven but loaded input terminal of an instance detected --overloadrules UndrivenInTerm-ML+severity=Error --checkInHierarchy="yes" // Rule will dive down the hierarchy to look for driver --checkRTLCInst='yes' // Rule will report violation for RTLC instances - -//-rules UndrivenNUnloaded-ML // Undriven and Unloaded nets/terminals detected in the design - -//-rules UnloadedInPort-ML // Unloaded but driven input port of a module detected - -//-rules LogicDepth // Logic depth exceeds specified number of levels (using parameter delaymax/delaymax_memtoflop/delaymax_floptomem/delaymax_memtomem/delaymax_err/delaymax_inputtoflop/delaymax_floptoflop/delaymax_inputtooutput/delaymax_floptooutput) -//-delaymax=500 - --rules BufClock // Clock buffer detected --overloadrules BufClock+severity=Warning - --rules checkPinConnectedToSupply // IO-ports or Output ports of cells/modules may not be connected to supply signals. --overloadrules checkPinConnectedToSupply+severity=Error - -//-rules ClockEdges // Do not use both levels of the clock to drive latches - --rules CombLoop // Combinational loop exists --overloadrules CombLoop+msgLabel=CombLoop+severity=Error --enableE2Q="yes" // Report comb loop from Enable to Q pin of flop. - -//-rules DisabledAnd // And/Nand gate is disabled - -//-rules DisabledOr // Or/Nor gate is disabled - --rules FlopClockConstant // Flip-flop clock pin driven by a constant value --overloadrules FlopClockConstant+msgLabel=FlopClockConstant+severity=Error - -//-rules FlopDataConstant // Flip-flop data pin driven by a constant value - --rules FlopEConst // Flip-flop enable pin is permanently disabled or enabled - --rules FlopSRConst // Flip-flop set or reset pin is permanently enabled - -//-rules IntReset // Internally generated reset detected -//-overloadrules IntReset+msgLabel=IntReset+severity=Warning - -//-rules LatchDataConstant // Latch data pin driven by a constant value - -//-rules LatchEnableConstant // Latch enable pin driven by a constant value - --rules LatchFeedback // There should not be a combinational feedback path from a latch output to data or enable of the same latch. --overloadrules LatchFeedback+severity=Error - -//-rules LatchGatedClock // Do not use gated/internally generated clock to drive latches -//-overloadrules LatchGatedClock+msgLabel=LatchGatedClock+severity=Warning - -//-rules LatchReset // Reset pin should not be used both synchronously and asynchronously - -//-rules LogNMux // LogN mux with large number of inputs detected - potential performance problem -//-logmux_max=5 - -//-rules MuxSelConst // Mux select is constant. - -//-rules RegOutputs // Some outputs from a top module are not registered -//-overloadrules RegOutputs+severity=Warning --reportundrivenout='no' // Rule will not report violation for undriven outputs. - -//-rules SetResetConverge-ML // Fanin cone of Set and Reset pin of a flop/latch converge - --rules STARC05-1.2.1.2 // Do not create a RS latch using primitive cells such as AND, OR --overloadrules STARC05-1.2.1.2+severity=Error - --rules STARC05-1.3.1.3 // Asynchronous reset/preset signals must not be used as non-reset/preset orsynchronous reset/preset signals --overloadrules STARC05-1.3.1.3+severity=Warning - -//-rules STARC05-1.3.1.7 // A flip-flop must not have both asynchronous set and asynchronous reset - --rules STARC05-1.4.3.4 // Flip-flop clock signals must not be used as non-clock signals --overloadrules STARC05-1.4.3.4+severity=Warning - --rules STARC05-2.1.4.5 // Flip-flop clock signals must not be used as non-clock signals --overloadrules STARC05-2.1.4.5+severity=Warning - --rules STARC05-2.4.1.5 // Do not use two level latches in the same phase clock --overloadrules STARC05-2.4.1.5+severity=Error - --rules STARC05-2.5.1.2 // Logic must not exist in tristate enable conditions - -//-rules STARC05-2.5.1.4 // A tristate bus should not be driven by more than the specified number of drivers -//-overloadrules STARC05-2.5.1.4+severity=Warning - -//-rules TristateConst // Tristate gate enable is constant - -//-rules W391 // Design has a clock driving it on both edges - --rules W392 // Do not use a reset or set with both positive and negative polarity within the samedesign unit - --rules W415 // Variable/signal that does not infer a tristate and has multiple simultaneous drivers --overloadrules W415+msgLabel=W415+severity=Error --assume_driver_load="yes" // Rule will report violation for unloaded signals/variables. --checkconstassign="yes" // Rule will report violation for constant assignments - -//-rules W422L // Multiple clocks in the event control list of latch is not allowed -//-overloadrules W422L+msgLabel=W422L+severity=Warning - --rules STARC05-2.10.1.4a // Signals must not be compared with X or Z. - --rules STARC05-2.10.1.4b // Signals must not be compared with values containing X or Z. - --rules W156 // Do not connect buses in reverse order - --rules STARC05-2.3.3.1 // Do not use multiple clock signals in a single process block - --rules W415a // Signal may be multiply assigned (beside initialization) in the same scope. - --rules W287b // Output port of an instance is not connected - --rules W224 // Multi-bit expression found when one-bit expression expected - --rules W287a // Some inputs to instance are not driven or unconnected - --rules W528 // A signal or variable is set but never read - --rules mixedsenselist // Mixed conditions in sensitivity list may not be synthesizable - --rules W339a // Case equal operator (===) and case not equal (!==) operators may not be synthesizable - --rules STARC05-2.10.3.2a // Bit-width of operands of a logical operator must match. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl_custom.tcl b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl_custom.tcl deleted file mode 100644 index c27750b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/lint/lint_turbo_rtl_custom.tcl +++ /dev/null @@ -1,114 +0,0 @@ -current_goal lint/lint_turbo_rtl -scenario optional -set_goal_option addrules AllocExpr -set_goal_option addrules DisconnSpec -set_goal_option addrules ForLoopWait -set_goal_option addrules IncompleteType -set_goal_option addrules Info_Case_Analysis -set_goal_option addrules IntGeneric -set_goal_option addrules LinkagePort -set_goal_option addrules LoopBound -set_goal_option addrules NoTimeOut -set_goal_option addrules PortType -set_goal_option addrules PreDefAttr -set_goal_option addrules ResFunction -set_goal_option addrules UserDefAttr -set_goal_option addrules W182g -set_goal_option addrules W182h -set_goal_option addrules W182k -set_goal_option addrules W182n -set_goal_option addrules SignedUnsignedExpr-ML -set_goal_option addrules sim_race01 -set_goal_option overloadrules sim_race01+severity=Warning -set_goal_option addrules W239 -set_goal_option addrules BothPhase -set_goal_option addrules ClockStyle -set_goal_option addrules DiffTimescaleUsed-ML -set_goal_option addrules MultipleWait -set_goal_option addrules NoSigCaseX-ML -set_goal_option addrules SetBeforeRead-ML -set_goal_option addrules SigVarInit -set_goal_option addrules STARC05-2.1.2.5v -set_goal_option addrules STARC05-2.1.8.6 -set_goal_option addrules STARC05-2.10.3.7 -set_goal_option addrules STARC05-2.3.1.4 -set_goal_option addrules STARC05-2.3.2.4 -set_goal_option addrules STARC05-2.3.4.2 -set_goal_option addrules SynthIfStmt -set_goal_option addrules W127 -set_goal_option addrules W129 -set_goal_option addrules W182c -set_goal_option addrules W189 -set_goal_option addrules W190 -set_goal_option addrules W213 -set_goal_option addrules W226 -set_goal_option addrules W245 -set_goal_option addrules W250 -set_goal_option addrules W253 -set_goal_option addrules W254 -set_goal_option addrules W280 -set_goal_option addrules W294 -set_goal_option addrules W425 -set_goal_option addrules W427 -set_goal_option addrules W430 -set_goal_option addrules W443 -set_goal_option overloadrules W443+severity=Warning -set_goal_option addrules W444 -set_goal_option overloadrules W444+severity=Warning -set_goal_option addrules W464 -set_goal_option addrules WhileInSubProg -set_goal_option addrules ArrayIndex -set_goal_option addrules DisallowCaseX-ML -set_goal_option addrules DisallowCaseZ-ML -set_goal_option addrules DisallowXInCaseZ-ML -set_goal_option addrules ParamOverrideMismatch-ML -set_goal_option overloadrules ParamOverrideMismatch-ML+severity=Warning -set_goal_option addrules STARC05-2.3.2.2 -set_goal_option addrules W111 -set_goal_option addrules W159 -set_goal_option addrules W164a -set_goal_option overloadrules W164a+severity=Warning -set_goal_option addrules W164b -set_goal_option addrules W210 -set_goal_option overloadrules W210+severity=Warning -set_goal_option addrules W241 -set_goal_option addrules W342 -set_goal_option addrules W343 -set_goal_option addrules W423 -set_goal_option addrules W446 -set_goal_option overloadrules W446+severity=Error -set_goal_option addrules W456a -set_goal_option addrules W491 -set_goal_option addrules W551 -set_goal_option addrules STARC05-2.3.6.1 -set_goal_option addrules UseMuxBusses -set_goal_option overloadrules UseMuxBusses+severity=Warning -set_goal_option addrules W428 -set_goal_option addrules UndrivenNUnloaded-ML -set_goal_option addrules UnloadedInPort-ML -set_goal_option addrules LogicDepth -set_parameter delaymax 500 -set_goal_option addrules ClockEdges -set_goal_option addrules DisabledAnd -set_goal_option addrules DisabledOr -set_goal_option addrules FlopDataConstant -set_goal_option addrules IntReset -set_goal_option overloadrules IntReset+msgLabel=IntReset+severity=Warning -set_goal_option addrules LatchDataConstant -set_goal_option addrules LatchEnableConstant -set_goal_option addrules LatchGatedClock -set_goal_option overloadrules LatchGatedClock+msgLabel=LatchGatedClock+severity=Warning -set_goal_option addrules LatchReset -set_goal_option addrules LogNMux -set_parameter logmux_max 5 -set_goal_option addrules MuxSelConst -set_goal_option addrules RegOutputs -set_goal_option overloadrules RegOutputs+severity=Warning -set_goal_option addrules SetResetConverge-ML -set_goal_option addrules STARC05-1.3.1.7 -set_goal_option addrules STARC05-2.5.1.4 -set_goal_option overloadrules STARC05-2.5.1.4+severity=Warning -set_goal_option addrules TristateConst -set_goal_option addrules W391 -set_goal_option addrules W422L -set_goal_option overloadrules W422L+msgLabel=W422L+severity=Warning -current_goal none diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/mbist_dft/mbist_dft.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/mbist_dft/mbist_dft.spq deleted file mode 100644 index 3cc903d..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/mbist_dft/mbist_dft.spq +++ /dev/null @@ -1,25 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal File -// -// mbist_dft -// Version: 5.6.0 -// -// Revision History: -// Ver Date Comments -// 5.6.0 26-Nov-2015 First appreance -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -mbist_dft -* -The objective of this template is to run the mbist-dft policy in tcl flow. -* -The objective of this template is to run the mbist-dft policy in tcl flow. - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --policy=mbist-dft --mbist_fast_mode=on --fullpolicy diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/order b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/order deleted file mode 100644 index fdb853c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/order +++ /dev/null @@ -1,95 +0,0 @@ -=methodology+++++++++++++++++++++++++++++++++++++++++++++++++++ -rtl_handoff -* -GuideWare Reference Methodology for rtl_handoff stage of New RTL Block development -* -The rtl_handoff goals are a super-set of the initial_rtl goals. This stage -contains the complete set of recommended RTL Handoff checks. Handoff is -assumed to be the hand-off from the RTL design team to the post-synthesis -implementation team or hand-off to System Integration (sub-system or SoC) -integration. Since the hand-off process is typically iterative, it is not -necessarily expected that all goals will be clean at the first hand-off, but -at least the issues will be known and can be communicated to the consumers -downstream. - -In addition to commonly applicable templates at above design stage, -this methodology also includes a set of Optional templates. Design -teams should inspect these templates for applicability to their design. - -GuideWare Methodology Guide provides detailed description of above -templates, as well as what factors should be reviewed when selecting -optional templates. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -lint/lint_rtl* -lint/lint_turbo_rtl* -lint/lint_functional_rtl* -!HIDE lint/design_audit* -lint/lint_abstract* -!HIDE adv_lint/adv_lint_setup* -adv_lint/adv_lint_struct* -adv_lint/adv_lint_verify* -!HIDE adv_lint/lint_functional_rtl* -!HIDE constraints/sdc_gen* -constraints/sdc_audit* -constraints/sdc_check* -constraints/sdc_exception_struct* PREREQ: constraints/sdc_check -!HIDE constraints/sdc_hier_equiv* -constraints/sdc_redundancy* -!HIDE constraints/sdc_equiv* -constraints/sdc_abstract* -txv_verification/fp_verification* -txv_verification/mcp_verification* -txv_verification/fp_mcp_verification* -txv_verification/txv_run_audit* -txv_verification/txv_glitch* -txv_verification/txv_rtl_gen* -txv_verification/txv_sdc_migration* -!HIDE cdc/cdc_setup* -cdc/cdc_setup_check* -cdc/clock_reset_integrity* -cdc/cdc_verify_struct* -cdc/cdc_verify* PREREQ: cdc/cdc_verify_struct -rdc/rdc_verify_struct* -cdc/cdc_abstract* PREREQ: cdc/cdc_verify -dft/dft_scan_ready* -dft/dft_best_practice* -dft/dft_bist_ready* -dft/dft_dsm_best_practice* -dft/dft_dsm_random_resistance* -dft/dft_abstract* -power/power_audit* -power/power_activity_check* -power/power_atd* -power/power_gen_pesd* -power/power_calibration* -power/power_est_average* -power/power_est_profiling* -power/power_reduction_adv* -power/power_cge_profiling* -power/power_mem_reduction* -power/power_guidance* -power/power_mode_detection* -power/power_wtc_model* -power/power_wtc_profiler* -power/power_wtc_virtualizer* -power/power_factor_values* -power/power_factor_conditions* -power/power_est_profiling_save* -power/power_cge_profiling_save* -power/power_cge_profiling_est* -power_verification/power_verif_audit* -power_verification/power_verif_noninstr* -power_verification/power_verif_instr_rtl* -power_verification/power_verif_abstract* -physical/lint_physical* -physical/physical_analysis_signoff* -!HIDE physical/physical_analysis_congestion* - - -physical_aware_power/physical_power_postfloorplan* -physical_aware_power/power_est_average* - -rtl2netlist/rtl2netlist_migration* DDR_GOAL - -connectivity_verify/connectivity_verification* diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/lint_physical.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/lint_physical.spq deleted file mode 100644 index a0dcda5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/lint_physical.spq +++ /dev/null @@ -1,104 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : lint_physical -// Version: 2.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 13-Oct-2014 5.3.1.2 Initial version -// 1.1.0 29-Jan-2015 5.4.1 Added option prefer_tech_lib -// 2.0.0 20-May-2015 5.5.0 Removed rule PHY_CriticalObjects and added rules PHY_FaninCone_MM and PHY_FanoutCone_MM -// Overload severity as Warning and updated parameter values for PHY_LargeMux, -// PHY_FaninCone, PHY_FanoutCone and PHY_FanoutCone2 rules. -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -lint_physical -* -Perform design read to create SpyGlass Physical DB for subsequent analysis -* -This goal runs set of rules necessary to provide physical linting solution for -early RTL. - -User inputs required for this goal are - - i) Design RTL - ii) Technology library, compiled using SpyGlass Physical - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -// ---------------------------------------------------------------------------- -// Policy Registration -// ---------------------------------------------------------------------------- - --policy=physical - -// ---------------------------------------------------------------------------- -// General Setup commands -// ---------------------------------------------------------------------------- - --physical_mode // Internal switch --enable_pgnetlist // Power ground pins are handled --prefer_tech_lib // Bind design instances to tech cell even if a module with same name as tech cell is defined in rtl - -// ---------------------------------------------------------------------------- -// Policy Specific Parameter Setting -// ---------------------------------------------------------------------------- - -//-phy_max_msg_count=10000 // Controls the number of messages of each rule to be reported --phy_tech_path=$SPYGLASS_PHYSICAL_HOME/common/genericLib/sgp_tech // Set default technology library to generic tech - -// ---------------------------------------------------------------------------- -// Rule Registration -// ---------------------------------------------------------------------------- - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Lint Rules -// ---------------------------------------------------------------------------- - --rule PHY_BlackBox // Reports black boxes in the design - --rule PHY_MemorySynthesis // Reports memory variables in the design - --rule PHY_FlopCount // Reports total number of flip-flops in the design -//-phy_enable_sequential_opt='CONSTANT_FLOP HANGING_FLOP FEEDBACK_FLOP' //Controls the sequential optimization - --rule PHY_LargeMux // Reports large mux structures in the design --overloadrules PHY_LargeMux+severity=Warning // Overload rule severity to Warning --phy_largemux_threshold="{100 75}" // Threshold value of large mux rule --phy_largemux_input_threshold=512 // Minimum input size of large mux which are considered for reporting --phy_largemux_select_threshold=16 // Minimum select size of large mux which are considered for reporting --phy_largemux_cong_threshold=0 // Congestion threshold of large mux parent module ignored for large mux scaling - --rule PHY_FaninCone // Reports nodes with high number of sequential elements and ports in their fanin cone --overloadrules PHY_FaninCone+severity=Warning // Overload rule severity to Warning --phy_fanin_threshold=10000 // Minimum threshold for PHY_FaninCone rule - --rule PHY_FaninCone_MM // Reports hardmacros and blackboxes with high number of sequential elements and ports in their fanin cone - --rule PHY_FanoutCone // Reports nodes with high number of sequential elements and ports in their fanout cone --overloadrules PHY_FanoutCone+severity=Warning // Overload rule severity to Warning --phy_fanout_threshold=10000 // Minimum threshold for PHY_FanoutCone rule - --rule PHY_FanoutCone_MM // Reports hardmacros and blackboxes with high number of sequential elements and ports in their fanout cone - --rule PHY_FanoutCone2 // Reports pairs of nodes with high number of sequential elements and ports in their fanout cone --overloadrules PHY_FanoutCone2+severity=Warning // Overload rule severity to Warning --phy_fanoutcone2_metric="{{THRESHOLD 5000 5000}}" // Minimum threshold for PHY_FanoutCone2 rule - --rule PHY_FaninFanoutCone // Reports sequential instances with high number of sequential elements and ports in their fanin and fanout cone - -// ---------------------------------------------------------------------------- -// LEGEND -// ------ -// 1. Rules that are recommended for this use model are enabled by default. -// 2. Rule that are available based on customer request, as well as rule parameter values -// that user can customize are included with comment. -// Uncomment to use these rules or parameters. -// 3. Rules that are not recommended for this use model, are not listed in this file. -// ---------------------------------------------------------------------------- - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion.spq deleted file mode 100644 index 5fb1d7c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion.spq +++ /dev/null @@ -1,170 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare3.0 Goal File -// -// Goal Name : physical_analysis_congestion -// Version: 3.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 31-May-2013 5.1 Removed parameter "phy_criticalobjects_threshold" -// Added new parameter "phy_criticalobjects_metric" -// 2.0.0 30-May-2014 5.3 Guideware 2.0 Content Consistency -// 2.1.0 29-Jan-2015 5.4.1 Added option prefer_tech_lib -// 3.0.0 20-May-2015 5.5.0 Overload severity as Warning and updated parameter values for PHY_LargeMux, -// PHY_FaninCone and PHY_FanoutCone rules. -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -physical_analysis_congestion -* -Perform physical analysis using vendor library, use for congestion analysis and debug -* -This goal runs selected SpyGlass Physical Pre-Floorplan rules together with -user-supplied vendor library. The rules are selected to analyze and debug -congestion aspects of user RTL design. - -User inputs required for this goal are - - i) Design RTL - ii) SDC constraints - iii) Technology library, compiled using SpyGlass Physical - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -// ---------------------------------------------------------------------------- -// Policy Registration -// ---------------------------------------------------------------------------- - --policy=physical - -// ---------------------------------------------------------------------------- -// General Setup commands -// ---------------------------------------------------------------------------- - --mixed // Design language --physical_mode // Internal switch --enable_pgnetlist // Power ground pins are handled --prefer_tech_lib // Bind design instances to tech cell even if a module with same name as tech cell is defined in rtl - -// ---------------------------------------------------------------------------- -// Policy Specific Parameter Setting -// ---------------------------------------------------------------------------- - -// Default tool setting is used - -// ---------------------------------------------------------------------------- -// Rule Registration -// ---------------------------------------------------------------------------- - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for area estimate -// ---------------------------------------------------------------------------- - --rule PHY_GateCount // Reports NAND2 gate-equivalent area estimate for the input design - -// -rule PHY_GateArea // Reports area estimate for the input design -// -phy_gatearea_cell_util=100 // Standard cell utilization percentage used to scale standard-cell area - --rule PHY_BlackBox // Reports black boxes in the design - -// -rule PHY_FlopCount // Reports total number of flip-flops in the design - -// -rule PHY_DesignResources // Reports design resources in the design - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for timing estimate -// ---------------------------------------------------------------------------- - --rule PHY_LogicDepth_Core_ClkDelay // Reports reg-reg timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_core_clkdelay_threshold=90 // Minimum threshold for PHY_LogicDepth_Core_ClkDelay rule - // Review with user, recommend 90 as CriticalObjects analysis - --rule PHY_LogicDepth_Peri_ClkDelay // Reports PI-PO, PI-reg and reg-PO timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_peri_clkdelay_threshold=45 // Minimum threshold for PHY_LogicDepth_Peri_ClkDelay rule - // Review with user, recommend 45 for CriticalObjects analysis - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for Congestion analysis -// ---------------------------------------------------------------------------- - --rule PHY_CongModules // Reports most congested modules in the input design -// -phy_cong_threshold=7.0 // Minimum threshold for PHY_CongModules rule - // Review with user, value of 7 is recommend for debug purposes - --rule PHY_FaninCone // Reports nodes with high number of sequential elements and ports in their fanin cone --overloadrules PHY_FaninCone+severity=Warning // Overload rule severity to Warning --phy_fanin_threshold=10000 // Minimum threshold for PHY_FaninCone rule - --rule PHY_FanoutCone // Reports nodes with high number of sequential elements and ports in their fanout cone --overloadrules PHY_FanoutCone+severity=Warning // Overload rule severity to Warning --phy_fanout_threshold=10000 // Minimum threshold for PHY_FanoutCone rule - --rule PHY_LargeMux // Reports large mux instances found in the design --overloadrules PHY_LargeMux+severity=Warning // Overload rule severity to Warning --phy_largemux_threshold="{100 75}" // Threshold value of large mux rule -//-phy_largemux_input_threshold=512 // Threshold value of the input pins of a mux instance -//-phy_largemux_select_threshold=16 // Threshold value of the select pins of a mux instance -// -phy_largemux_cong_threshold=7.0 // Threshold value of the congestion score of the parent module of a mux instance - // May use value of 0.0 to ignore congestion score for large mux scaling - --rule PHY_CriticalObjects // Reports critical objects (registers and ports) in the design --phy_criticalobjects_logicdepth_mode="ClkDelay" // Selects the logic depth rule variant used for PHY_CriticalObjects rule - // this must match LogicDepth selection -//-phy_criticalobjects_threshold=4 // Threshold value for PHY_CriticalObjects rule - // review suitable threshold with user -//-phy_criticalobjects_max_objects=10000 // Maximum critical objects to be reported --phy_criticalobjects_metric="{ {FICN {5000 1.0} {20000 2.0} {40000 4.0}} {FOCN {5000 1.0} {20000 2.0} {40000 4.0}} {FILD {90 1.0} {140 2.0} {160 4.0}} {FOLD {90 1.0} {140 2.0} {160 4.0}} {FILM {25 1.0} {100 2.0} {200 4.0}} {FOLM {25 1.0} {100 2.0} {200 4.0}} }" // Select metrics contributing to PHY_CriticalObjects rule - - --rule PHY_CellPinDensity // Reports pin density of technology library cells instantiated in each congested module of the design - --rule PHY_HighFanout // Reports high fanout nodes in the input design -// -phy_highfanout_threshold=500 // Minimum threshold for PHY_HighFanout rule - // Review threshold with users, a value of 1000 is recommend for gross violators - - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for general reports -// ---------------------------------------------------------------------------- - -// -rule PHY_PhysicalSummary // Reports the Area_Congestion_Timing profile for the design at pre-floorplanned stage - --rule PHY_Reports // View all reports generated during SpyGlass Physical flow - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for customer requests -// ---------------------------------------------------------------------------- - -// Review all custom rules with user, including the threshold values - -// -rule PHY_LogicDepth_MM_ClkDelay // Reports PI-memory or reg-memory or memory-reg or memory-PO or memory-memory timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_to_mm_clkdelay_threshold=50.0 // Minimum fanin logic depth threshold for PHY_LogicDepth_MM_ClkDelay rule -// -phy_logicdepth_from_mm_clkdelay_threshold=50.0 // Minimum fanout logic depth threshold for PHY_LogicDepth_MM_ClkDelay rule - -// -rule PHY_FaninCone_MM // Reports memory and black box objects with high number of sequential elements and ports in their fanin cone -// -phy_fanin_mm_threshold=10 // Minimum threshold for PHY_FaninCone_MM rule - -// -rule PHY_FanoutCone_MM // Reports memory and black box objects with high number of sequential elements and ports in their fanout cone -// -phy_fanout_mm_threshold=10 // Minimum threshold for PHY_FanoutCone_MM rule - -// -rule PHY_CriticalObjects_MM // Reports critical objects of memory and black box type in the design -// -phy_criticalobjects_mm_threshold=2.0 // Minimum threshold for PHY_CriticalObjects_MM rule -// -phy_fanin_mm_scale_factor=1.0 // Scaling factor used for calculating FaninCone weightage for PHY_CriticalObjects_MM rule -// -phy_fanout_mm_scale_factor=1.0 // Scaling factor used for calculating FanoutCone weightage for PHY_CriticalObjects_MM rule - // PHY_LargeMux scale factor used is same as for PHY_CriticalObjects rule - ---deprecate_template physical_analysis_congestion+spg-5.6.0+Warning -// ---------------------------------------------------------------------------- -// LEGEND -// ------ -// 1. Rules that are recommended for this use model are enabled by default. -// 2. Rule that are available based on customer request, as well as rule parameter values -// that user can customize are included with comment. -// Uncomment to use these rules or parameters. -// 3. Rules that are not recommended for this use model, are not listed in this file. -// ---------------------------------------------------------------------------- - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_debug_help.htm deleted file mode 100644 index baa8824..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_debug_help.htm +++ /dev/null @@ -1,73 +0,0 @@ - - - - - - - - - - physical_analysis_congestion - - - - - - - - - - - - - -
    - -
    -

    -physical_analysis_congestion -

    -

    -This goal runs selected SpyGlass Physical Pre-Floorplan rules together with user-supplied vendor library. The rules are selected to analyze and debug congestion aspects of user RTL design. -

    -

    -User inputs required for this goal are: -

    -
      -
    • Design RTL
      • -
    • SDC constraints
      • -
    • Technology library, compiled using SpyGlass Physical
      • -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_setup.sgs deleted file mode 100644 index 3c826bd..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_congestion_setup.sgs +++ /dev/null @@ -1,89 +0,0 @@ -########################################################################## -# SpyGlass Physical Methodology -# -# Version: 1.0 -# -# Revision History: -# Ver Date Comments -# 1.0 16-Feb-2010 Initial Draft -# 1.1 02-Sep-2010 Support for honoring preset params from prj file -# 1.2 07-Sep-2010 Updated to correctly handle VI 47531 -# -# Copyright Atrenta Inc, 2010. All rights reserved. -########################################################################## -# This is the SGS script to setup PHYSICAL ANALYSIS CONGESTION -########################################################################## - -if {[info exists env(SPYGLASS_PHYSICAL_HOME)] != 0} { - set MY_ENV_SGP_PATH $env(SPYGLASS_PHYSICAL_HOME)/common/sgphysical -} elseif {[info exists env(BP_HOME)] != 0} { - if {[file exists $env(BP_HOME)/sgphysical] != 0} { - set MY_ENV_SGP_PATH $env(BP_HOME)/sgphysical - } else { - set MY_ENV_SGP_PATH $env(BP_HOME)/../../common/sgphysical - } -} else { - return -code error "SPYGLASS_PHYSICAL_HOME/BP_HOME not set" -} - -########################################################################## -# Register Variables to be used in the script here -########################################################################## -# Variable to set path to user-specified technology library -register_variable Q_USER_TECHPATH "SGS_Unset" - -# Variable to set path to user-specified SDC file -register_variable Q_USER_SDCFILE "SGS_Unset" - -########################################################################## -# Initialize variables from value in project file (or corresponding parameter defaults) -########################################################################## -get_property console.parameterValue phy_tech_path -result_variable Q_USER_TECHPATH -get_property console.parameterValue phy_sdc -result_variable Q_USER_SDCFILE - -########################################################################## -# set_property -hide_step_numbering - -set_property -step_header "Introduction" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_property -restore_session_log -enable_next_button - -create_form -label "PAC_INTRODUCTION" { - show_html $MY_ENV_SGP_PATH/templates/html/pac_1_introduction.htm -} -set_header_state "Introduction" complete - -########################################################################## -set_property -step_header "Select Technology" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAC_SELECT_TECH" { - get_dir -text "Select Precompiled technology library directory, usually named sgp_tech" -type {"sgp_tech directory" "*"} -result_variable Q_USER_TECHPATH -geometry { -side bottom } -auto_proceed - show_html $MY_ENV_SGP_PATH/templates/html/pac_2_select_techlib.htm -geometry { -side bottom } -} -set_parameters_value {phy_tech_path get_variable $Q_USER_TECHPATH} -set_header_state "Select Technology" complete - -########################################################################## -set_property -step_header "Select SDC file" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAC_SELECT_SDC" { - get_file -text "Select SDC file" -type {"SDC File" "*.sdc"} -fileExt { "SDC File" "*.sdc" } -allow_multiple -result_variable Q_USER_SDCFILE -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/pac_3_select_sdc.htm -geometry { -side bottom } -} -set_parameters_value {phy_sdc get_variable $Q_USER_SDCFILE} -set_header_state "Select SDC file" complete - -########################################################################## - -set_property -step_header "Setup optional parameter" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAC_SETUP_RULEPARA" { - set_parameters {phy_tech_path phy_sdc phy_optimization_effort phy_enable_hbo phy_blackbox_models_tcl_file phy_dont_use_cell_list phy_gatecount_depth phy_gatecount_module_size phy_gatecount_percent_size phy_highfanout_threshold phy_logicdepth_core_clkdelay_merge_bus phy_logicdepth_core_clkdelay_threshold phy_logicdepth_peri_clkdelay_merge_bus phy_logicdepth_peri_clkdelay_threshold phy_logicdepth_scale_factor phy_calculate_fold phy_fanout_scale_factor phy_fanout_threshold phy_fanin_scale_factor phy_fanin_threshold phy_cong_module_size_low phy_cong_module_size_high phy_cong_module_count phy_cong_module_size phy_cong_threshold phy_cong_effort phy_largemux_threshold phy_largemux_input_threshold phy_largemux_select_threshold phy_largemux_merge_mode phy_largemux_cong_threshold phy_largemux_scale_factor phy_enable_sequential_opt phy_criticalobjects_threshold } -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/pac_4_rule_customize.htm -} -set_header_state "Setup optional parameter" complete - -########################################################################## - -set_property -step_header "Setup Complete" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_header_state "Setup Complete" complete -create_form -label "PAC_Completed" { - show_text "Setup is successfully completed" -} - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff.spq deleted file mode 100644 index e4efd97..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff.spq +++ /dev/null @@ -1,197 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare3.0 Goal File -// -// Goal Name : physical_analysis_signoff -// Version: 3.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 18-Feb-2013 5.0 Initial version -// 1.1.0 31-May-2013 5.1 Added new parameter "phy_criticalobjects_metric" -// 2.0.0 30-May-2014 5.3 Guideware 2.0 Content Consistency -// 2.1.0 29-Jan-2015 5.4.1 Added option prefer_tech_lib -// 3.0.0 20-May-2015 5.5.0 Overload severity as Warning and updated parameter values for PHY_LargeMux, -// PHY_FaninCone and PHY_FanoutCone rules. -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -physical_analysis_signoff -* -Perform physical analysis using vendor library, use for signoff on area, congestion and timing -* -This goal runs selected SpyGlass Physical Pre-Floorplan rules together with -user-supplied vendor library. The rules are selected to signoff for area, -timing and congestion aspects of user RTL design. - -User inputs required for this goal are - - i) Design RTL - ii) SDC constraints - iii) Technology library, compiled using SpyGlass Physical - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -// ---------------------------------------------------------------------------- -// Policy Registration -// ---------------------------------------------------------------------------- - --policy=physical - -// ---------------------------------------------------------------------------- -// General Setup commands -// ---------------------------------------------------------------------------- - --mixed // Design language --physical_mode // Internal switch --enable_pgnetlist // Power ground pins are handled --prefer_tech_lib // Bind design instances to tech cell even if a module with same name as tech cell is defined in rtl - -// ---------------------------------------------------------------------------- -// Policy Specific Parameter Setting -// ---------------------------------------------------------------------------- - --phy_optimization_effort=medium // Controls the complexity and number of transform iterations used during timing optimization - // user may increase to high in .prj file, which may modestly increase runtime - -// ---------------------------------------------------------------------------- -// Rule Registration -// ---------------------------------------------------------------------------- - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for area estimate -// ---------------------------------------------------------------------------- - --rule PHY_GateCount // Reports NAND2 gate-equivalent area estimate for the input design - --rule PHY_GateArea // Reports area estimate for the input design -// -phy_gatearea_cell_util=100 // Standard cell utilization percentage used to scale standard-cell area - --rule PHY_BlackBox // Reports black boxes in the design - -// -rule PHY_FlopCount // Reports total number of flip-flops in the design - -// -rule PHY_DesignResources // Reports design resources in the design - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for timing estimate -// ---------------------------------------------------------------------------- - -// -rule PHY_LogicDepth_Core // Reports reg-reg timing paths that exceed specified logic depth (calculated on per gate basis) -// -phy_logicdepth_core_threshold=30 // Minimum threshold for PHY_LogicDepth_Core rule - // review threshold with user - -// -rule PHY_LogicDepth_Peri // Reports PI_PO,PI-PIreg and reg-PO timing paths that exceed specified logic depth (calculated on per gate basis) -// -phy_logicdepth_peri_threshold=15 // Minimum threshold for PHY_LogicDepth_Peri rule - // review threshold with user - -// -rule PHY_LogicDepth_Core_Delay // Reports reg-reg timing paths that exceed specified logic depth (based on inverter weighted delay of each instance) -// -phy_logicdepth_core_delay_threshold=100 // Minimum threshold for PHY_LogicDepth_Core_Delay rule - // review threshold with user - -// -rule PHY_LogicDepth_Peri_Delay // Reports PI_PO,PI-reg and reg-PO timing paths that exceed specified logic depth (based on inverter weighted delay of each instance) -// -phy_logicdepth_peri_delay_threshold=50 // Minimum threshold for PHY_LogicDepth_Peri_Delay rule - // review threshold with user - --rule PHY_LogicDepth_Core_ClkDelay // Reports reg-reg timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_core_clkdelay_threshold=120 // Minimum threshold for PHY_LogicDepth_Core_ClkDelay rule - // Review with user, Recommend 120 for gross outlier - --rule PHY_LogicDepth_Peri_ClkDelay // Reports PI-PO, PI-reg and reg-PO timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_peri_clkdelay_threshold=60 // Minimum threshold for PHY_LogicDepth_Peri_ClkDelay rule - // Review with user, Recommend 60 for gross outlier - --rule PHY_Timing // Generates detailed timing report at the pre-floorplanned design database - --rule PHY_TimingModules // Reports timing distribution in the design - --rule PHY_ClockDetail // Reports worst critical paths with respect to each clock in the design - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for Congestion analysis -// ---------------------------------------------------------------------------- - --rule PHY_CongModules // Reports most congested modules in the input design --phy_cong_module_size_low=50000 // Minimum instance count threshold of modules which are gross violators of logical congestion --phy_cong_threshold=8.0 // Minimum threshold for PHY_CongModules rule - // sign-off criteria uses default threshold of 8 - --rule PHY_FaninCone // Reports nodes with high number of sequential elements and ports in their fanin cone --overloadrules PHY_FaninCone+severity=Warning // Overload rule severity to Warning --phy_fanin_threshold=10000 // Minimum threshold for PHY_FaninCone rule - --rule PHY_FanoutCone // Reports nodes with high number of sequential elements and ports in their fanout cone --overloadrules PHY_FanoutCone+severity=Warning // Overload rule severity to Warning --phy_fanout_threshold=10000 // Minimum threshold for PHY_FanoutCone rule - -//-rule PHY_LargeMux // Reports large muxes in the design -//-overloadrules PHY_LargeMux+severity=Warning // Overload rule severity to Warning -//-phy_largemux_threshold="{100 75}" // Threshold value of large mux rule -//-phy_largemux_input_threshold=512 -//-phy_largemux_select_threshold=16 -// -phy_largemux_cong_threshold=7.0 - // May use value of 0.0 to ignore congestion score for large mux scaling - -// -rule PHY_CriticalObjects // Reports critical objects (registers and ports) in the design - // Review with user, recommended as part of Congestion Debug Goal only - // in this goal, default CriticalObjects metric will be FICN, FOCN and FILD. -//-phy_criticalobjects_threshold=4 // Threshold value for PHY_CriticalObjects rule -//-phy_criticalobjects_max_objects=10000 // Maximum critical objects to be reported --phy_calculate_fold=false // Enable reporting of fanout logic depth - // change above to true, if FOLD metric is required in PHY_CriticalObjects --phy_criticalobjects_logicdepth_mode="ClkDelay" // Selects the logic depth rule variant used for PHY_CriticalObjects rule - // this must match LogicDepth selection, if PHY_CriticalObjects rule is enabled --phy_criticalobjects_metric="{ {FICN {5000 1.0} {20000 2.0} {40000 4.0}} {FOCN {5000 1.0} {20000 2.0} {40000 4.0}} {FILD {90 1.0} {140 2.0} {160 4.0}} }" // Select metrics contributing to PHY_CriticalObjects rule - - -// -rule PHY_CellPinDensity // Reports pin density of technology library cells instantiated in each congested module of the design - -// -rule PHY_HighFanout // Reports high fanout nodes in the input design -// -phy_highfanout_threshold=500 // Minimum threshold for PHY_HighFanout rule - // Review threshold with users, a value of 1000 is recommend for gross violators - - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for general reports -// ---------------------------------------------------------------------------- - --rule PHY_PhysicalSummary // Reports the Area_Congestion_Timing profile for the design at pre-floorplanned stage - --rule PHY_Dashboard // Generates datasheet and dashboard reports - --rule PHY_Reports // View all reports generated during SpyGlass Physical flow - -// ---------------------------------------------------------------------------- -// SpyGlass Physical Rules for customer requests -// ---------------------------------------------------------------------------- - -// Review all custom rules with user, including the threshold values - -// -rule PHY_LogicDepth_MM_ClkDelay // Reports PI-memory or reg-memory or memory-reg or memory-PO or memory-memory timing paths that exceed specified logic depth (based on percentage of clock period weighted delay) -// -phy_logicdepth_to_mm_clkdelay_threshold=50.0 // Minimum fanin logic depth threshold for PHY_LogicDepth_MM_ClkDelay rule -// -phy_logicdepth_from_mm_clkdelay_threshold=50.0 // Minimum fanout logic depth threshold for PHY_LogicDepth_MM_ClkDelay rule - -// -rule PHY_FaninCone_MM // Reports memory and black box objects with high number of sequential elements and ports in their fanin cone -// -phy_fanin_mm_threshold=10 // Minimum threshold for PHY_FaninCone_MM rule - -// -rule PHY_FanoutCone_MM // Reports memory and black box objects with high number of sequential elements and ports in their fanout cone -// -phy_fanout_mm_threshold=10 // Minimum threshold for PHY_FanoutCone_MM rule - -// -rule PHY_CriticalObjects_MM // Reports critical objects of memory and black box type in the design -// -phy_criticalobjects_mm_threshold=2.0 // Minimum threshold for PHY_CriticalObjects_MM rule -// -phy_fanin_mm_scale_factor=1.0 // Scaling factor used for calculating FaninCone weightage for PHY_CriticalObjects_MM rule -// -phy_fanout_mm_scale_factor=1.0 // Scaling factor used for calculating FanoutCone weightage for PHY_CriticalObjects_MM rule - // PHY_LargeMux scale factor used is same as for PHY_CriticalObjects rule - -// ---------------------------------------------------------------------------- -// LEGEND -// ------ -// 1. Rules that are recommended for this use model are enabled by default. -// 2. Rule that are available based on customer request, as well as rule parameter values -// that user can customize are included with comment. -// Uncomment to use these rules or parameters. -// 3. Rules that are not recommended for this use model, are not listed in this file. -// ---------------------------------------------------------------------------- - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_debug_help.htm deleted file mode 100644 index 0834421..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_debug_help.htm +++ /dev/null @@ -1,73 +0,0 @@ - - - - - - - - - - physical_analysis_signoff - - - - - - - - - - - - - -
    - -
    -

    -physical_analysis_signoff -

    -

    -This goal runs selected SpyGlass Physical Pre-Floorplan rules together with user-supplied vendor library. The rules are selected to signoff for area, timing and congestion aspects of user RTL design. -

    -

    -User inputs required for this goal are: -

    -
      -
    • Design RTL
      • -
    • SDC constraints
      • -
    • Technology library, compiled using SpyGlass Physical
      • -
    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_setup.sgs deleted file mode 100644 index 7ddc7ee..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical/physical_analysis_signoff_setup.sgs +++ /dev/null @@ -1,89 +0,0 @@ -########################################################################## -# SpyGlass Physical Methodology -# -# Version: 1.0 -# -# Revision History: -# Ver Date Comments -# 1.0 16-Feb-2010 Initial Draft -# 1.1 02-Sep-2010 Support for honoring preset params from prj file -# 1.2 07-Sep-2010 Updated to correctly handle VI 47531 -# -# Copyright Atrenta Inc, 2010. All rights reserved. -########################################################################## -# This is the SGS script to setup PHYSICAL ANALYSIS SIGNOFF -########################################################################## - -if {[info exists env(SPYGLASS_PHYSICAL_HOME)] != 0} { - set MY_ENV_SGP_PATH $env(SPYGLASS_PHYSICAL_HOME)/common/sgphysical -} elseif {[info exists env(BP_HOME)] != 0} { - if {[file exists $env(BP_HOME)/sgphysical] != 0} { - set MY_ENV_SGP_PATH $env(BP_HOME)/sgphysical - } else { - set MY_ENV_SGP_PATH $env(BP_HOME)/../../common/sgphysical - } -} else { - return -code error "SPYGLASS_PHYSICAL_HOME/BP_HOME not set" -} - -########################################################################## -# Register Variables to be used in the script here -########################################################################## -# Variable to set path to user-specified technology library -register_variable Q_USER_TECHPATH "SGS_Unset" - -# Variable to set path to user-specified SDC file -register_variable Q_USER_SDCFILE "SGS_Unset" - -########################################################################## -# Initialize variables from value in project file (or corresponding parameter defaults) -########################################################################## -get_property console.parameterValue phy_tech_path -result_variable Q_USER_TECHPATH -get_property console.parameterValue phy_sdc -result_variable Q_USER_SDCFILE - -########################################################################## -# set_property -hide_step_numbering - -set_property -step_header "Introduction" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_property -restore_session_log -enable_next_button - -create_form -label "PASO_INTRODUCTION" { - show_html $MY_ENV_SGP_PATH/templates/html/paso_1_introduction.htm -} -set_header_state "Introduction" complete - -########################################################################## -set_property -step_header "Select Technology" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PASO_SELECT_TECH" { - get_dir -text "Select Precompiled technology library directory, usually named sgp_tech" -type {"sgp_tech directory" "*"} -result_variable Q_USER_TECHPATH -geometry { -side bottom } -auto_proceed - show_html $MY_ENV_SGP_PATH/templates/html/paso_2_select_techlib.htm -geometry { -side bottom } -} -set_parameters_value {phy_tech_path get_variable $Q_USER_TECHPATH} -set_header_state "Select Technology" complete - -########################################################################## -set_property -step_header "Select SDC file" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PASO_SELECT_SDC" { - get_file -text "Select SDC file" -type {"SDC File" "*.sdc"} -fileExt { "SDC File" "*.sdc" } -allow_multiple -result_variable Q_USER_SDCFILE -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/paso_3_select_sdc.htm -geometry { -side bottom } -} -set_parameters_value {phy_sdc get_variable $Q_USER_SDCFILE} -set_header_state "Select SDC file" complete - -########################################################################## - -set_property -step_header "Setup optional parameter" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PASO_SETUP_RULEPARA" { - set_parameters {phy_tech_path phy_sdc phy_optimization_effort phy_enable_hbo phy_blackbox_models_tcl_file phy_dont_use_cell_list phy_gatecount_depth phy_gatecount_module_size phy_gatecount_percent_size phy_gatearea_depth phy_gatearea_module_size phy_gatearea_percent_size phy_gatearea_cell_util phy_logicdepth_core_clkdelay_merge_bus phy_logicdepth_core_clkdelay_threshold phy_logicdepth_peri_clkdelay_merge_bus phy_logicdepth_peri_clkdelay_threshold phy_fanout_threshold phy_fanin_threshold phy_cong_module_size_low phy_cong_module_size_high phy_cong_module_count phy_cong_module_size phy_cong_threshold phy_cong_effort phy_enable_sequential_opt } -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/paso_4_rule_customize.htm -} -set_header_state "Setup optional parameter" complete - -########################################################################## - -set_property -step_header "Setup Complete" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_header_state "Setup Complete" complete -create_form -label "PASO_Completed" { - show_text "Setup is successfully completed" -} - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/.submethodology_help deleted file mode 100644 index 4791a85..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/.submethodology_help +++ /dev/null @@ -1,9 +0,0 @@ -The Physical_aware_power methodology enables to run physical aware power estimation flow. This flow is the integration of SpyGlass Physical and SpyGlass Power products. The RTL design is synthesized using SpyGlass Physical timing optimization engine and power estimated using SpyGlass Power. The power estimation is accurate and close to silicon numbers. - -The following goals are part of this methodology. All the options relevant to this flow are enabled in the goals. - -1. physical_power_postfloorplan: The goal runs SpyGlass Physical and generates timing optimized netlist, capacitance and slew on input RTL design. - -2. power_est_average: The goal runs SpyGlass Power and estimates accurate power using above netlist, capacitance and slew values. - -Access to the licenses are required to run this flow. For a list of licenses, contact Synopsys Support. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/doc/power_est_average.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/doc/power_est_average.htm deleted file mode 100644 index 4e17132..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/doc/power_est_average.htm +++ /dev/null @@ -1,5 +0,0 @@ - -

    -Introduction -

    -

    This goal estimates the average power of the design. You can supply the power data for standard cells in a sglib file. You can supply the activity data with a file such as VCD, FSDB or SAIF, or for an early estimate, by giving activity values for clocks and other key nets. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan.spq deleted file mode 100644 index 2c8f142..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan.spq +++ /dev/null @@ -1,62 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Template -// To be used with products released by Synopsys only -// -// physical_power_postfloorplan-mixed -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 31-May-2013 5.1 Initial version -// 1.1.0 23-Jan-2014 5.2.1 Removed all rules -// -// Copyright Synopsys Inc, 2013. All rights reserved. -// -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -physical_power_postfloorplan -* -Perform physical analysis of the design block and generate the timing optimized design DB. -* -This goal performs Early Physical Analysis of the design and generates the timing-optimized design DB. This DB can be used to correctly estimate design power. -Design inputs required for physical analysis are - - i) Design RTL - ii) Library .lib & .lef - iii) SDC constraints - -The physical constraints for SpyGlass Physical Analysis can be specified in either of the following two formats: - - i) User-specified DEF file: - - - Block size & aspect ratio - - Pin placement (optional) - - Hard-macro pre-placements (optional) - - Placement or Routing Blockages (optional) - - ii) User-specified parameters - - - Block height & width - - Block utilization and aspect ratio - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --mixed --policy=physical --physical_mode --enable_pgnetlist --policy=power_est -//-rule PHY_PhysicalSummary_FP -//-rule PHY_Timing_FP -//-rule PHY_CongestionMap_FP -//-rule PHY_Reports -//-rule PHY_Dashboard --rule sgdc2sdc --phy_vt_value=high --phy_preserve_vt=false --enable_physical_aware_pe --phy_enable_macro_flattening=true -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan_setup.sgs deleted file mode 100644 index e1ae7b3..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/physical_power_postfloorplan_setup.sgs +++ /dev/null @@ -1,204 +0,0 @@ -########################################################################## -# SpyGlass Physical Methodology -# -# Version: 0.1 -# -# Revision History: -# Ver Date Comments -# 0.1 16-Feb-2010 Initial Draft -# 1.1 02-Sep-2010 Support for honoring preset params from prj file -# 1.2 07-Sep-2010 Updated to correctly handle VI 47531 -# -# Copyright Synopsys Inc, 2010. All rights reserved. -########################################################################## -# This is the SGS script to setup PHYSICAL ANALYSIS POSTFLOORPLAN -########################################################################## - -if {[info exists env(SPYGLASS_PHYSICAL_HOME)] != 0} { - set MY_ENV_SGP_PATH $env(SPYGLASS_PHYSICAL_HOME)/common/sgphysical -} elseif {[info exists env(BP_HOME)] != 0} { - if {[file exists $env(BP_HOME)/sgphysical] != 0} { - set MY_ENV_SGP_PATH $env(BP_HOME)/sgphysical - } else { - set MY_ENV_SGP_PATH $env(BP_HOME)/../../common/sgphysical - } -} else { - return -code error "SPYGLASS_PHYSICAL_HOME/BP_HOME not set" -} - -########################################################################## -# Register Variables to be used in the script here -# All variables pick up their default value from corresponding parameter defaults (if applicable) -# The value "SGS_Unset" is just a dummy value -########################################################################## -# Variable to set path to user-specified technology library -register_variable Q_USER_TECHPATH "SGS_Unset" - -# Variable to set path to user-specified SDC file -register_variable Q_USER_SDCFILE "SGS_Unset" - -# Variable to check how user would like to specify the FP constraints -register_variable Q_USER_FP_CHOICE "None" - -register_variable Q_USER_DEFFILE "SGS_Unset" -register_variable Q_USER_BLOCKUTIL "SGS_Unset" -register_variable Q_USER_STDCELLUTIL "SGS_Unset" -register_variable Q_USER_ASPECTR "SGS_Unset" - -# Variable to check how user would like to specify the FP constraints -#register_variable Q_USER_PE_CHOICE "Do not generate power report" - -#register_variable Q_USER_PE_FLAG "SGS_Unset" -#register_variable Q_USER_PE_ACTIVITY "SGS_Unset" -#register_variable Q_USER_PE_PROB "SGS_Unset" -#register_variable Q_USER_PE_FILENAME "SGS_Unset" -#register_variable Q_USER_PE_FILETYPE "SGS_Unset" -#register_variable Q_USER_PE_TOPMODULE "SGS_Unset" -#register_variable Q_USER_PE_STARTTIME "SGS_Unset" -#register_variable Q_USER_PE_ENDTIME "SGS_Unset" - -########################################################################## -# Initialize from Project settings -########################################################################## - -get_property console.parameterValue phy_tech_path -result_variable Q_USER_TECHPATH -get_property console.parameterValue phy_sdc -result_variable Q_USER_SDCFILE - -get_property console.parameterValue phy_def_file -result_variable Q_USER_DEFFILE -get_property console.parameterValue phy_aspect_ratio -result_variable Q_USER_ASPECTR -get_property console.parameterValue phy_block_utilization -result_variable Q_USER_BLOCKUTIL -get_property console.parameterValue phy_std_cell_utilization -result_variable Q_USER_STDCELLUTIL - -#get_property console.parameterValue phy_pi_activity -result_variable Q_USER_PE_ACTIVITY -#get_property console.parameterValue phy_pi_probability -result_variable Q_USER_PE_PROB -#get_property console.parameterValue phy_sim_data_file -result_variable Q_USER_PE_FILENAME -#get_property console.parameterValue phy_sim_file_type -result_variable Q_USER_PE_FILETYPE -#get_property console.parameterValue phy_sim_top_module -result_variable Q_USER_PE_TOPMODULE -#get_property console.parameterValue phy_sim_start_time -result_variable Q_USER_PE_STARTTIME -#get_property console.parameterValue phy_sim_end_time -result_variable Q_USER_PE_ENDTIME - -########################################################################## -########################################################################## - -set_property -step_header "Introduction" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_property -hide_step_numbering - -create_form -label "PAPR_INTRODUCTION" { - show_html $MY_ENV_SGP_PATH/templates/html/pppf_1_introduction.htm -} -set_header_state "Introduction" complete - -########################################################################## -set_property -step_header "Select Technology Library" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAPR_SELECT_TECH" { - get_dir -text "Specify Technology Library" -type {"sgp_tech directory" "*"} -result_variable Q_USER_TECHPATH -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/pppf_2_select_techlib.htm -geometry { -side bottom } -} -set_parameters_value {phy_tech_path get_variable $Q_USER_TECHPATH} -set_header_state "Select Technology Library" complete - -########################################################################## -set_property -step_header "Select SDC file" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAPR_SELECT_SDC" { - get_file -text "Select SDC file" -type {"SDC File" "*.sdc"} -fileExt { "SDC File" "*.sdc" } -allow_multiple -result_variable Q_USER_SDCFILE -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/pppf_3_select_sdc.htm -geometry { -side bottom } -} -set_parameters_value {phy_sdc get_variable $Q_USER_SDCFILE} -set_header_state "Select SDC file" complete - -########################################################################## -set_property -step_header "Specify FP constraints" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -create_form -label "PAPR_SET_FP_CONSTR" { - get_choice -text "Select how you would like to specify FP contraints" -list {"None" "DEF Input" "Block Utilization" "Std. cell Utilization"} -result_variable Q_USER_FP_CHOICE -geometry { -side bottom } - show_html $MY_ENV_SGP_PATH/templates/html/pppf_4_select_fp1.htm -geometry { -side bottom } -} -sgsIf { $Q_USER_FP_CHOICE == "None" } { - show_text "You have selected Default FP Initialization method which is 70 percent std. cell utilization. Please Click Next to proceed." - set_parameters_value {phy_std_cell_utilization "70.0"} - set_parameters_value {phy_aspect_ratio "1.0"} - set_parameters_value {phy_def_file "NULL"} - set_parameters_value {phy_block_utilization "NULL"} -} -sgsIf { $Q_USER_FP_CHOICE == "DEF Input" } { - create_form -label "FP_DEFFILE" { - get_file -text "Select DEF file: " -type {"DEF File" "*"} -result_variable Q_USER_DEFFILE -geometry { -side bottom } - show_text "You have selected FP Initialization by input DEF file. Please select DEF file:" -geometry { -side bottom } - } - set_parameters_value {phy_def_file get_variable $Q_USER_DEFFILE} - set_parameters_value {phy_std_cell_utilization "NULL"} - set_parameters_value {phy_block_utilization "NULL"} -} -sgsIf { $Q_USER_FP_CHOICE == "Block Utilization" } { - create_form -label "FP_BLOCKUTIL" { - get_string -text "Specify Block Aspect Ratio (Width/Height)" -result_variable Q_USER_ASPECTR -geometry { -side bottom } - get_string -text "Specify Block Utilization percentage (range 1-99)" -result_variable Q_USER_BLOCKUTIL -geometry { -side bottom } - show_text "You have selected FP Initialization based on user-specified Block utilization and aspect ratio" -geometry { -side bottom } - } - set_parameters_value {phy_block_utilization get_variable $Q_USER_BLOCKUTIL} - set_parameters_value {phy_aspect_ratio get_variable $Q_USER_ASPECTR} - set_parameters_value {phy_def_file "NULL"} - set_parameters_value {phy_std_cell_utilization "NULL"} -} -sgsIf { $Q_USER_FP_CHOICE == "Std. cell Utilization" } { - create_form -label "FP_STDCELLUTIL" { - get_string -text "Specify Block Aspect Ratio (Width/Height)" -result_variable Q_USER_ASPECTR -geometry { -side bottom } - get_string -text "Specify Std. Cell Utilization percentage (range 1-99)" -result_variable Q_USER_STDCELLUTIL -geometry { -side bottom } - show_text "You have selected FP Initialization based on user-specified Std. Cell utilization and aspect ratio" -geometry { -side bottom } - } - set_parameters_value {phy_std_cell_utilization get_variable $Q_USER_STDCELLUTIL} - set_parameters_value {phy_aspect_ratio get_variable $Q_USER_ASPECTR} - set_parameters_value {phy_def_file "NULL"} - set_parameters_value {phy_block_utilization "NULL"} -} -set_header_state "Specify FP constraints" complete - -########################################################################## -#set_property -step_header "Specify Power-est Setup" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -#create_form -label "PAPR_SET_PE_CONSTR" { - #get_choice -text "Select how you would like to specify Power-est setup" -list {"Default Prob. model" "FSDB/VCD input" "Do not generate power report"} -result_variable Q_USER_PE_CHOICE -geometry { -side bottom } - #show_html $MY_ENV_SGP_PATH/templates/html/pppf_5_setup_powerest.htm -geometry { -side bottom } -#} -#sgsIf { $Q_USER_PE_CHOICE == "Default Prob. model" } { - #create_form -label "PE_PROB" { - #get_string -text "Specify PROBABILITY for primary inputs (range 0.0-1.0)" -result_variable Q_USER_PE_PROB -geometry { -side bottom } - #get_string -text "Specify ACTIVITY for primary inputs (range 0.0-1.0)" -result_variable Q_USER_PE_ACTIVITY -geometry { -side bottom } - #show_text "You have selected Power-est based on default activity & probability specification on primary inputs." -geometry { -side bottom } - #} - #sgsSet Q_USER_PE_FLAG "true" - #set_parameters_value {phy_pi_activity get_variable $Q_USER_PE_ACTIVITY} - #set_parameters_value {phy_pi_probability get_variable $Q_USER_PE_PROB} - #set_parameters_value {phy_sim_data_file "NULL"} -#} -#sgsIf { $Q_USER_PE_CHOICE == "FSDB/VCD input" } { - #create_form -label "PE_FSDB" { - #get_string -text "Specify End time for activity data in FSDB/VCD" -result_variable Q_USER_PE_ENDTIME -geometry { -side bottom } - #get_string -text "Specify Start time for activity data in FSDB/VCD" -result_variable Q_USER_PE_STARTTIME -geometry { -side bottom } - #get_string -text "Specify module path name in FSDB/VCD file" -result_variable Q_USER_PE_TOPMODULE -geometry { -side bottom } - #get_choice -text "Select file type" -list {"FSDB" "VCD"} -result_variable Q_USER_PE_FILETYPE -buttons -geometry { -side bottom } - #get_file -text "Select FSDB/VCD file" -type {"FSDB/VCD File" "*"} -result_variable Q_USER_PE_FILENAME -geometry { -side bottom } - #show_text "You have selected Power-est based on activity data from user-input FSDB/VCD file" -geometry { -side bottom } - #} - #sgsSet Q_USER_PE_FLAG "true" - #set_parameters_value {phy_sim_data_file get_variable $Q_USER_PE_FILENAME} - #set_parameters_value {phy_sim_file_type get_variable $Q_USER_PE_FILETYPE} - #set_parameters_value {phy_sim_top_module get_variable $Q_USER_PE_TOPMODULE} - #set_parameters_value {phy_sim_start_time get_variable $Q_USER_PE_STARTTIME} - #set_parameters_value {phy_sim_end_time get_variable $Q_USER_PE_ENDTIME} -#} -#sgsIf { $Q_USER_PE_CHOICE == "Do not generate power report" } { - #show_text "You have selected NOT to report power-est sections in the physical summary report." - #sgsSet Q_USER_PE_FLAG "false" -#} -#set_parameters_value {phy_power_metric_report get_variable $Q_USER_PE_FLAG} -#set_header_state "Specify Power-est Setup" complete -# -########################################################################## -########################################################################## - -set_property -step_header "Setup Complete" -hide_label -show_index -enable_next_button -hide_quality_bar -show_progress_bar -set_header_state "Setup Complete" complete -create_form -label "PAPR_Completed" { - set_parameters {phy_tech_path phy_sdc phy_def_file phy_optimization_effort phy_enable_hbo phy_blackbox_models_tcl_file phy_dont_use_cell_list phy_def_file phy_def_out_file phy_block_utilization phy_std_cell_utilization phy_aspect_ratio } -geometry { -side bottom } - show_text "Setup is successfully completed. You may review final parameter values as below." -} - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average.spq deleted file mode 100644 index 6c53cc2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average.spq +++ /dev/null @@ -1,34 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_est_average -// Version: 1.1 -// -// Revision History: -// Ver Date Comments -// 1.0 01-jul-2008 For Spyglass 4.1 release -// 1.1 15-may-2009 For Spyglass 4.3 release -// -// Copyright Synopsys Inc, 2008. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_est_average mixed -* -Estimates the average power of the design -* -This goal estimates the average power of the design. You can -supply the power data for standard cells in a sglib file. You -can supply the activity data with a file such as VCD, FSDB or -SAIF, or for an early estimate, by giving activity values for -clocks and other key nets. -=cut+++++++++++ - --mixed --policy=power_est --rules PEPWR02 --rules poweraudit --enable_physical_aware_pe ---flat_disable_remove_rtlc_buffer -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average_debug_help.htm deleted file mode 100644 index 79e7d98..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/power_est_average_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - power_est_average - - - - - - - - - - - - - -

    - -
    -

    -power_est_average -

    -

    -This goal produces a report of the average power estimation. The power browser displays the power in a graphical form. To see this, select the PEPWR02 rule in the message tree and double click on it. The pe_summary.rpt report file contains the same overall power information as the graphical browser. It has several sections, including a summary, hierarchical power, clock power, and memory power. -

    -

    -The pe_design_stats.rpt report file contains information about the number of registers and combnational gates in the design; it also contains information about cells without power models. Several other reports are generated. For details, please see the Power Estimation Reports section of the Power Estimation Rule Reference Guide. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_1_introduction.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_1_introduction.htm deleted file mode 100644 index 9bd14e9..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_1_introduction.htm +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - - - - - -
    - -

    Introduction

    - -

    - This template performs Early Physical Analysis of the design and generates the timing-optimized design DB. This DB can be used to correctly estimate design power. - The following input is required from user: -

    - -

    1.    -Select Technology Library

    - -

    2.    -Select SDC file

    - -

    3.    -Specify Floorplanning Constraints (Optional)

    - - -

    Please Click Next to proceed.

    - -

     

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_2_select_techlib.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_2_select_techlib.htm deleted file mode 100644 index 68c47e9..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_2_select_techlib.htm +++ /dev/null @@ -1,101 +0,0 @@ - - - - - - - - - - - -
    - -

    1. Select Technology

    - -

    - This template requires a technology library to be selected for physical analysis. This template does not support a generic library. hence, user must specify a precompiled technology library in order to run this template. -

    - -

       -

    - -

    Please select technology library, then Click Next to proceed.

    - -

     

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_3_select_sdc.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_3_select_sdc.htm deleted file mode 100644 index 08577ef..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_3_select_sdc.htm +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - - - - - -
    - -

    2. Select SDC File

    - -

    - This template requires an SDC file, that defines following design information: -

    - -

    A)    -Clock definitions, defining all clocks and their frequency

    - -

    B)    -Input and Output port delays (Recommended, but not mandatory)

    - -

    C)    -Timing Exceptions (Recommended, but not mandatory)

    - -

     

    - -

    Please select SDC file using File Browser button.

    - -

     

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_4_select_fp1.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_4_select_fp1.htm deleted file mode 100644 index 72086f6..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_4_select_fp1.htm +++ /dev/null @@ -1,112 +0,0 @@ - - - - - - - - - - - -
    - -

    3. Select Floorplanning method

    - -

    - This template allows user to optionally specify FP constraints to control the floorplan method. Available choices are: -

    - -

    1)    -None - software defaults to 70 percent standard cell utilization, and square aspect ratio.

    - -

    2)    -DEF file - input by user

    - -

    3)    -Block utilization and aspect ratio - input by user

    - -

    4)    -Std. cell utilization and aspect ratio - input by user

    - -

     

    - -

    Please select the FP method you would like to use:

    - -

     

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_5_setup_powerest.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_5_setup_powerest.htm deleted file mode 100644 index d23a9c5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/pppf_5_setup_powerest.htm +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - - - - - -
    - -

    4. Select model or data for Power-Estimation report generation:

    - -

    - This template allows you to select one of the following options: -

    - -

    1)    -Generate power-estimate report based on statistical primary input activity

    - -

    2)    -Generate power-estimate report based on input VCD or FSDB file (Recommended method)

    - -

    3)    -Do not generate power-estimate report (Default method)

    - -

     

    - -

    Please select the Power-estimation method you would like to use:

    - -

     

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/regression_run.tcl b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/regression_run.tcl deleted file mode 100644 index a9d32c4..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/physical_aware_power/regression_run.tcl +++ /dev/null @@ -1 +0,0 @@ -define_regression physical_aware_power_est -goals { physical_power_postfloorplan power_est_average } diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/.submethodology_help deleted file mode 100644 index 387c47c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/.submethodology_help +++ /dev/null @@ -1 +0,0 @@ -Expand to select the recommended goals for power estimation and reduction. The goals are applicable to the RTL stage of design. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check.spq deleted file mode 100644 index 75cfd04..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check.spq +++ /dev/null @@ -1,44 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_activity_check -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.1.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_activity_check mixed -* -Performs activity analysis -* -This goal analyzes activity for a simulation testbench. For -simulation data such as VCD or FSDB, it produces a graph of -activity over time. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PESAE04 //Reports activity captured by simulation file for the design. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_debug_help.htm deleted file mode 100644 index a47307b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_activity_check - - - - - - - - - - - - - -
    - -
    -

    -power_activity_check -

    -

    -This goal displays a graph of activity over time for the selected simulation database. Select the PESAE04 rule in the message tree, open it, and double click on the message to view the graph browser. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_setup.sgs deleted file mode 100644 index 68934ac..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_activity_check_setup.sgs +++ /dev/null @@ -1,34 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2009. All rights reserved. -########################################################################## - -register_variable ACTCHECK_SGDC "$PRJFILES_DIR/actcheck.sgdc" -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -enable_next_button -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_activity_check.htm -set_header_state "Introduction" complete - -# Instance list -set_property -step_header "Specify Instances" -enable_next_button -set_constraints2 {instance_trace} -sgdcFile {get_variable $ACTCHECK_SGDC} -hidden_fields {instance_trace:-clock} -sgdcTag "ACTCHECK_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/instance_trace.htm -set_header_state "Specify Instances" complete - -# Activity file -set_property -step_header "Specify Activity File" -enable_next_button -set_constraints2 {activity_data} -sgdcFile {get_variable $ACTCHECK_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "ACTCHECK_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -# Closure -set_property -step_header "Setup Closure" -enable_next_button -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $ACTCHECK_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.htm deleted file mode 100644 index fb6f6bb..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.htm +++ /dev/null @@ -1,666 +0,0 @@ - - - - - - - - - - - - - - - - - - - -
    - -

    Introduction

    - -

    This goal performs activity trigger detection for several -instances of the design. It computes activity over time for each instance and -detects the most significant activity events. It also reports trigger signals -for those events which are found by statistical analysis of the simulation -trace.

    - -

    By default the top most instances of the design are -analyzed, and two parameters are available:

    - -

    -          -pe_atd_max_num_modules_to_report: -defines the maximum number of instances which are analyzed

    - -

    -          -pe_atd_min_module_size: -defines the minimal size of a module to be analyzed (in terms of the number of its -leaf instances)

    - -

    If you wish to manually specify the instances, use next to -create the instance_trace constraint which can be set -in this screen. The activity trigger detection is performed from activity data -in VCD or FSDB format. Use the second screen to create the activity_data -constraint to specify the filename, format, and optionally the start and end -times.

    - -
    - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.spq deleted file mode 100644 index 025e175..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd.spq +++ /dev/null @@ -1,48 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_atd -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 16-Apr-2015 5.5.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_atd mixed -* -Performs activity trigger detection -* -This goal analyzes activity for a simulation file. -It detects and reports signals which trigger significant activity change in the design -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEATD01 // activity trigger detection - --pe_atd_min_module_size=50 --pe_atd_enable_surge_detection=yes --pe_atd_enable_glitch_detection=yes --pe_atd_idle_filter_size=5 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_debug_help.htm deleted file mode 100644 index 736f572..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_debug_help.htm +++ /dev/null @@ -1,69 +0,0 @@ - - - - - - - - - - power_activity_check - - - - - - - - - - - - - -
    - -
    -

    -power_atd -

    -

    -This goal performs activity trigger detection. It analyses a simulation file and detects signals which trigger significant changes in the design. -Three types of activity events are considered: idle/non-idle changes, -activity up/down surges, and glitches (abrupt and short loss of activity). -The analysis is performed for each instance or a specific set of instances specified through the instance_trace sgdc command. -Signals which are highly correlated to the detected activity events are reported. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_setup.sgs deleted file mode 100644 index d999bf4..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_atd_setup.sgs +++ /dev/null @@ -1,34 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2009. All rights reserved. -########################################################################## - -register_variable ATDCHECK_SGDC "$PRJFILES_DIR/atdcheck.sgdc" -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -enable_next_button -show_html $SPYGLASS_HOME/GuideWare3.0-EarlyAdopter/block/rtl_handoff/power/power_atd.htm -set_header_state "Introduction" complete - -# Instance list -set_property -step_header "Specify Instances" -enable_next_button -set_constraints2 {instance_trace} -sgdcFile {get_variable $ATDCHECK_SGDC} -hidden_fields {instance_trace:-clock} -sgdcTag "ATDCHECK_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/instance_trace.htm -set_header_state "Specify Instances" complete - -# Activity file -set_property -step_header "Specify Activity File" -enable_next_button -set_constraints2 {activity_data} -sgdcFile {get_variable $ATDCHECK_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "ATDCHECK_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -# Closure -set_property -step_header "Setup Closure" -enable_next_button -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $ATDCHECK_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit.spq deleted file mode 100644 index 3824720..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit.spq +++ /dev/null @@ -1,50 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_audit -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.1.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_audit mixed -* -Performs audit check on the inputs for power estimation -* -This goal performs an audit of the design to list the key -parameters that will be used in a power estimation. While -running this goal, the input parameters, simulation -information, technology libraries etc should be the same as what -will be used for the actual power estimation run. This goal -will create a pe_audit report that will have the detailed report -of how power estimation will comprehend the various inputs. -Please review this report and make sure that it is in sync with -the expectations. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules poweraudit //Generates audit reports for Power estimation rules - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_debug_help.htm deleted file mode 100644 index 4e0dce7..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_audit - - - - - - - - - - - - - -
    - -
    -

    -power_audit -

    -

    -This goal helps to ensure that the library and design data is set up correctly before running power estimation. Select the power audit report in the report menu. Please see the Power Methodology Guide, section 5.4 for details on what to review. In particular, this report will help you to find cells with missing power models, two dimensional array nets which are not annotated in the simulation data, and other possible power estimation problems. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_setup.sgs deleted file mode 100644 index 20c9336..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_audit_setup.sgs +++ /dev/null @@ -1,50 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 18-Aug-2008 For Spyglass 4.1 release -# 1.1 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2008. All rights reserved. -########################################################################## - -register_variable POWEREST_SGDC "$PRJFILES_DIR/powerest.sgdc" -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -register_variable USE_BBOX_RESOLUTION 1 -register_variable USE_DESIGN_CLOCKS 1 -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_audit.htm -set_header_state "Introduction" complete - -# Common setup -sgsSet STATUS {get_variable_global {$BBOX_RESOLUTION}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -} -sgsSet STATUS {get_variable_global {$DESIGN_CLOCKS}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs -} -source $SPYGLASS_HOME/auxi/common_setup/power/power_bbox_setup.sgs - -# Activity file -set_property -step_header "Specify Activity File" -enable_next_button -set_constraints2 {activity_data} -sgdcFile {get_variable $POWEREST_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -# VT mix percentage -set_property -step_header "Specify VT Mix" -set_constraints2 {vt_mix_percentage} -sgdcFile {get_variable $POWEREST_SGDC} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/vt_mix_percentage.htm -set_header_state "Specify VT Mix" complete - -# Closure -set_property -step_header "Setup Closure" -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $POWEREST_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration.spq deleted file mode 100644 index b808c02..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration.spq +++ /dev/null @@ -1,63 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// power_calibration -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 13-Jun-2014 5.3.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_calibration mixed -* -Generates the calibration data -* -This goal generates calibration data. It generates the sgdc file showing the -percentage cell allocation and percentage distribution of vt_mix in current -design. It generates the clock buffer information from the netlist design and -generates a sgdc file. It also creates a wireload based on input design and -corresponding SPEF file -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_generate_calibration_data=all //configures which all calibration data is to be generated - --pe_calibration_data_dir=./sg_calibration_data //Specify the directory path where the calibration data should be generated - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - - --rules PEVTDIST //Generates the sgdc constraints showing percentage distribution of vt_mix in current design - --rules PECLKTREE //Generates the clock buffer information from the netlist design - --rules PECELLDIST //Generates the sgdc constraints showing the percentage cell allocation in current design - --rules PECWL //creates wireload based on input design and corresponding SPEF file - --rules PESLEWEXTRACT //Extracts the default slew from the design. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration_debug_help.htm deleted file mode 100644 index b93f65f..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_calibration_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_calibration - - - - - - - - - - - - - -
    - -
    -

    -power_calibration -

    -

    -This goal generates calibration data. It generates the sgdc file showing the percentage cell allocation and percentage distribution of vt_mix in current design. It generates the clock buffer information from the netlist design and generates a sgdc file. It also creates a wireload based on input design and corresponding SPEF file -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling.spq deleted file mode 100644 index 5a4cab2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling.spq +++ /dev/null @@ -1,75 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : power_cge_profiling -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Nov-2016 2017.03 Initial version -// -// Copyright Synopsys Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_cge_profiling mixed -* -Locates opportunities for power reduction using advanced techniques and reports power savings from these opportunities -This goal enables fsdb trace for PR opportunities and D^Q enable. -* -Locates opportunities for power reduction using advanced -techniques and reports power savings from these -opportunites. For registers that do not have any -enable, this goal finds new enables. For the registers -that already has an enable, this goal finds stronger enables -that will switch off the clock for a larger duration than -the original enable. Additionally this goal estimates -power savings when a memory in design is replaced with an -equivalent half size memory or an equivalent quarter size memory. -=cut++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --rme_active2 //RTL modification status - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_ignore_clock_xor=1 //This flag is used to enable/disable the handling of Xor gate in clock path while searching for ICG - --pe_enable_fsdb_trace=1 - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR18 //Estimates power savings when a memory in design is replaced with an equivalent half size memory or an equivalent quarter size memory. - --rules PEPWR13 //Generates the report for power savings of non gated flops in the design - --rules PEPWR06 //Reports module wise summary of the clock gating enables in the design and their effectiveness. - --rules poweraudit //Generates audit reports for Power estimation rules - --rules PEPWR20 //Finds new clock gating opportunities by ODC(observability don't care) technique and estimates the power savings. - --rules PEPWR21 //Finds new clock gating opportunities by STC(Stability Condition) technique and estimates the power savings. - --rules PEPWR22 //Finds better enable using ODC techniques for registers that are already gated and estimates the power savings. - --rules PEPWR23 //Finds better enable using STC techniques for registers that are already gated and estimates the power savings. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_est.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_est.spq deleted file mode 100644 index eadf6ed..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_est.spq +++ /dev/null @@ -1,61 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_cge_profiling_est -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 21-jul-2014 For Spyglass 5.3.0.2 release -// -// Copyright Synopsys Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_cge_profiling_est mixed -* -Estimates the average power of the design and reports various power components and activity profiling information -This goal also enables fsdb trace for potential clock gating opportunities -* -Estimates the average power of the design and reports various power components and activity profiling information -=cut+++++++++++ - - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --pe_run_profiling=1 //Controls the license usage for availability of profiling information during the power estimation runs - --pe_enable_fsdb_trace=1 - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR02 //Estimates the leakage, switching and internal powers dissipated during the complete period for the design using activity analysis - --rules PEPWR03 //Estimates power savings when clock gating is implemented to replace data-muxing controlled by enable signal for flip-flops - --rules PEPWR05 //Estimates power savings due to existing clock gatings. - --rules PEPWR06 //Reports module wise summary of the clock gating enables in the design and their effectiveness. - --rules PESTR26 //Reports all the registers in the design along with their frequency information - --rules PESTR27 //Generates clock domain wise activity of the design. - --rules PESTR31 //Clock domain wise clock gating report - --rules poweraudit //Generates audit reports for Power estimation rules - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_save.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_save.spq deleted file mode 100644 index 37ad4fb..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_cge_profiling_save.spq +++ /dev/null @@ -1,46 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : power_cge_profiling_save -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 19-Sep-2017 2017.03 Initial version -// -// Copyright Synopsys Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_cge_profiling_save mixed -* -Saves design database compatible with power_cge_profiling without running any flat rules -* -Saves design database compatible with power_cge_profiling without running any flat rules -=cut++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ --pe_sim_minclk=1 ---exit_on_save --pe_enable_fsdb_trace=1 -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ --rules PEPWR20 //Finds new clock gating opportunities by ODC(observability don't care) technique and estimates the power savings. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average.spq deleted file mode 100644 index 82c534e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average.spq +++ /dev/null @@ -1,48 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_est_average -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.1.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_est_average mixed -* -Estimates the average power of the design -* -This goal estimates the average power of the design. You can -supply the power data for standard cells in a sglib file. You -can supply the activity data with a file such as VCD, FSDB or -SAIF, or for an early estimate, by giving activity values for -clocks and other key nets. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules poweraudit //Generates audit reports for Power estimation rules. - --rules PEPWR02 //Estimates the leakage, switching and internal powers dissipated during the complete period for the design using activity analysis. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_debug_help.htm deleted file mode 100644 index 79e7d98..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - power_est_average - - - - - - - - - - - - - -
    - -
    -

    -power_est_average -

    -

    -This goal produces a report of the average power estimation. The power browser displays the power in a graphical form. To see this, select the PEPWR02 rule in the message tree and double click on it. The pe_summary.rpt report file contains the same overall power information as the graphical browser. It has several sections, including a summary, hierarchical power, clock power, and memory power. -

    -

    -The pe_design_stats.rpt report file contains information about the number of registers and combnational gates in the design; it also contains information about cells without power models. Several other reports are generated. For details, please see the Power Estimation Reports section of the Power Estimation Rule Reference Guide. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_setup.sgs deleted file mode 100644 index 04acf6e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_average_setup.sgs +++ /dev/null @@ -1,50 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 18-Aug-2008 For Spyglass 4.1 release -# 1.1 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2008. All rights reserved. -########################################################################## - -register_variable POWEREST_SGDC "$PRJFILES_DIR/powerest.sgdc" -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -register_variable USE_BBOX_RESOLUTION 1 -register_variable USE_DESIGN_CLOCKS 1 -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_est_average.htm -set_header_state "Introduction" complete - -# Common setup -sgsSet STATUS {get_variable_global {$BBOX_RESOLUTION}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -} -sgsSet STATUS {get_variable_global {$DESIGN_CLOCKS}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs -} -source $SPYGLASS_HOME/auxi/common_setup/power/power_bbox_setup.sgs - -# Activity file -set_property -step_header "Specify Activity File" -enable_next_button -set_constraints2 {activity_data} -sgdcFile {get_variable $POWEREST_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -# VT mix percentage -set_property -step_header "Specify VT Mix" -set_constraints2 {vt_mix_percentage} -sgdcFile {get_variable $POWEREST_SGDC} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/vt_mix_percentage.htm -set_header_state "Specify VT Mix" complete - -# Closure -set_property -step_header "Setup Closure" -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $POWEREST_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling.spq deleted file mode 100644 index 36dce8e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling.spq +++ /dev/null @@ -1,58 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_est_profiling -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 21-jul-2014 For Spyglass 5.3.0.2 release -// -// Copyright Synopsys Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_est_profiling mixed -* -Estimates the average power of the design and reports various power components and activity profiling information -* -Estimates the average power of the design and reports various power components and activity profiling information -=cut+++++++++++ - - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --pe_run_profiling=1 //Controls the license usage for availability of profiling information during the power estimation runs - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR02 //Estimates the leakage, switching and internal powers dissipated during the complete period for the design using activity analysis - --rules PEPWR03 //Estimates power savings when clock gating is implemented to replace data-muxing controlled by enable signal for flip-flops - --rules PEPWR05 //Estimates power savings due to existing clock gatings. - --rules PEPWR06 //Reports module wise summary of the clock gating enables in the design and their effectiveness. - --rules PESTR26 //Reports all the registers in the design along with their frequency information - --rules PESTR27 //Generates clock domain wise activity of the design. - --rules PESTR31 //Clock domain wise clock gating report - --rules poweraudit //Generates audit reports for Power estimation rules - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling_save.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling_save.spq deleted file mode 100644 index fdaad04..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_est_profiling_save.spq +++ /dev/null @@ -1,46 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_est_profiling_save -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 19-Sep-2017 For Spyglass 17.03-SP2-1 release -// -// Copyright Synopsys Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_est_profiling_save mixed -* -Saves design database compatible with power_est_profiling without running any flat rules -* -Saves design database compatible with power_est_profiling without running any flat rules -=cut++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ --pe_sim_minclk=1 ---exit_on_save - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ --rules PEPWR02 //Estimates the leakage, switching and internal powers dissipated during the complete period for the design using activity analysis - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_conditions.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_conditions.spq deleted file mode 100644 index fbf8837..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_conditions.spq +++ /dev/null @@ -1,49 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass EarlyAdopter Goal File -// -// Goal Name : power_factor_conditions -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 27-Oct-2017 2017.03-SP2-2 Initial version -// -// Copyright Synopsys, 2017. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_factor_conditions mixed -* -Extract cell when conditions from libs. -* -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_wtc_mem_conditions=1 - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEMEMCOND --rules PECHECK04 - - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_values.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_values.spq deleted file mode 100644 index 103b93e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_factor_values.spq +++ /dev/null @@ -1,47 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass EarlyAdopter Goal File -// -// Goal Name : power_factor_values -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 27-Oct-2017 2017.03-SP2-2 Initial version -// -// Copyright Synopsys, 2017. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_factor_values mixed -* -Generate weight model for all nets. -* -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_toggle_activity_bucket_for_swave=1 - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPTAB01 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify.spq deleted file mode 100644 index 9072036..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify.spq +++ /dev/null @@ -1,45 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_fix_verify -// Version: 1.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0 04-Apr-2015 5.5 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_fix_verify mixed -* -Runs automatic RTL modification suggested by power reduction recommendations followed by sequential equivalence checking(SEC) on designs before and after modification. -* -Runs automatic RTL modification suggested by power reduction recommendations followed by sequential equivalence checking(SEC) on designs before and after modification. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --sgsyn_opt_file $SPYGLASS_HOME/GuideWare/latest/soc/rtl_handoff/power/red_opt.tcl //Configuration file for synthesis - --disallow_view_delete //To disable view deletion, required For RTL modification engine to work - --classic_mode //To run rules in CLASSIC synthesis mode --pe_generate_equiv_sim_file --pe_disable_goal_consolidation --pe_auto_infer_rme=1 --rme_active - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_debug_help.htm deleted file mode 100644 index 080edfc..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_fix_verify - - - - - - - - - - - - - -
    - -
    -

    -power_fix_verify -

    -

    -This goal generates modified RTL after a power reduction run is completed and reports the status of each modification as reported by SEC. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_setup.sgs deleted file mode 100644 index 6c78ebf..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_fix_verify_setup.sgs +++ /dev/null @@ -1,17 +0,0 @@ -set_property -show_index -set_property -hide_step_numbering - -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_fix_verify_bys.htm -set_header_state "Before You Start" complete - - -set_property -step_header "Set Parameters" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_fix_verify_parameters.htm -set_parameters rme_selection -set_header_state "Set Parameters" complete - -set_property -step_header "Setup Closure" -show_text " Setup is complete and verified " -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_gen_pesd.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_gen_pesd.spq deleted file mode 100644 index 84c4cad..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_gen_pesd.spq +++ /dev/null @@ -1,53 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : power_gen_pesd -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 08-Jan-2015 5.4.1 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_gen_pesd mixed -* -Generates the list of Power-Essential signals for power estimation -* -By extracting the Power-Essential signals in a design, this goal generates a -list of Power-Essential signals that can by used to reduce the simulation -data, with minimum loss in power estimation accuracy. -Power-Essential signals are crucial signals that identify key nodes, which -need to be annotated in the design. Tools used for power estimation can -subsequently propagate toggle rate and probability onto other signals with -minimal loss of accuracy. -Use this goal to reduce the size of simulation data represented in FSDB -format. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commandus -//------------------------------------------------ - --mixed //Allow mixed language --classic_mode //Allow classic mode -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPESD01 -// The PEPESD01 rule generates a list of Power-Essential signals from the -//design, which must be captured during simulation to perform the power -//estimation with reasonable accuracy. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_guidance.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_guidance.spq deleted file mode 100644 index b226e74..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_guidance.spq +++ /dev/null @@ -1,58 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_guidance -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 19-may-2014 For Spyglass 5.3 release - -// -// Copyright Synopsys Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_guidance mixed -* -Performs high level micro-architectural analysis and reports on aspects of how flops are used in the design. -* -This goal creates various reports reporting information on the use of flops in the design and looking for higher level architectural power reductions. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PESTR08 //Reports gated clocks that can be shared across the module boundaries. - --rules PESTR09 //Enable signal should be a state signal and latched in the inactive half of the clock cycle. - --rules PESTR10 //Flags cascaded gated clocks in the design. - --rules PESTR11 //Reports clock gating/Memory enable signals that are held at a constant value i.e. being tied high/low - --rules PESTR12 //Flags the gated clocks that may be further gated by power synthesis tools. - --rules PESTR32 //Flag a flop that is never idle and at-least one constant is assigned to it - --rules PRARITH01 //Detection and classification of operator groups with glitchy inputs. - --rules PRCOUNT01 //Detects and report signal that can be used to gate the counter - -//-rules PRFIFOS01 //Detection and classification of FIFOs. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction.spq deleted file mode 100644 index af4f33e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction.spq +++ /dev/null @@ -1,70 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power__mem_reduction -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 25-Nov-2013 5.2.0 Initial version -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_mem_reduction mixed -* -Reports power savings using memory power reduction techniques and register power reduction techniques. -* -Reports power savings using memory power reduction techniques and register power reduction techniques. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --rme_active2 //RTL modification status - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_ignore_clock_xor=1 //This flag is used to enable/disable the handling of Xor gate in clock path while searching for ICG - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR06 //Reports module wise summary of the clock gating enables in the design and their effectiveness. - --rules PEPWR24 //Finds memory gating opportunities by STC(Stability Condition) technique and estimates the power savings. - --rules PEPWR25 //Finds memory gating opportunities by ODC(observability don't care) technique and estimates power savings. - --rules PEPWR28 //Finds memory gating opportunities by STC(Stability Condition) technique for gating write pin and estimates the power savings. - --rules PEPWR18 //Estimates power savings when a memory in design is replaced with an equivalent half size memory or an equivalent quarter size memory. - --rules PEPWR13 //Generates the report for power savings of non gated flops in the design. - --rules poweraudit //Generates audit reports for Power estimation rules - --rules PEPWR20 //Finds new clock gating opportunities by ODC(observability don't care) technique and estimates the power savings. - --rules PEPWR21 //Finds new clock gating opportunities by STC(Stability Condition) technique and estimates the power savings. - --rules PEPWR22 //Finds better enable using ODC techniques for registers that are already gated and estimates the power savings. - --rules PEPWR23 //Finds better enable using STC techniques for registers that are already gated and estimates the power savings. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_debug_help.htm deleted file mode 100644 index 75041ba..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_mem_reduction - - - - - - - - - - - - - -
    - -
    -

    -power_mem_reduction -

    -

    -This goal finds a number of potential power saving opportunities in the design. This goal assumes you are early in the design flow and you do not have simulation data or a technology library. So it does not compute the amount of power savings; to see power values, run the power_reduction_adv goal instead. The first result to review should be the PESTR06 spreadsheet. Select the PESTR06 rule in the message tree and double-click to display a spreadsheet. This shows a "scorecard" for each module in the design with statistics on the number of existing explicit, and potential new implicit enables. Next, review the register and memory power reduction opportunites by double clicking on the violation messages of PERES01 and PERES02 rules. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_setup.sgs deleted file mode 100644 index 2188dc0..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mem_reduction_setup.sgs +++ /dev/null @@ -1,47 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2009. All rights reserved. -########################################################################## - -register_variable EARLY_SGDC "$PRJFILES_DIR/early.sgdc" -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -register_variable USE_BBOX_RESOLUTION 1 -register_variable USE_DESIGN_CLOCKS 1 -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_mem_reduction.htm -set_header_state "Introduction" complete - -# Common setup -sgsSet STATUS {get_variable_global {$BBOX_RESOLUTION}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -} -sgsSet STATUS {get_variable_global {$DESIGN_CLOCKS}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs -} -# Activity file -set_property -step_header "Specify Activity File" -set_constraints2 {activity_data} -sgdcFile {get_variable $EARLY_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "EARLY_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -set_property -step_header "AutoFix Setup" -enable_next_button -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_autofix.htm -set_parameters rme_active -set_header_state "AutoFix Setup" complete - -# Closure -set_property -step_header "Setup Closure" -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $EARLY_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-mixed.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-mixed.spq deleted file mode 100644 index ec19b06..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-mixed.spq +++ /dev/null @@ -1,28 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_mode_detection -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 04-may-2011 For Spyglass 4.6 release -// -// Copyright Atrenta Inc, 2011. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_mode_detection mixed -* -For auto-detection of different design modes based on simulation information -* -This goal automatically detects modes based on logical conditions which -can be specfied using 'mode_condition' constraint. Mode condition can -be creating a logical expression of valid nets in design. Before -creating a 'mode_condition' please also define a mode set using constraint -'mode_set'. -This goal requires simulation data as VCD file(s) or FSDB file(s). -=cut+++++++++++ - --mixed --policy=power_est --rules PESAE08 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-verilog.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-verilog.spq deleted file mode 100644 index bb0dc8c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-verilog.spq +++ /dev/null @@ -1,28 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_mode_detection -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 04-may-2011 For Spyglass 4.6 release -// -// Copyright Atrenta Inc, 2011. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_mode_detection verilog -* -For auto-detection of different design modes based on simulation information -* -This goal automatically detects modes based on logical conditions which -can be specfied using 'mode_condition' constraint. Mode condition can -be creating a logical expression of valid nets in design. Before -creating a 'mode_condition' please also define a mode set using constraint -'mode_set'. -This goal requires simulation data as VCD file(s) or FSDB file(s). -=cut+++++++++++ - --verilog --policy=power_est --rules PESAE08 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-vhdl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-vhdl.spq deleted file mode 100644 index a5cf02a..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection-vhdl.spq +++ /dev/null @@ -1,28 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_mode_detection -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 04-may-2011 For Spyglass 4.6 release -// -// Copyright Atrenta Inc, 2011. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_mode_detection vhdl -* -For auto-detection of different design modes based on simulation information -* -This goal automatically detects modes based on logical conditions which -can be specfied using 'mode_condition' constraint. Mode condition can -be creating a logical expression of valid nets in design. Before -creating a 'mode_condition' please also define a mode set using constraint -'mode_set'. -This goal requires simulation data as VCD file(s) or FSDB file(s). -=cut+++++++++++ - --vhdl --policy=power_est --rules PESAE08 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection_debug_help.htm deleted file mode 100644 index 8ff6dc1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_mode_detection_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - power_mode_detection - - - - - - - - - - - - - -
    - -
    -

    -power_mode_detection -

    -

    -This goal automatically detects modes based on logical conditions which can be specified using 'mode_condition' constraint. Mode condition can be creating a logical expression of valid nets in design. Before creating a 'mode_condition' please also define a mode set using constraint 'mode_set'. This goal requires simulation data as VCD file(s) or FSDB file(s). -

    -

    -The pe_activity.rpt report file contains information about the detected modes. details, please see the Power Estimation Reports section of the Power Estimation Rule Reference Guide. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv.spq deleted file mode 100644 index 9c474e7..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv.spq +++ /dev/null @@ -1,73 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_reduction_adv -// Version: 1.1.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Feb-2013 5.1.0 Initial version -// 1.1.0 26-Nov-2013 5.2.0 Aligned Guideware to Methodology template -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_reduction_adv mixed -* -Locates opportunities for power reduction using advanced techniques and reports power savings from these opportunities -* -Locates opportunities for power reduction using advanced -techniques and reports power savings from these -opportunites. For registers that do not have any -enable, this goal finds new enables. For the registers -that already has an enable, this goal finds stronger enables -that will switch off the clock for a larger duration than -the original enable. Additionally this goal estimates -power savings when a memory in design is replaced with an -equivalent half size memory or an equivalent quarter size memory. -=cut++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --rme_active2 //RTL modification status - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_ignore_clock_xor=1 //This flag is used to enable/disable the handling of Xor gate in clock path while searching for ICG - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR18 //Estimates power savings when a memory in design is replaced with an equivalent half size memory or an equivalent quarter size memory. - --rules PEPWR13 //Generates the report for power savings of non gated flops in the design - --rules PEPWR06 //Reports module wise summary of the clock gating enables in the design and their effectiveness. - --rules poweraudit //Generates audit reports for Power estimation rules - --rules PEPWR20 //Finds new clock gating opportunities by ODC(observability don't care) technique and estimates the power savings. - --rules PEPWR21 //Finds new clock gating opportunities by STC(Stability Condition) technique and estimates the power savings. - --rules PEPWR22 //Finds better enable using ODC techniques for registers that are already gated and estimates the power savings. - --rules PEPWR23 //Finds better enable using STC techniques for registers that are already gated and estimates the power savings. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_debug_help.htm deleted file mode 100644 index 62678af..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_reduction_medium_effort - - - - - - - - - - - - - -
    - -
    -

    -power_reduction_medium_effort -

    -

    -This goal finds a number of potential power saving opportunities in the design. Review the new and stronger enables in the design by selecting the PEPWR20, PEPWR21, PEPWR22 and PEPWR23 rules and double-clicking to see the spreadsheet. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_setup.sgs deleted file mode 100644 index ac90f54..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_reduction_adv_setup.sgs +++ /dev/null @@ -1,57 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 18-Aug-2008 For Spyglass 4.1 release -# 1.1 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Synopsys Inc, 2008. All rights reserved. -########################################################################## - -register_variable POWEREST_SGDC "$PRJFILES_DIR/powerest.sgdc" -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -register_variable USE_BBOX_RESOLUTION 1 -register_variable USE_DESIGN_CLOCKS 1 -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress - -# Introduction -set_property -step_header "Introduction" -#show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_med_reduction.htm -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_reduction_adv.htm -set_header_state "Introduction" complete - -# Common setup -sgsSet STATUS {get_variable_global {$BBOX_RESOLUTION}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -} -sgsSet STATUS {get_variable_global {$DESIGN_CLOCKS}} -sgsIf { $STATUS != 1} { - source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs -} -source $SPYGLASS_HOME/auxi/common_setup/power/power_bbox_setup.sgs - - -# Activity file -set_property -step_header "Specify Activity File" -set_constraints2 {activity_data} -sgdcFile {get_variable $POWEREST_SGDC} -hidden_fields {activity_data:-weight,-sim_topname,-instname,-sim_rtl_design_nl,-mode,-use} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/activity_data.htm -set_header_state "Specify Activity File" complete - -# VT mix percentage -set_property -step_header "Specify VT Mix" -set_constraints2 {vt_mix_percentage} -sgdcFile {get_variable $POWEREST_SGDC} -sgdcTag "POWEREST_SGDC" -html $SPYGLASS_HOME/htmlhelp/power_est/vt_mix_percentage.htm -set_header_state "Specify VT Mix" complete - -set_property -step_header "AutoFix Setup" -enable_next_button -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_autofix.htm -set_parameters rme_active -set_header_state "AutoFix Setup" complete - -# Closure -set_property -step_header "Setup Closure" -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs -set_header_state "Setup Closure" complete - -set_sgdc_state -enable $POWEREST_SGDC diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec.spq deleted file mode 100644 index 01900c0..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec.spq +++ /dev/null @@ -1,55 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_sec -// Version: 1.0.1 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 26-Nov-2013 5.2.0 Initial version -// 1.0.1 13-Jun-2014 5.3.0 Change of goal name -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_sec mixed -* -Performs sequential equivalence checking on designs before and after power optimization. -* -This goal performs sequential equivalence checking on designs before and after power -optimization. The goal runs in DDR (Dual Design Read) mode and reads in 2 designs. The first -design is the modified RTL created by autofix ( or user) based on power reduction recommendations. -The second design is the original RTL. -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=sec - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --sgsyn_opt_file $SPYGLASS_HOME/GuideWare/latest/soc/rtl_handoff/power/sec_opt.tcl //Configuration file for synthesis - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --sec_abstract_clock=1 //This parameter specifies whether to perform clock abstraction in SEC. - --sec_atime=50 //Specifies the CPU time (in seconds) that the tool takes to perform the functional analysis per assertion. - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Sec_Start01 //Performs sequential equivalence checking on designs before and after power optimization - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_debug_help.htm deleted file mode 100644 index d307df8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_debug_help.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - power_sec - - - - - - - - - - - - - -
    - -
    -

    -power_sec -

    -

    -This goal performs sequential equivalance checking on designs before and after power -optimization. The goal runs in DDR (Dual Design Read) mode and reads in 2 designs. The first -design is the modified RTL created by autofix ( or user) based on power reduction recommendations. -The second design is the original RTL. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_setup.sgs deleted file mode 100644 index 6e0c198..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_sec_setup.sgs +++ /dev/null @@ -1,26 +0,0 @@ -set_property -show_index -set_property -hide_step_numbering - -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -show_html $SPYGLASS_HOME/.Methodology/SEC/doc/sec-help1.htm -set_header_state "Before You Start" complete - -set_property -step_header "Configure SpyGlass Design Constraint File" -set_constraints -constraints {clock reset} -html $SPYGLASS_HOME/.Methodology/SEC/doc/sec-help2.htm -set_header_state "Configure SpyGlass Design Constraint File" complete - - -set_property -step_header "Set Reference Design" -show_html $SPYGLASS_HOME/.Methodology/SEC/doc/sec-help3.htm -set_reference_design -set_header_state "Set Reference Design" complete - -set_property -step_header "Set Parameters" -show_html $SPYGLASS_HOME/.Methodology/SEC/doc/sec-help4.htm -set_parameters pe_wdir -set_header_state "Set Parameters" complete - -set_property -step_header "Setup Closure" -show_text " Setup is complete and verified " -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix.spq deleted file mode 100644 index 77932bf..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix.spq +++ /dev/null @@ -1,42 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_selective_autofix -// Version: 1.0.1 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 26-Nov-2013 5.2.0 Initial version -// 1.0.1 13-Jun-2014 5.3.0 Change of goal name -// -// Copyright Synopsys Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_selective_autofix mixed -* -Runs automatic RTL modification based on the power reduction recommendations selected by the user -* -Runs automatic RTL modification based on the power reduction recommendations selected by the user -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - --sgsyn_opt_file $SPYGLASS_HOME/GuideWare/latest/soc/rtl_handoff/power/red_opt.tcl //Configuration file for synthesis - --disallow_view_delete //To disable view deletion, required For RTL modification engine to work - --classic_mode //To run rules in CLASSIC synthesis mode - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_debug_help.htm deleted file mode 100644 index 6329872..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_selective_autofix - - - - - - - - - - - - - -
    - -
    -

    -power_selective_autofix -

    -

    -This goal regenerates modified RTL after a power reduction run is completed. There is only one rule and it will not generate any messages. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_setup.sgs deleted file mode 100644 index 60453b5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_selective_autofix_setup.sgs +++ /dev/null @@ -1,17 +0,0 @@ -set_property -show_index -set_property -hide_step_numbering - -set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar -show_html $SPYGLASS_HOME/.Methodology/Power/doc/selective_autofix_bys.htm -set_header_state "Before You Start" complete - - -set_property -step_header "Set Parameters" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/selective_autofix_parameters.htm -set_parameters rme_selection -set_header_state "Set Parameters" complete - -set_property -step_header "Setup Closure" -show_text " Setup is complete and verified " -set_header_state "Setup Closure" complete - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_model.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_model.spq deleted file mode 100644 index 0eeaa39..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_model.spq +++ /dev/null @@ -1,41 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass EarlyAdopter Goal File -// -// Goal Name : power_wtc_model -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Oct-2016 2016.06-SP1 Initial version -// -// Copyright Atrenta Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_wtc_model mixed -* -Generates weight toggle count model for the design -* -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPTAB01 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_profiler.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_profiler.spq deleted file mode 100644 index 80c2bf3..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_profiler.spq +++ /dev/null @@ -1,41 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass EarlyAdopter Goal File -// -// Goal Name : power_wtc_profiler -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 18-Oct-2016 2016.06-SP1 Initial version -// -// Copyright Atrenta Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_wtc_profiler mixed -* -Profiles weight toggle count waveform and identifies time windows of peak power -* -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPROFILER01 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_virtualizer.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_virtualizer.spq deleted file mode 100644 index 5724a75..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/power_wtc_virtualizer.spq +++ /dev/null @@ -1,52 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass EarlyAdopter Goal File -// -// Goal Name : power_wtc_virtualizer -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 04-Apr-2017 2016.06-SP1 Initial version -// -// Copyright Synopsys, 2017. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -power_wtc_virtualizer mixed -* -Run power wtc virtualizer. -* -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=power_est - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //Allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pe_toggle_act_profiler_debug=1 // this enables virtualizer mode within PEPWR01 --pe_toggle_act_profiler_debug_no_power=1 // do not perform power calculations --pe_toggle_act_profiler_debug_out_fsdb="pwr_act_wtc.fsdb" - -// user must specify pe_toggle_act_profiler_debug_bucket_file generated by power_wtc_model -// user must specify pe_toggle_act_profiler_debug_pwr_num_file generated by PEPWR01 - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules PEPWR01 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/red_opt.tcl b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/red_opt.tcl deleted file mode 100644 index 9949d63..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power/red_opt.tcl +++ /dev/null @@ -1,3 +0,0 @@ -syn_set_option remove_identical_seq_cells false -syn_set_option preserve_mux 2 -syn_set_option transfer_for_gen_index_value_info 1 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/.submethodology_help deleted file mode 100644 index 59420f8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/.submethodology_help +++ /dev/null @@ -1,5 +0,0 @@ -Validate voltage/power domain goal overview: - -To check your power intent for level shifters, isolation logic, retention registers and other low power cell types, enter a SpyGlass sgdc file, or a CPF file, or a UPF file. - -Power_verification_RTL checks the intent at the RTL level. Even if you have not added low power cell types to the RTL, SpyGlass will check that the intent is correct and complete. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract.spq deleted file mode 100644 index 509729b..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract.spq +++ /dev/null @@ -1,28 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Goal Template File -// -// power_verif_abstract -// Version: 1.0 -// -// Revision History: -// Ver Date Comments -// 1.0 27-Nov-2014 For Spyglass 5.4.0 release -// -// Copyright Atrenta Inc, 2014. All rights reserved. -// ---------------------------------------------------------------------------- -=template++++++ -power_verif_abstract mixed -* -Abstraction of a block for Power Verification at a higher level of hierarchy -* -This step is used to abstract a block which is to be used at higher level of -hierarchy for Power Verification. The abstracted model helps in following: - - Less run-time at top-level - - Less noise at top-level as no violations will be reported inside the blocks - - Perform this step after doing Power verification of block. -=cut+++++++++++ --policies=lowpower - --rules PV_Abstract01 //Generates relevant abstraction of the block - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract_setup.sgs deleted file mode 100644 index b096dca..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_abstract_setup.sgs +++ /dev/null @@ -1,19 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 24-Nov-2014 For Spyglass 5.4 release -# -# Copyright Atrenta Inc, 2014. All rights reserved. -########################################################################## - -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_verif_any.htm -set_header_state "Introduction" complete -source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -source $SPYGLASS_HOME/.Methodology/Power/pwrintent_step.sgs -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit.spq deleted file mode 100644 index 6034709..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit.spq +++ /dev/null @@ -1,73 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_verif_audit -// Version: 2.1.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 2.0.0 31-May-2014 Formating changes for consistent look and feel -// 2.1.0 31-May-2015 Added new rules -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -power_verif_audit -* -Audits the power intent -* -Audits the power intent and flags missing, inconsistent and duplicate commands. -This will also report unsupported commands as well as flags non-existent objects - -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ --policy=lowpower - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - - -//------------------------------------------ -// Checks related to UPF -//----------------------------------------- --rules UPFWRN_16 //Reports the usage of an unsupported command --rules UPFWRN_17 //Reports the usage of an unsupported field of a command --rules checkUPF_existence //Checks existence of design objects(instances/nets/pins) specified with UPF commands --rules UPF_lowpower02 //Checks relationship of power nets between commands 'set_domain_supply_net', 'connect_supply_net' and 'add_port_state' --rules UPF_lowpower03 //Checks missing specification of power domain for top design unit --rules UPF_lowpower04 //Checks invalid/duplicate pst state defined in 'add_pst_state' command --rules UPF_lowpower08 //Check invalid specification of pst table using 'create_pst' commands --rules UPF_lowpower09 //Checks if supply port or supply net defined in UPF file is either undriven or multiple driven --rules UPF_lowpower10 //Checks different isolation sense for same isolation signal is specified for a domain. --rules UPF_lowpower11 //Check to ensure supply net must be declared for associated domain where supply net is used --rules UPF_lowpower12 //Specify single isolation/levelshifter strategy on domain element. --rules UPF_lowpower13 //Checks the power switch output port should have same voltage values as parent supply --rules UPF_lowpower14 //Checks the information of supply nets and their states in power state tables is complete --rules UPF_lowpower15 //Reports multi supply cells with missing connect_supply_net command --rules UPF_lowpower16 //Checks the relationship between the bias net and the primary supply net. - -//------------------------------------------ -// Checks related to Reporting -//----------------------------------------- --rules LP_DECOMPILE_CONSTR //Reports user-specified LowPower constraints interpretation details. - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit_debug_help.htm deleted file mode 100644 index 33946f2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_audit_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_verif_rtl - - - - - - - - - - - - - -
    - -
    -

    -power_verif_rtl -

    -

    -This goal checks the multiple voltage domain design for correctness of the power intent files. To check that the power intent has been applied correctly, look at the LP_DECOMPILE_CONSTRAINTS report first. Then look for the error messages for the UPF_lowpower*/CPF_lowpower* rules and review messages for each rule. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl.spq deleted file mode 100644 index e114273..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl.spq +++ /dev/null @@ -1,109 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_verif_instr_rtl -// Version: 2.1.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 2.0.0 31-May-2014 Formating changes for consistent look and feel -// 2.1.0 31-May-2015 Adding new rules -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++ -power_verif_instr_rtl -* -Verifies proper usage of power management circuitry in RTL -* -This goal verifies the proper usage of power management circuitry -in the earliest possible design stage. For design teams that -insert level shifters and isolation logic into the RTL, this goal -will check the design against the power intent. It will ensure -that level shifters protect each voltage domain crossing and the -proper type of isolation logic is inserted at the output of each -power domain. -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ --policy=lowpower - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - - -//------------------------------------------ -// Checks related to UPF -//----------------------------------------- --rules UPFWRN_16 //Reports the usage of an unsupported command --rules UPFWRN_17 //Reports the usage of an unsupported field of a command --rules checkUPF_existence //Checks existence of design objects(instances/nets/pins) specified with UPF commands --rules UPF_lowpower02 //Checks relationship of power nets between commands 'set_domain_supply_net', 'connect_supply_net' and 'add_port_state' --rules UPF_lowpower03 //Checks missing specification of power domain for top design unit --rules UPF_lowpower04 //Checks invalid/duplicate pst state defined in 'add_pst_state' command --rules UPF_lowpower08 //Check invalid specification of pst table using 'create_pst' commands --rules UPF_lowpower09 //Checks if supply port or supply net defined in UPF file is either undriven or multiple driven --rules UPF_lowpower10 //Checks different isolation sense for same isolation signal is specified for a domain. --rules UPF_lowpower11 //Check to ensure supply net must be declared for associated domain where supply net is used --rules UPF_lowpower12 //Specify single isolation/levelshifter strategy on domain element. --rules UPF_lowpower13 //Checks the power switch output port should have same voltage values as parent supply --rules UPF_lowpower14 //Checks the information of supply nets and their states in power state tables is complete --rules UPF_lowpower15 //Reports multi supply cells with missing connect_supply_net command --rules UPF_lowpower16 //Checks the relationship between the bias net and the primary supply net. - - -//------------------------------------------ -// Checks related to Reporting -//----------------------------------------- --rules LP_DECOMPILE_CONSTR //Reports user-specified LowPower constraints interpretation details. - -//------------------------------------------ -// Non-instrumented checks -//------------------------------------------ --rules LPISO04A //Check for missing Isolation Strategy of Power Domain outputs --rules LPISO04B //Check for incorrect Isolation Strategy of Power Domain - //outputs, -no_isolation given --rules LPISO05 //Check for redundant Isolation Strategy of Power Domain outputs - --rules LPLSH01 //Checks that cell defined in command 'map_level_shifter' has - // attribute 'is_level_shifter' in library --rules LPLSH03 //Check for incorrect Level Shifter Strategy, -no_shift given --rules LPLSH04 //Check for redundant Level Shifter Strategy --rules LPLSH05 //Check for missing Level Shifter Strategy - -//------------------------------------------ -// Instrumented rtl checks -//------------------------------------------ --rules LPSVM12A //Isolation signal should be in always-on domain. --rules LPSVM53 //Ensure that the always-on pin of a cell should always come from an always-on domain. - --rules LPSVM04 //Find missing/incorrect level shifters --overloadrules LPSVM04A+severity=Error --overloadrules LPSVM04B+severity=Error --overloadrules LPSVM04C+severity=Error --overloadrules LPSVM04D+severity=Error --overloadrules LPSVM04E+severity=Error - --rules LPSVM08 //Find missing isolation logic --rules LPSVM09 //Find incorrect isolation logic - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_debug_help.htm deleted file mode 100644 index 44839fe..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_verif_rtl - - - - - - - - - - - - - -
    - -
    -

    -power_verif_rtl -

    -

    -This goal checks the multiple voltage domain design for electrical correctness before synthesis. To check that the power intent has been applied correctly, look at the LP_DECOMPILE_CONSTRAINTS report first. The two key rules are LPSVM04 for level shifters, and LPSVM08 for isolation logic. Review the LPSVM08 violations before reviewing LPSVM09; many errors will generate one message for each rule. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_setup.sgs deleted file mode 100644 index 439b777..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_instr_rtl_setup.sgs +++ /dev/null @@ -1,20 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 18-Aug-2008 For Spyglass 4.1 release -# 1.1 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Atrenta Inc, 2009. All rights reserved. -########################################################################## - -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_verif_any.htm -set_header_state "Introduction" complete -source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -source $SPYGLASS_HOME/.Methodology/Power/pwrintent_step.sgs -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr.spq deleted file mode 100644 index 867c7a9..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr.spq +++ /dev/null @@ -1,92 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : power_verif_noninstr -// Version: 2.1.0 -// -// Revision History: -// Ver Date Comments -// 1.0.0 18-Feb-2013 Initial version -// 2.0.0 31-May-2014 Formating changes for consistent look and feel -// 2.1.0 31-May-2015 Adding new rules -// -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -power_verif_noninstr -* -Verifies proper usage of power management circuitry in Non-Instrmented RTL -* -This goal verifies the proper usage of power management circuitry -in the earliest possible design stage. For design teams that -insert level shifters and isolation logic during Synthesis, this goal -will check the design against the power intent.It will ensure that -level shifters and isolation strategies defined in UPF files are -correct to protect each voltage domain crossing for isolation and -level shifting power domain. -=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ --policy=lowpower - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - - -//------------------------------------------ -// Checks related to UPF -//----------------------------------------- --rules UPFWRN_16 //Reports the usage of an unsupported command --rules UPFWRN_17 //Reports the usage of an unsupported field of a command --rules checkUPF_existence //Checks existence of design objects(instances/nets/pins) specified with UPF commands --rules UPF_lowpower02 //Checks relationship of power nets between commands 'set_domain_supply_net', 'connect_supply_net' and 'add_port_state' --rules UPF_lowpower03 //Checks missing specification of power domain for top design unit --rules UPF_lowpower04 //Checks invalid/duplicate pst state defined in 'add_pst_state' command --rules UPF_lowpower08 //Check invalid specification of pst table using 'create_pst' commands --rules UPF_lowpower09 //Checks if supply port or supply net defined in UPF file is either undriven or multiple driven --rules UPF_lowpower10 //Checks different isolation sense for same isolation signal is specified for a domain. --rules UPF_lowpower11 //Check to ensure supply net must be declared for associated domain where supply net is used --rules UPF_lowpower12 //Specify single isolation/levelshifter strategy on domain element. --rules UPF_lowpower13 //Checks the power switch output port should have same voltage values as parent supply --rules UPF_lowpower14 //Checks the information of supply nets and their states in power state tables is complete --rules UPF_lowpower15 //Reports multi supply cells with missing connect_supply_net command --rules UPF_lowpower16 //Checks the relationship between the bias net and the primary supply net. - - -//------------------------------------------ -// Checks related to Reporting -//----------------------------------------- --rules LP_DECOMPILE_CONSTR //Reports user-specified LowPower constraints interpretation details. - -//------------------------------------------ -// Non-instrumented checks -//------------------------------------------ --rules LPISO04A //Check for missing Isolation Strategy of Power Domain outputs --rules LPISO04B //Check for incorrect Isolation Strategy of Power Domain outputs, -no_isolation given --rules LPISO05 //Check for redundant Isolation Strategy of Power Domain outputs - --rules LPLSH01 //Checks that cell defined in command 'map_level_shifter' has attribute 'is_level_shifter' in library --rules LPLSH03 //Check for incorrect Level Shifter Strategy, -no_shift given --rules LPLSH04 //Check for redundant Level Shifter Strategy --rules LPLSH05 //Check for missing Level Shifter Strategy - - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_debug_help.htm deleted file mode 100644 index 9e6cf4f..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_debug_help.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - power_verif_noninstr - - - - - - - - - - - - - -
    - -
    -

    -power_verif_noninstr -

    -

    -This goal checks the multiple voltage domain design for correctness and completeness of the power intent files. To check that the power intent has been applied correctly, look at the LP_DECOMPILE_CONSTRAINTS report first. Then look for the error messages for the UPF_lowpower*/CPF_lowpower* rules and review messages for each rule. Then review the messages for LPLSH* and LPISO* rules for the completeness/correctness for strategy specified for level shifting and isolation respectively. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_setup.sgs deleted file mode 100644 index 439b777..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/power_verification/power_verif_noninstr_setup.sgs +++ /dev/null @@ -1,20 +0,0 @@ -########################################################################## -# SpyGlass Goal Setup File -# -# Revision History: -# Ver Date Comments -# 1.0 18-Aug-2008 For Spyglass 4.1 release -# 1.1 24-Jun-2009 For Spyglass 4.3 release -# -# Copyright Atrenta Inc, 2009. All rights reserved. -########################################################################## - -source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs -source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs -set_property -hide_quality_bar -show_index -hide_step_numbering -show_progress -set_property -step_header "Introduction" -show_html $SPYGLASS_HOME/.Methodology/Power/doc/power_verif_any.htm -set_header_state "Introduction" complete -source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs -source $SPYGLASS_HOME/.Methodology/Power/pwrintent_step.sgs -source $SPYGLASS_HOME/.Methodology/Power/closure_step.sgs diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct.spq deleted file mode 100644 index c917828..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct.spq +++ /dev/null @@ -1,110 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : rdc_verify_struct -// Version: 1.15.0 -// -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 06-July-2015 5.5 Initial version -// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed -// 1.13.0 03-Feb-2017 2017.03 Parameter validate_qual_enable added -// 1.14.0 26-Apr-2017 2017.03-SP1 Parameters check_multiclock_bbox, ignore_qualifier_mismatch_rdc, enable_diff_clkdom_rdc, enable_or_sync added -// 1.15.0 04-Jun-2017 2017.03-SP2 Value of parameter report_all_reset_cross changed from 'no' to 'yes' -// 1.16.0 18-July-2017 2017.12 Parameter report_common_reset added -// Parameter use_inferred_abstract_port added -// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added -// Copyright Atrenta Inc, 2016. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -rdc_verify_struct mixed -* -Reset Domain Crossing Verification -* -This step is used to report reset domain crossings (RDC). It also performs -synchronization analysis, dynamic clock switching checks to identify the -RDC which will not cause the design issues. - -It also provides reset matrix view that shows the RDC count between each reset pair. -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - --mixed //allow mixed language --enable_const_prop_thru_seq //allow to propagate beyond the sequential elements --use_advcdc_features //Run Advanced CDC Rules in restore mode - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --enable_mux_sync=all //MUX Synchronization schemes --enable_and_sync=yes //Enables the AND Gate Synchronization Scheme --enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic --hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution --strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops --enable_sim_check_rdc=yes //enable/disable simulation checks in Ar_resetcross01 --report_sync_rdc=all //enable/disable reporting of synchronized reset domain crossings in Ar_resetcross01. --report_for_single_busbit=no //Specifies whether single bit of a bus is to be reported by Ar_resetcross01 --report_all_reset_cross=yes //enable the reporting the Ar_resetcross01 rules on reset crossings with destination recieving no clear/set. --validate_qual_enable=rdc //Enable/disable functional analysis at each source qualifier merging gate --ignore_qualifier_mismatch_rdc=yes //to enable/disable checks to find out mismatches of qualifier's clock and reset domains with that of destination object in reset domain crossing --enable_diff_clkdom_rdc=yes //To control whether different clock domain RDC should be reported --enable_or_sync=yes //To enable the "Or Gate Synchronization" scheme --check_multiclock_bbox=yes //If a BBox has multiple clocks then do NOT ignore inputs --report_common_reset=yes //To avoid multiple Reset_info09a violations and report common reset source --use_inferred_abstract_port=yes - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Clock_info03a // Reports unconstrained clock nets --overloadrules Clock_info03a+severity=Error - --rules Clock_info05 // MUX descriptions where two or more clock signals converge --overloadrules Clock_info05+severity=Error - --rules Reset_info09a // Reports Unconstrained asynchronous reset nets --overloadrules Reset_info09a+severity=Error - --rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge --overloadrules Clock_info05b+severity=Error - --rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value - --rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant --overloadrules Clock_info03c+severity=Error - --rules Setup_port01 //Reports unconstrained ports summary for top design unit - --rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes - --rules Clock_info15 // Generates clock domain information for primary ports - --rules Info_Case_Analysis // Constant propagation in schematic display - --rules Ar_resetcross01 // Reports reset domain crossings (RDC) --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN+severity=Error --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN_SINGLE_BIT+severity=Error --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN_BUS_DECOMPRESS+severity=Error --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN_DIFF_CLK+severity=Error --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN_SINGLE_BIT_DIFF_CLK+severity=Error --overloadrules Ar_resetcross01+msgLabel=AR_RESETCROSS01_WRN_RSN_BUS_DECOMPRESS_DIFF_CLK+severity=Error - --rules Ar_resetcross_matrix01 // Generates reset crossing matrix view - - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct_setup.sgs b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct_setup.sgs deleted file mode 100644 index b6c0f5d..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rdc/rdc_verify_struct_setup.sgs +++ /dev/null @@ -1,4 +0,0 @@ -## Register all variables -####END - -source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_setup.sgs diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/regression_run.tcl b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/regression_run.tcl deleted file mode 100644 index ebec061..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/regression_run.tcl +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Regression List -# The following regression goals will be available with this methodology. -################################################################################ - -######################################## -# default list of recommend goals to run for sign-off -######################################## -set regression_mandatory_list { lint/lint_rtl - adv_lint/adv_lint_verify - constraints/sdc_audit - constraints/sdc_check - constraints/sdc_redundancy - constraints/sdc_exception_struct - cdc/clock_reset_integrity - cdc/cdc_verify - dft/dft_scan_ready - dft/dft_best_practice - dft/dft_dsm_best_practice - power/power_est_average - power_verification/power_verif_noninstr - txv_verification/fp_mcp_verification - } - -######################################## -# additional goals to run for sign-off -######################################## -set regression_optional_list { lint/lint_abstract - constraints/sdc_abstract - constraints/sdc_equiv - constraints/sdc_hier_equiv - cdc/cdc_abstract - dft/dft_abstract - power/power_audit - power_verification/power_verif_audit - } - - -######################################## -# define/register the actual regression sets -######################################## -define_regression mandatory -goals "$regression_mandatory_list" - -define_regression optional -goals "$regression_optional_list" - -# note this goal is a superset of the mandatory and optional goals -define_regression all -goals "$regression_mandatory_list $regression_optional_list" - -define_regression physical_aware_power_est -goals { physical_aware_power/physical_power_postfloorplan physical_aware_power/power_est_average } diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration.spq deleted file mode 100644 index b3898ab..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration.spq +++ /dev/null @@ -1,50 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : rtl2netlist_migration -// Version: 1.0.0 -// Note: It is a beta feature and contact Atrenta support if you are interested -// in using it. -// Revision History: -// Ver Date SG Ver Comments -// 1.0.0 15-Apr-2015 5.5 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -rtl2netlist_migration mixed -* -Migration of RTL to netlist constraints and object names referred in RTL results -* -This goal is used to migrate following from RTL to netlist: - 1- SGDC constraints - 2- Netlist name mapping of object names referred in RTL - -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policy=rtl2netlist,clock-reset - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ --mixed //allow mixed language - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Netlist_constraint_migration01 // Migrates the constraints specified at RTL to netlist --rules Gen_inference_file01 // Maps the rtl result object names to its corresponding netlist object names present in the netlist - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration_debug_help.htm deleted file mode 100644 index 8ad7f50..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/rtl2netlist/rtl2netlist_migration_debug_help.htm +++ /dev/null @@ -1,66 +0,0 @@ - - - - - - - - - - cdc_setup_check - - - - - - - - - - - - - -
    - -
    -

    -cdc_setup_check -

    -

    -This goal is used to migrate following from RTL to netlist: - 1- SGDC constraints - 2- Netlist name mapping of object names referred in RTL -

    - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/.submethodology_help b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/.submethodology_help deleted file mode 100644 index f6fe739..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/.submethodology_help +++ /dev/null @@ -1,5 +0,0 @@ -TXV verifies correctness of timing exception constraints like false path and multicycle path. This is done using formal methods. -User can use TXV to verify the following timing exception constraints (provided by the user) - -A) False path constraint combinationally and/or sequentially -B) Multicycle path constraints -This methodology helps designers prepare the design by setting up and cleaning up SDC files diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification.spq deleted file mode 100644 index 1887e1c..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification.spq +++ /dev/null @@ -1,72 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : adv_fp_mcp_verification -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 10-Mar-2015 5.4.1 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++ -fp_mcp_verification -* -False Path and Multicycle Path Verification -* -This template is used to verify false paths and multicycle paths in timing constraints. - -The only difference between this template and the one that exists in Guideware2.0 -is that this template contains two additional parameters and two additional -constraints rules. -Parameters: - 1. 'txv_enable_new_report' set to 'yes' - 2. 'txv_mcp_reactive_flow' set to 'new_flow' -Constraints rules: - 1. Show_Case_Analysis - 2. Show_Clock_Propagation - -* -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ - --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=txv --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --txv_enable_new_report=yes // This parameter provides backward compatibility for Spreadsheet reporting --txv_mcp_reactive_flow=new_flow // This parameter runs the MCP verification in reactive mode --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Txv_MCP_StartEnd01 // Reports Multi-cycle path with missing -start/-end option when the involved clocks have different periods --rules MCP_Check01 // Multi-cycle path command does not satisfy setup/hold criteria --rules Txv_FP_Warn04 // False path uses same clock in its -from and -to lists --rules Txv_FP_Warn05 // // False path does not support the options, such as setup, hold, rise or fall --rules Txv_Info05 // Multiple paths exist from the clock pin of a sequential cell to different clock sources --rules Txv_Info06 //txv_assess report --rules Txv_MCP_Warn05 // Multicycle path does not support the options, such as rise or fall --rules Txv_resetvalue01 // Reports missing '-value' field in 'reset' constraint --rules Txv_FP01 // fp verification rule --rules Txv_MCP01 // mcp verification rule --rules Txv_Info01 // this rule should be added as user can refer to vho only through this rule violation --rules Show_Case_Analysis // Constraint Rule: Highlights case-analysis settings --rules Show_Clock_Propagation // Constraint Rule: Shows clock propagation for the port/pin -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification_debug_help.htm deleted file mode 100644 index e145c7e..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_mcp_verification_debug_help.htm +++ /dev/null @@ -1,95 +0,0 @@ - - - - - - - - - - fp_mcp_verification - - - - - - - - - - - - - -
    - -
    -

    -fp_mcp_verification -

    -

    -This goal is used to verify false path timing constraints. For faster debug and violations resolution, you can first close non functional failures as follow: -

    -

    -1. Analyze and fix setup issues reported by following rules -

    -

    -Txv_clockperiod02*, Txv_Reset03*, Txv_resetvalue01*, Clk_Gen06, Txv_FP_Warn04, Txv_FP_Warn05, Txv_MCP_Warn04, Txv_MCP_Warn05, FP_Inconclusive_Verif01, FP_Inconclusive_Verif02, MCP_Inconclusive_Verif01, MCP_Inconclusive_Verif02, MCP_As_FP_Verif06i, MCP05 -

    -

    -*: these violations need to be fixed only for sequential exception verification -

    -

    -2. Analyze and fix timing exceptions failure due to non functional reasons reported by following rules -

    -

    -Txv_FP_Nontop, MCP_Nontop, FP_Skip_Verif02, MCP_Skip_Verif02, MCP_Skip_Verif03, FP_Fail_Verif01, FP_Fail_Verif05, MCP_Info02 -

    -

    -3. Analyze and fix timing exceptions failing based on functional verification. These failures are reported by following rules -

    -

    -FP_Fail_Verif03, FP_Fail_Verif04, MCP_Fail_Verif01a, MCP_Fail_Verif01b, MCP_Fail_Verif01c, MCP_Fail_Verif02a, MCP_Fail_Verif02b, MCP_Fail_Verif02c -

    -

    -4. Analyze exceptions where functional verification did not complete and proceed with more runs to conclude the verification as needed. The following rules need to be reviewed -

    -

    -Rules FP_Incomplete_Verif01, FP_Incomplete_Verif02, MCP_Incomplete_Verif01, MCP_Incomplete_Verif02, MCP_Incomplete_Verif03 -

    -

    -The goal needs to be run again whenever the setup, exceptions, or the design has been changed. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification.spq deleted file mode 100644 index 770ecba..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification.spq +++ /dev/null @@ -1,69 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass GuideWare2.0 Goal File -// -// Goal Name : fp_verification -// Version: 1.0.0 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 10-Mar-2015 5.4.1 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// --------- - -=template++++++ -fp_verification -* -False Path Verification -* -This template is used to verify false paths in timing constraints. The given -false path is correct if there exists no input vectors that can sensitize the -given path. If the given false path is incorrect, a witness or counter -example is provided. Both combinational and sequential false paths can be -verified. - -The only difference between this template and the one that exists in Guideware2.0 -is that this template contains one additional parameters and two additional -constraints rules. -Parameter: - 'txv_enable_new_report' set to 'yes' -Constraints rules: - 1. Show_Case_Analysis - 2. Show_Clock_Propagation - -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ - --mixed -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=txv --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --txv_enable_new_report=yes // This parameter provides backward compatibility for Spreadsheet reporting --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Txv_FP_Warn04 // False path uses same clock in its -from and -to lists --rules Txv_FP_Warn05 // False path does not support the options, such as setup, hold, rise or fall --rules Txv_Info05 // Multiple paths exist from the clock pin of a sequential cell to different clock sources --rules Txv_Info06 //txv_assess report --rules Txv_resetvalue01 // Reports missing '-value' field in 'reset' constraint --rules Txv_FP01 // fp verification rule --rules Txv_Info01 // this rule should be added as user can refer to vho only through this rule violation --rules Show_Case_Analysis // Constraint Rule: Highlights case-analysis settings --rules Show_Clock_Propagation // Constraint Rule: Shows clock propagation for the port/pin -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification_debug_help.htm deleted file mode 100644 index 1aa9681..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/fp_verification_debug_help.htm +++ /dev/null @@ -1,95 +0,0 @@ - - - - - - - - - - fp_verification - - - - - - - - - - - - - -
    - -
    -

    -fp_verification -

    -

    -This goal is used to verify false path and multi-cycle path timing constraints. For faster debug and resolution of the violations, you can first close non functional failures as follow: -

    -

    -1. Analyze and fix setup issues reported by the following rules: -

    -

    -Txv_clockperiod02*, Txv_resetvalue01*, Clk_Gen06, Txv_FP_Warn04, Txv_FP_Warn05, FP_Inconclusive_Verif01, FP_Inconclusive_Verif02 -

    -

    -*: these violations need to be fixed only for sequential exception verification -

    -

    -2. Analyze and fix timing exceptions failure due to non functional reasons reported by the following rules -

    -

    -Txv_FP_Nontop, FP_Skip_Verif02, FP_Fail_Verif01, FP_Fail_Verif05 -

    -

    -3. Analyze and fix timing exceptions failing based on functional verification. These failures are reported by following rules -

    -

    -FP_Fail_Verif03, FP_Fail_Verif04 -

    -

    -4. Analyze exceptions where functional verification did not complete and proceed with more runs to conclude the verification as needed. Following rules need to be reviewed -

    -

    -FP_Incomplete_Verif01, FP_Incomplete_Verif02 -

    -

    -The goal needs to be run again whenever the setup, exceptions, or the design has been changed. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification.spq deleted file mode 100644 index 32d76fa..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification.spq +++ /dev/null @@ -1,71 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : txv_debug -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 09-Mar-2015 5.4.1 Initial version -// -// Copyright Atrenta Inc, 2015. All rights reserved. -// ----------------------------------------------------------------------------- - -=template++++++ -mcp_verification -* -Multicycle Path Verification -* -This template is used to verify multicycle paths in timing constraints by -analyzing the sequential state space. The given multicycle path of N cycles -is correct if the transition that originates from the start point can arrive -at the end point in N or more clock cycles. Over-constrained multipliers can -also be verified. - -The only difference between this template and the one that exists in Guideware2.0 -is that this template contains two additional parameters and two additional -constraints rules. -Parameters: - 1. 'txv_enable_new_report' set to 'yes' - 2. 'txv_mcp_reactive_flow' set to 'new_flow' -Constraints rules: - 1. Show_Case_Analysis - 2. Show_Clock_Propagation - -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. - -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --mixed --policies=txv --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --txv_enable_new_report=yes // This parameter provides backward compatibility for Spreadsheet reporting --txv_mcp_reactive_flow=new_flow // This parameter runs the MCP verification in reactive mode --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Txv_MCP_StartEnd01 // Reports Multi-cycle path with missing -start/-end option when the involved clocks have different periods --rules MCP_Check01 // Multi-cycle path command does not satisfy setup/hold criteria --rules Txv_Info05 // Multiple paths exist from the clock pin of a sequential cell to different clock sources --rules Txv_Info06 // txv_assess report --rules Txv_MCP_Warn05 // Multicycle path does not support the options, such as rise or fall --rules Txv_resetvalue01 // Reports missing '-value' field in 'reset' constraint --rules Txv_MCP01 // mcp verification rule --rules Txv_Info01 // this rule should be added as user can refer to vho only through this rule violation --rules Show_Case_Analysis // Constraint Rule: Highlights case-analysis settings --rules Show_Clock_Propagation // Constraint Rule: Shows clock propagation for the port/pin -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification_debug_help.htm deleted file mode 100644 index 39b3c25..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/mcp_verification_debug_help.htm +++ /dev/null @@ -1,95 +0,0 @@ - - - - - - - - - - mcp_verification - - - - - - - - - - - - - -
    - -
    -

    -mcp_verification -

    -

    -This goal is used to verify multi-cycle path timing constraints. For faster debug and violations resolution, you can first close non functional failures as follow: -

    -

    -1. Analyze and fix setup issues reported by the following rules -

    -

    -Txv_clockperiod02*, Txv_Reset03*, Txv_resetvalue01*, Clk_Gen06, Txv_MCP_Warn04, Txv_MCP_Warn05, MCP_Inconclusive_Verif01, MCP_Inconclusive_Verif02, MCP_As_FP_Verif06, MCP05 -

    -

    -*: these violations need to be fixed only for sequential exception verification -

    -

    -2. Analyze and fix timing exceptions failure due to non functional reasons reported by the following rules -

    -

    -MCP_Nontop, MCP_Skip_Verif02, MCP_Skip_Verif03, MCP_Info02 -

    -

    -3. Analyze and fix timing exceptions failing based on functional verification reported by following rules -

    -

    -MCP_Fail_Verif01a, MCP_Fail_Verif01b, MCP_Fail_Verif01c, MCP_Fail_Verif02a, MCP_Fail_Verif02b, MCP_Fail_Verif02c -

    -

    -4. Analyze exceptions where functional verification did not complete and proceed with more runs to conclude the verification as needed. The following rules need to be reviewed -

    -

    -MCP_Incomplete_Verif01, MCP_Incomplete_Verif02, MCP_Incomplete_Verif03 -

    -

    -The goal needs to be run again whenever the setup, exceptions, or the design has been changed. -

    - - - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_glitch.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_glitch.spq deleted file mode 100644 index 28a0afb..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_glitch.spq +++ /dev/null @@ -1,23 +0,0 @@ -// ----------------------------------------------------------------------------- -// SpyGlass Goal Template File for Clock to clock False Path Generation from RTL -// -// Copyright Atrenta Inc, 2008. All rights reserved. -// ----------------------------------------------------------------------------- -=template++++++ -txv_glitch -* -Failed due to Glitch because of reconvergence -* -The rule flags false-path commands where there is a probablity of a glitch -because of reconvergence from 'from' point. This rule checks for reconvergence -if and only if no clock is specified in the from list of the false path. - -The failed false-path commands are also listed in the autogenerated -txv_fail_ file in the $CWD/_reports/txv directory. -=cut+++++++++++ - - --mixed --policies=txv --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior --rules Txv_FP_Glitch01 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_rtl_gen.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_rtl_gen.spq deleted file mode 100644 index 97afdd1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_rtl_gen.spq +++ /dev/null @@ -1,26 +0,0 @@ -// ----------------------------------------------------------------------------- -// SpyGlass Goal Template File for Clock to clock False Path Generation from RTL -// -// Copyright Atrenta Inc, 2008. All rights reserved. -// ----------------------------------------------------------------------------- -=template++++++ -txv_rtl_gen -* -clock to clock False Path Generation -* -This template is used to report pair of unrelated clocks. If parameter txv_verify_c2c -is set to 'yes', it reports clock to clock false paths after validation. If parameter -txv_verify_c2c is set to 'no', it reports candidate for clock to clock false paths. -This template also reports the terminals on which generated clocks should be specified -and interacting clock pairs with non integer period ratio. - -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. -=cut+++++++++++ - - --mixed --policies=txv --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior --rules Txv_Info08 --rules Txv_Info09 --rules Txv_C2C_Fp diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit.spq deleted file mode 100644 index 2707b58..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit.spq +++ /dev/null @@ -1,78 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : txv_run_audit -// Version: 1.0.1 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 30-Oct-2014 5.4.0 Initial version -// -// Copyright Atrenta Inc, 2014. All rights reserved. -// ----------------------------------------------------------------------------- - -=template++++++ -txv_run_audit -* -Run TXV in audit mode -* -This template is used to run TXV in audit mode. In audit mode, only -structural (non-functional) verification is performed. Constraints which -require functional verification are not verified. They are reported under -'Skip' category in this mode. - -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. - -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --mixed --policies=txv -#-policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --txv_run_audit=yes -#-txv_detect_te_overlap=no --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Txv_MCP_StartEnd01 // Reports Multi-cycle path with missing -start/-end option when the involved clocks have different periods --rules MCP_Check01 // Multi-cycle path command does not satisfy setup/hold criteria -#-rules Txv_clockperiod02 // This rule reports the clocks rounded with their actual period and rounded value --rules Txv_FP_Warn04 // False path uses same clock in its -from and -to lists --rules Txv_FP_Warn05 // // False path does not support the options, such as setup, hold, rise or fall --rules Txv_Info05 // Multiple paths exist from the clock pin of a sequential cell to different clock sources --rules Txv_Info06 //txv_assess report --rules Txv_MCP_Warn05 // Multicycle path does not support the options, such as rise or fall --rules Txv_resetvalue01 // Reports missing '-value' field in 'reset' constraint --rules Txv_FP01 // fp verification rule --rules Txv_MCP01 // mcp verification rule --rules Txv_Info01 // this rule should be added as user can refer to vho only through this rule violation -#-rules Show_Case_Analysis -#-rules Clk_Gen33 -#-rules Clk_Gen23 -#-rules Clk_Gen02 -#-rules Clk_Gen03 -#-rules Clk_Gen08 -#-rules Clk_Gen09 -#-rules Clk_Gen22 -#-rules Clk_Gen06 // Multiple paths exist from the clock pin of a sequential cell to different clock sources -#-rules TE_Methodology02 -#-rules SDC_Methodology66 -#-rules SDC_Methodology67 -#-rules MCP05 // Multi-cycle path command does not satisfy setup/hold criteria -#-rules Clk_Gen01a -#-rules Clk_Gen01b -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit_debug_help.htm deleted file mode 100644 index db96e76..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_run_audit_debug_help.htm +++ /dev/null @@ -1,63 +0,0 @@ - - - - - - - - - - mcp_verification - - - - - - - - - - - - - -
    - -
    -

    -mcp_verification -

    -

    -This goal is used to audit set_multicycle_path and set_false_path timing constraints. When this goal is run only structural (non-functional) verification is performed. Constraints which require functional verification are skipped. This provides a quick overview of timing exception verification. -

    - - -
    - -
    - - - -
    - - - - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_sdc_migration.spq b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_sdc_migration.spq deleted file mode 100644 index 9a9f524..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/txv_verification/txv_sdc_migration.spq +++ /dev/null @@ -1,49 +0,0 @@ -// ---------------------------------------------------------------------------- -// SpyGlass Methodology2.0 Goal File -// -// Goal Name : txv_sdc_migration -// Version: 1.0.1 -// -// Revision History: -// Ver Date SG Version Comments -// 1.0.0 27-Nov-2014 5.4.0 Initial version -// -// Copyright Atrenta Inc, 2014. All rights reserved. -// ----------------------------------------------------------------------------- - -=template++++++ -txv_sdc_migration -* -Migrate netlist constraints to RTL -* -This template is used to convert netlist design constraints to rtl level design constraints. -It is used on customer designs where we have rtl design but constraints on netlist. - -For more details about this goal, please refer to the SpyGlass-TXV-Methodology.pdf file in the doc subdirectory of your SpyGlass installation. - -=cut+++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --mixed -#-policies=txv --policies=constraints - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - --pt=no // This parameter determines that parsing, verification and generation should follow Design Compiler behavior - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules SDC_Methodology73 - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/del_tmp_files.sh b/src/UWE_projectCode/tmp/tmp/Scripts/del_tmp_files.sh deleted file mode 100644 index c623688..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/del_tmp_files.sh +++ /dev/null @@ -1,17 +0,0 @@ -find . -name "command.log" -exec rm -fr "{}" \; -find . -name "pt_shell_command.log" -exec rm -fr "{}" \; -find . -name "pt.log" -exec rm -fr "{}" \; -find . -name "default.svf" -exec rm -fr "{}" \; -find . -name "*_constr.pt" -exec rm -fr "{}" \; -find . -name "alib-52" -exec rm -fr "{}" \; -find . -name "lib2db.log" -exec rm -fr "{}" \; -find . -name "synopsysdc" -exec rm -fr "{}" \; -find . -name "analyzed" -exec rm -fr "{}" \; -find . -name "*~" -exec rm -fr "{}" \; -find . -name "filenames_*.log" -exec rm -fr "{}" \; -find . -name "*.lck" -exec rm -fr "{}" \; -find . -name "*fm_shell_command*.log" -exec rm -fr "{}" \; -find . -name "*FM_WORK*" -exec rm -fr "{}" \; -find . -name "*formality*_svf" -exec rm -fr "{}" \; -find . -name "*formality*.log" -exec rm -fr "{}" \; -find . -name "filenames.log" -exec rm -fr "{}" \; diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/error_find.perl b/src/UWE_projectCode/tmp/tmp/Scripts/error_find.perl deleted file mode 100644 index 3813ec2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/error_find.perl +++ /dev/null @@ -1,9 +0,0 @@ -#! /usr/bin/perl -open(USER,"dc.log") || die "can't open"; -open(Data,">error.txt") || die "can't open"; -while(){chomp;if($_ eq ""){next;} if($_=~/#+/){next;} -#if(/Warning\:/) {print Data "$_\n";} -if(/Error\:/) {print Data "$_\n";} -} -close(USER); -close(Data); diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/ezeco_setup.sh b/src/UWE_projectCode/tmp/tmp/Scripts/ezeco_setup.sh deleted file mode 100644 index b2d6934..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/ezeco_setup.sh +++ /dev/null @@ -1,101 +0,0 @@ -moduleName=`tclsh setModuleName.tcl` -echo $moduleName - -PP=`setPP.sh` -echo "PP = ${PP}" - -while read line -do - echo $line - R1_PATH=`echo $line` - echo $R1_PATH -done < dc.work/R1_PATH.txt - -echo $ECO_COMM - -EZ_FLOW=$1 -echo $EZ_FLOW -echo $EZECO_HOME - -if [ ${EZ_FLOW} == "dc" ]; then - POSTFIX="" -fi - -if [ ${EZ_FLOW} == "dft" ]; then - POSTFIX="_dft" -fi - -if [ ${EZ_FLOW} == "pr" ]; then - POSTFIX="_pr" -fi - -echo $POSTFIX - -cp $EZECO_HOME/scripts/easyeco_setup.template.script ./ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?easyeco.lic?$EZECO_HOME/../easyeco.lic?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?lib /lib/std2.lib?lib_file ez.work/lib.f?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i '/std1.lib/d' ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i '/std3.lib/d' ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -if [ -e $R1_PATH/result/${moduleName}${POSTFIX}.v ]; then - sed -i "s?old.v?$R1_PATH/result/${moduleName}${POSTFIX}.v?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -else - sed -i "s?old.v?$R1_PATH/result/${moduleName}${POSTFIX}.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -fi -if [ -e $R1_PATH/result/${moduleName}.v ]; then - sed -i "s?old_syn.v?$R1_PATH/result/${moduleName}.v?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -else - sed -i "s?old_syn.v?$R1_PATH/result/${moduleName}.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -fi - -if [ ${EZ_FLOW} == "dc" ] ; then - if [ -e ${PP}/result/${moduleName}.sv ]; then - sed -i "s?new.v?${PP}/result/${moduleName}.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - else - sed -i "s?new.v?${PP}/result/${moduleName}.v?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - fi -fi - -if [ ${EZ_FLOW} == "dft" ]; then - if [ -e ${R1_PATH}/result/${moduleName}_eco.v ]; then - sed -i "s?new.v?${R1_PATH}/result/${moduleName}_eco.v?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - else - sed -i "s?new.v?${R1_PATH}/result/${moduleName}_eco.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - fi -fi - -if [ ${EZ_FLOW} == "pr" ]; then - if [ -e ${R1_PATH}/result/${moduleName}_eco.v ]; then - sed -i "s?new.v?${R1_PATH}/result/${moduleName}_eco.v?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - else - sed -i "s?new.v?${R1_PATH}/result/${moduleName}_eco.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - fi -fi - -sed -i "s?old1.svf old2.svf?$R1_PATH/fm_svf.txt?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?new1.svf new2.svf?${PP}/fm_svf.txt?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - - -sed -i "s?lef lef?#lef lef?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?def old.def?#def old.def?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?ecoed.v?ez.work/$ECO_COMM/${moduleName}${POSTFIX}_eco.sv?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?ecoed.script?ez.work/$ECO_COMM/ecoed${POSTFIX}.script?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?ecoed.log?ez.work/$ECO_COMM/ecoed${POSTFIX}.log?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i '/debug/a\fast' ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?map_constant_by_tie_cell?#map_constant_by_tie_cell?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?spare_module?#spare_module?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?spare_instance?#spare_instance?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?spare_filler?#spare_filler?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?eco_gate_array_cell?#eco_gate_array_cell?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "s?# ignore_optimized_ff_in_setup?ignore_optimized_ff_in_setup?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i '/ignore_optimized_ff_in_setup/a\ignore_false_add_port' ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "/ignore_optimized_ff_in_setup/a\include ez.work/dont_use_cells.tcl" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script -sed -i "/ignore_optimized_ff_in_setup/a\ignore_false_eco_sub_module_input" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - -sed -i "s?top top?top ${moduleName}?" ez.work/$ECO_COMM/easyeco${POSTFIX}_setup.script - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/ezlec.sh b/src/UWE_projectCode/tmp/tmp/Scripts/ezlec.sh deleted file mode 100644 index 468b7bf..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/ezlec.sh +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -# You may add the directory of the ezlec executable to PATH by $ export PATH=$PATH: -# or modify the "ezlec" below to the absolute path of ezlec executable -# Options description: -# old_file_list and new_file_list: paths to the file containing the list of RTL files. -# old_root and new_root: root module name in the old/new design from which the comparison starts. -# output_dir: path to the output directory -# rtlec_log_file: path to the RTL-EC log file -#ezlec --old_file_list old.f --new_file_list new.f \ - -moduleName=`tclsh setModuleName.tcl` -echo $moduleName - -while read line -do - echo $line - R1_PATH=`echo $line` - echo $R1_PATH -done < dc.work/R1_PATH.txt - -if [ -d ./ez.work/R1src ]; then - echo "R1 src already exit" -else - cp $R1_PATH/update_RTL_SVN.sh ./src/ - cd src - chmod +x update_RTL_SVN.sh - ./update_RTL_SVN.sh - rm ./update_RTL_SVN.sh - cd - - mkdir ./ez.work/R1src - cp -r ./src/* ./ez.work/R1src/ - grep 'Opening include file' $R1_PATH/dc.log > ez.work/R1src/R1_filelist.f - sed -i 's?Opening include file ./src?./ez.work/R1src?' ez.work/R1src/R1_filelist.f - sed -i 's?Opening include file ??' ez.work/R1src/R1_filelist.f - sed -i '/filelist/d' ez.work/R1src/R1_filelist.f -fi - -cd src -svn up -cd - - -cp -r ./src ./ez.work/$ECO_COMM/ - -ezeco -in ./ez.work/$ECO_COMM/easyeco_setup.script -write_ungroup_info_from_svf -cp old_ungroup_list.rpt ez.work/${ECO_COMM}/old_ungroup_list.rpt -cp new_ungroup_list.rpt ez.work/${ECO_COMM}/new_ungroup_list.rpt - -if [ ${moduleName} == "gsm_sub_top" ]; then - OLD_TOP=gsm_top - NEW_TOP=gsm_top -else - OLD_TOP=${moduleName} - NEW_TOP=${moduleName} -fi - -echo ${LAST_ECO} -if [ ${LAST_ECO} == "" ]; then - OLD_FILE=ez.work/R1src/R1_filelist.f -else - OLD_FILE=${LAST_ECO}/ECO_filelist.f -fi -echo ${OLD_FILE} - -echo ${PP} -grep 'Opening include file' ${PP}/dc.log > ez.work/${ECO_COMM}/ECO_filelist.f -sed -i 's?Opening include file ??' ez.work/${ECO_COMM}/ECO_filelist.f -sed -i '/filelist/d' ez.work/${ECO_COMM}/ECO_filelist.f - -ezlec --old_file_list ${OLD_FILE} --new_file_list ./ez.work/${ECO_COMM}/ECO_filelist.f \ - --old_top ${OLD_TOP} --new_top ${NEW_TOP} \ - --old_root ${moduleName} --new_root ${moduleName} \ - --output_dir ez.work/${ECO_COMM} \ - --old_flatten_paths_list old_ungroup_list.rpt \ - --new_flatten_paths_list new_ungroup_list.rpt \ - --rtlec_log_file ez.work/${ECO_COMM}/rtlec.log diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/filelist_gen.sh b/src/UWE_projectCode/tmp/tmp/Scripts/filelist_gen.sh deleted file mode 100644 index 0fb6d6a..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/filelist_gen.sh +++ /dev/null @@ -1,58 +0,0 @@ -echo "######################################################################" -echo "=====================Filelist_Generator===============================" -echo "This script is used for generating the initial version of the filelist" -echo "for your designed unit. Users should modified it manually in order to " -echo "make it correct for both simulation and synthesis. " -echo "Currently, only .h .vh .v .vp are supported. If other files are needed" -echo "to be included, please do it manually! " -echo "======================================================================" -echo "This script is generated by LI CHEN. 2020.05.28." -echo "======================================================================" -echo "######################################################################" - - -dir=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -moduleName=`tclsh setModuleName.tcl` - -if [ ! -d ${dir}/src/${moduleName} ]; then - echo "Source code is not exist, exit." - exit -fi - -echo "The source code path is $dir/src/${moduleName}, the module name is $moduleName" - -#echo "Please type the dir name of your design unit: " -#read dir - -if [ -e ${dir}/src/${moduleName}/${moduleName}_filelist.v ]; then - mv ${dir}/src/${moduleName}/${moduleName}_filelist.v ${dir}/src/${moduleName}/${moduleName}_filelist_before.v -fi - -if [ `find $dir/src/${moduleName} -name "*.h"` ]; then - echo "//=============define files==============" >>${dir}/src/${moduleName}/${moduleName}_filelist.v -fi - -for hfile in `find $dir/src/${moduleName} -name "*.h"` -do - echo '`'"include" '"'$hfile'"' >> ${dir}/src/${moduleName}/${moduleName}_filelist.v -done - -for vhfile in `find $dir/src/${moduleName} -name "*.vh"` -do - echo '`'"include" '"'$vhfile'"' >> ${dir}/src/${moduleName}/${moduleName}_filelist.v -done - -echo "//=============design files==============" >> ${dir}/src/${moduleName}/${moduleName}_filelist.v - - -for vfile in `find $dir/src/${moduleName} -name "*.v"` -do - echo '`'"include" '"'$vfile'"' >> ${dir}/src/${moduleName}/${moduleName}_filelist.v -done - -for vpfile in `find $dir/src/${moduleName} -name "*.vp"` -do - echo '`'"include" '"'$vpfile'"' >> ${dir}/src/${moduleName}/${moduleName}_filelist.v -done - -echo "${dir}/src/${moduleName}/${moduleName}_filelist.v is generated successfully!" diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/get_CURRENT_DESIGN.sh b/src/UWE_projectCode/tmp/tmp/Scripts/get_CURRENT_DESIGN.sh deleted file mode 100644 index 331dcb2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/get_CURRENT_DESIGN.sh +++ /dev/null @@ -1,3 +0,0 @@ -design=`tclsh setModuleName.tcl` -echo $design - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/get_DBs_info.sh b/src/UWE_projectCode/tmp/tmp/Scripts/get_DBs_info.sh deleted file mode 100644 index bfa7227..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/get_DBs_info.sh +++ /dev/null @@ -1,23 +0,0 @@ -moduleName=`tclsh setModuleName.tcl` -echo $moduleName - -PP=`setPP.sh` -echo "PP = ${PP}" - -grep '\.db' ${PP}/report/${moduleName}_area.txt > tmp.log - -sed -i "1i\ " RTL_DC_info.log -sed -i "1i\################################" RTL_DC_info.log -while read line -do - #echo $line - d=`echo $line | cut -d' ' -f3` - #echo $d - p=${d%/*} - dd=${d##*/} - ddd=${dd%)*} - #echo $ddd - #echo $p - sed -i "1i\# Use $ddd in `realpath $p`" RTL_DC_info.log -done < tmp.log -sed -i "1i\######### DBs Info###############" RTL_DC_info.log diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/get_PROJECT_PATH.sh b/src/UWE_projectCode/tmp/tmp/Scripts/get_PROJECT_PATH.sh deleted file mode 100644 index a2c4401..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/get_PROJECT_PATH.sh +++ /dev/null @@ -1,3 +0,0 @@ -dir=`tclsh ProjectPathSetting.tcl` -echo $dir - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/quick_start b/src/UWE_projectCode/tmp/tmp/Scripts/quick_start deleted file mode 100644 index f7bcf24..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/quick_start +++ /dev/null @@ -1,70 +0,0 @@ -echo "######################################################################" -echo "=====================quick start===============================" -echo "This script is used for generating the initial version of the files " -echo "used by synthesizing. Users should modified files manually if necessary." -echo "======================================================================" -echo "This script is generated by LIU CHANG. 2020.05.28." -echo "======================================================================" -echo "Last modifed 2020.05.29." -echo "======================================================================" -echo "######################################################################" - -if [ -e ProjectPathSetting.tcl ]; then - echo "project path is exist" -else - read -p "Please type the PROJECTPATH : " projectpath - n=${projectpath%?} - c1="${projectpath##$n}" - if [ "$c1" == "/" ]; then - projectpath_=$n - else - projectpath_=$projectpath - fi - echo $projectpath_ - echo "set PROJECTPATH ${projectpath_}" > ProjectPathSetting.tcl - echo 'puts ${PROJECTPATH}' >> ProjectPathSetting.tcl - echo "ProjectPathSetting.tcl is generated successfully!" -fi - -if [ -e ./src ]; then - echo "./src is exist." -else - read -p "Please type the source code path: " sourcecodepath - ln -s ${sourcecodepath} ./src - echo "./src soft link is created." -fi - -if [ -e setModuleName.tcl ]; then - echo "../setModuleName.tcl is exist." -else - read -p "Please type the name of top module: " moduleName - echo "set Design ${moduleName}" > setModuleName.tcl - echo 'puts ${Design}' >> setModuleName.tcl - echo " setModuleName.tcl is created." - - cp -r $RELATIVEPATH/Template/* ./ - touch tmp.log - echo "copy files in Template here." - - filelistpath=`find ./src/ -maxdepth 1 -name '*flist*' -type f` - echo $filelistpath - filelistname=${filelistpath#*src/} - echo $filelistname - echo '`'"include" '"./'$filelistname'"' > ./dc.work/filelist.v - - incdirlistpath=`find ./src/ -maxdepth 1 -name '*incdir*' -type f` - echo $incdirlistpath - incdirlistname=${incdirlistpath#*src/} - echo $incdirlistname - echo -f ./src/$incdirlistname \ > ./nc.work/sim_filelist.f - - echo ./dc.work/filelist.v \ >> ./nc.work/sim_filelist.f - echo " " >> ./nc.work/sim_filelist.f - echo //Add simulation files bellow >> ./nc.work/sim_filelist.f - echo "./$moduleName/dc.work/filelist.v is generated successfully!" - echo "./$moduleName/nc.work/sim_filelist.f is generated successfully!" - mv ./spyglass.work/demo.prj ./spyglass.work/$moduleName.prj - mv ./spyglass.work/waiver/demo.awl ./spyglass.work/waiver/$moduleName.awl -fi - - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/report_dc_summary.sh b/src/UWE_projectCode/tmp/tmp/Scripts/report_dc_summary.sh deleted file mode 100644 index 4e9d183..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/report_dc_summary.sh +++ /dev/null @@ -1,74 +0,0 @@ -#!/bin/sh - -moduleName=`tclsh setModuleName.tcl` -echo $moduleName - -PP=`setPP.sh` -echo "PP = ${PP}" - -if [ ! -f dc.work/syn_summary.log ]; then - echo "Date"$'\t'$'\t'"|"$'\t'"RTL"$'\t'"|"$'\t'"Area"$'\t'$'\t'$'\t'"(Comb Area,"$'\t'$'\t'"NonComb Area,"$'\t'"Block Area )"$'\t'"|"$'\t'"Cells"$'\t'"(Comb Cells,"$'\t'"Seq Cells)"$'\t'"|"$'\t'"Slack(reg2reg)" > dc.work/syn_summary.log -fi - -PP_date=${PP#*dc.work/${moduleName}_} -echo "PP_date = $PP_date" - -Revision=`grep 'Revision' RTL_DC_info.log` -RTL=`echo $Revision | cut -d' ' -f2` -echo RTL = $RTL - -area=`grep 'Cell Area' ${PP}/report/${moduleName}_qor.txt` -Area=`echo $area | cut -d' ' -f3` -echo Area = $Area - -Conarea=`grep 'Combinational Area:' ${PP}/report/${moduleName}_qor.txt` -ConArea=`echo $Conarea | cut -d' ' -f3` -echo ConArea = $ConArea - -NonConarea=`grep 'Noncombinational Area:' ${PP}/report/${moduleName}_qor.txt` -NonConArea=`echo $NonConarea | cut -d' ' -f3` -if [ -z $NonConArea ]; then - NonConarea=`grep -A1 'Noncombinational Area:' ${PP}/report/${moduleName}_qor.txt | grep -A1 -v 'Noncombinational Area:'` - NonConArea=`echo $NonConarea | cut -d' ' -f1` -fi -echo NonConArea = $NonConArea - -Blockarea=`grep 'Noncombinational Area:' ${PP}/report/${moduleName}_qor.txt` -BlockArea=`echo $Blockarea | cut -d' ' -f4` -if [ -z $BlockArea ]; then - Blockarea=`grep -A1 'Macro/Black Box Area:' ${PP}/report/${moduleName}_qor.txt | grep -A1 -v 'Macro/Black Box Area:'` - BlockArea=`echo $Blockarea | cut -d' ' -f1` -fi -echo BlockArea = $BlockArea - -cell=`grep 'Leaf Cell Count' ${PP}/report/${moduleName}_qor.txt` -cellNum=`echo $cell | cut -d' ' -f4` -echo Cells = $cellNum - -Comcell=`grep 'Combinational Cell Count' ${PP}/report/${moduleName}_qor.txt` -ComcellNum=`echo $Comcell | cut -d' ' -f4` -echo ComCells = $ComcellNum - -Seqcell=`grep 'Sequential Cell Count' ${PP}/report/${moduleName}_qor.txt` -SeqcellNum=`echo $Seqcell | cut -d' ' -f4` -echo SeqCells = $SeqcellNum - -slack=`grep -A4 'reg2reg' ${PP}/report/${moduleName}_qor.txt | grep 'Critical Path Slack:'` -Slack=`echo $slack | cut -d' ' -f4` -echo Slack = $Slack - -#grep '.db' ${PP}/report/${moduleName}_area.txt > tmp.log -# -#while read line -#do -# #echo $line -# d=`echo $line | cut -d' ' -f3` -# #echo $d -# p=${d%/*} -# dd=${d##*/} -# ddd=${dd%)*} -# #echo $ddd -# #echo $p -#done < tmp.log - -echo "$PP_date"$'\t'"$RTL"$'\t'"$Area"$'\t'"$ConArea"$'\t'"$NonConArea"$'\t'"$BlockArea"$'\t'$'\t'"$cellNum"$'\t'$'\t'"$ComcellNum"$'\t'$'\t'"$SeqcellNum"$'\t'$'\t'$'\t'"$Slack" >> dc.work/syn_summary.log diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/runAll.sh b/src/UWE_projectCode/tmp/tmp/Scripts/runAll.sh deleted file mode 100644 index 771edd8..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/runAll.sh +++ /dev/null @@ -1,108 +0,0 @@ -MODULES=(DDR_top PCIE_Top RapidIO_top DMA0_wrapper RA14S_top SMC_BankMem) -MASK=( 1 1 1 1 0 1) - -i=0 -for m in ${MODULES[@]} -do - echo $i ${MASK[$i]} - if [ ${MASK[$i]} == 1 ]; then - echo $m - if [ $m == SMC_BankMem ]; then - gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../SMC_Top; make flow; cd ../../; touch ${m}_done.tmp; exec csh" - else - gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../../; touch ${m}_done.tmp; exec csh" - fi - fi - i=$(($i+1)) -done - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - i=0 - k=0 - for m in ${MODULES[@]} - do - if [ ${MASK[$i]} == 1 ]; then - if [ -f ${m}_done.tmp ]; then - echo $i $m "continue" - i=$(($i+1)) - continue - else - echo $i $m "break" - k=1 - break - fi - fi - i=$(($i+1)) - done - if [ $k == 0 ]; then - j=0 - fi -done - -gnome-terminal --geometry=100x30+100*$i+0 --window --title="M8024V_SuperNode" -x csh -c "cd Syn_SubModule/M8024V_SuperNode; make flow; cd ../../; touch M8024V_SuperNode_done.tmp; exec csh" - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - k=0 - if [ ! -f M8024V_SuperNode_done.tmp ]; then - echo "M8024V_SuperNode break" - k=1 - else - echo "M8024V_SuperNode continue" - fi - if [ $k == 0 ]; then - j=0 - fi -done - -date=`date +%Y_%m%d_%H%M` -echo $date -reportfile=flow_${date}.report -touch reportfile -i=0 -for m in ${MODULES[@]} -do - if [ ${MASK[$i]} == 1 ]; then - echo $m >> $reportfile - cat Syn_SubModule/${m}/R0_check.result >> $reportfile - echo " " >> $reportfile - echo " " >> $reportfile - fi - i=$(($i+1)) -done - -echo "M8024V_SuperNode:" >> $reportfile -cat Syn_SubModule/M8024V_SuperNode/R0_check.result >> $reportfile -echo " " >> $reportfile -echo " " >> $reportfile - -gnome-terminal --geometry=100x30+110*$i+0 --window --title="M8024V_FullChip" -x csh -c "cd Syn_Top; make flow; cd ..; touch M8024V_FullChip_done.tmp; exec csh" - -j=1 -while [ $j == 1 ] -do - echo "sleep 1" - sleep 1 - k=0 - if [ ! -f M8024V_FullChip_done.tmp ]; then - echo "M8024V_FullChip break" - k=1 - else - echo "M8024V_FullChip continue" - fi - if [ $k == 0 ]; then - j=0 - fi -done - -echo "M8024V_FullChip:" >> $reportfile -cat Syn_Top/R0_check.result >> $reportfile - -rm *_done.tmp diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/setPP.sh b/src/UWE_projectCode/tmp/tmp/Scripts/setPP.sh deleted file mode 100644 index 2acb7a6..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/setPP.sh +++ /dev/null @@ -1,12 +0,0 @@ -dir=`tclsh ./Tcls/ProjectPathSetting.tcl` -moduleName=`tclsh ./Tcls/setModuleName.tcl` -#echo $dir -#echo $moduleName -if [ ${PP} == "./" ]; then - #echo "PP = ./" - find ./dc.work -maxdepth 1 -name "${moduleName}_202*" | sort > tmp.log - PP=`tail -n 1 tmp.log` - echo ${PP} -else - echo ${PP} -fi diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/tab_change b/src/UWE_projectCode/tmp/tmp/Scripts/tab_change deleted file mode 100644 index a1459d5..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/tab_change +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh -#author: wdzs-liusheng -#date:2018.7.18 -PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl` -if grep -n " " -r $PROJECTPATH -R --include=*.{v,sv} re . - then - echo -e "there is TAB in the .v or .sv file of your directory. \c" - echo -e "please type N=2/4/8, here N means replacing 1*TAB with N*BLANKSPACE. \c" - echo -e "Usually, in UltraEdit N=2; in DVT, N=4; and in Nedit, N=8." - echo -e "N=\c"; - read N - case $N in - 2) sed -i "s/\t/ /g" `grep " " -rl $PROJECTPATH --include=*.{v,sv} re .`;; - 4) sed -i "s/\t/ /g" `grep " " -rl $PROJECTPATH --include=*.{v,sv} re .`;; - 8) sed -i "s/\t/ /g" `grep " " -rl $PROJECTPATH --include=*.{v,sv} re .`;; - esac - else - echo "there is no TAB in the .v or .sv file of your directory" -fi - diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/temp_files_cleaner.sh b/src/UWE_projectCode/tmp/tmp/Scripts/temp_files_cleaner.sh deleted file mode 100644 index affb9af..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/temp_files_cleaner.sh +++ /dev/null @@ -1,41 +0,0 @@ -echo "############################################################" -echo "This script is used for deleting temporary files and .svn files" -echo "Created by LI CHEN, 2020/5/28 ." -echo "###########################################################" - -echo "Please type the directory you want to delete temporary files and .svn files: " -read arg - -cd $arg - -find . -name "*.bak" -find . -name "*~" -find . -name "*.log" -find . -name "*.swp" -echo "Are you sure to delete these files? (y/n)" -read arga - -case $arga in -Y|y) -rm -f `find . -name "*.bak"` -rm -f `find . -name "*~"` -rm -f `find . -name "*.log"` -rm -f `find . -name "*.swp"` -echo "Deleted!" -;; -*) -;; -esac - -echo "Do you want to delete .svn in this dir? (y/n)" -read argb - -case $argb in -Y|y) rm -rf `find . -name ".svn"` -echo "Deleted!" - ;; -*) -;; -esac - -#deleting more files or directories can be extendied. diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/tmp.log b/src/UWE_projectCode/tmp/tmp/Scripts/tmp.log deleted file mode 100644 index e69de29..0000000 diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/warning_find.perl b/src/UWE_projectCode/tmp/tmp/Scripts/warning_find.perl deleted file mode 100644 index 27b42b1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/warning_find.perl +++ /dev/null @@ -1,9 +0,0 @@ -#! /usr/bin/perl -open(USER,"dc.log") || die "can't open"; -open(Data,">warning.txt") || die "can't open"; -while(){chomp;if($_ eq ""){next;} if($_=~/#+/){next;} -if(/Warning\:/) {print Data "$_\n";} -#if(/Error\:/) {print Data "$_\n";} -} -close(USER); -close(Data); diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/#syn_main.tcl# b/src/UWE_projectCode/tmp/tmp/Tcls/#syn_main.tcl# deleted file mode 100644 index b79db47..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/#syn_main.tcl# +++ /dev/null @@ -1,345 +0,0 @@ -set run_dc true -set run_pt false - -set RTL_DC_ID "" -set RTL_SIM_ID "" - -source -echo "./ProjectPathSetting.tcl" - -#-------------------------------------------------------------- -# NOTE: CHANGE DESIGN NAME TO YOUR OWN -source -echo "./setModuleName.tcl" - -source -echo "${PROJECTPATH}/syn/synopsys_dc.setup" - -if { [string match *FullChip $Design]} then { - echo "current design is $Design" - #source -echo "RTL_SIM_ID.tcl" - #source -echo "RTL_DC_ID.tcl" - if { $RTL_DC_ID != $RTL_SIM_ID} then { - echo "RTL_DC_ID != RTL_SIM_ID" - echo "RTL_DC_ID = $RTL_DC_ID" - echo "RTL_SIM_ID = $RTL_SIM_ID" - return - } -} - -#-------------------------------------------------------------- -#Reload ddc -echo $env(LOADDDC) -if { $env(LOADDDC) == "TRUE"} { - read_ddc $env(PP)/report/${Design}.ddc - return -} -#-------------------------------------------------------------- -set dc_date [exec date +%Y_%m%d_%H%M] -exec mkdir dc.work/${Design}_${dc_date} -exec mkdir dc.work/${Design}_${dc_date}/result -exec mkdir dc.work/${Design}_${dc_date}/report - -remove_design -all - -#-------------------------------------------------------------- - -set view_command_win {true} -set_host_options -max_cores 16 - -set compile_enable_async_mux_mapping {true} -set template_naming_style {%s_%p} -set template_parameter_style {%d} -set template_separator_style {_} - -set hdl_keep_licenses {false} -set hdlin_ff_always_async_set_reset {true} -set hdlin_latch_always_async_set_reset {true} -set hdlin_ff_always_sync_set_reset {false} -##set hdlin_use_carry_in true -set hdlin_check_no_latch {true} -set hdlin_mux_size_limit {32} -set hdlin_shorten_long_module_name true -set hdlin_while_loop_iterations 8192 -set hdlin_module_name_limit 128 - -set verilogout_equation {false} -set verilogout_single_bit {false} -set verilogout_higher_designs_first {true} -set verilogout_no_tri {true} -#set verilogout_show_unconnected_pins {false} -set verilogout_show_unconnected_pins {true} - -define_name_rules M2G_MODULE_LEVEL -allowed "A-Z a-z 0-9 _" ; -define_name_rules M2G_MODULE_LEVEL -first_restricted "0-9" ; -define_name_rules M2G_MODULE_LEVEL -replacement_char "_" ; -define_name_rules M2G_MODULE_LEVEL -collapse_name_space ; -define_name_rules M2G_MODULE_LEVEL -case_insensitive ; -define_name_rules M2G_MODULE_LEVEL -remove_internal_net_bus ; -define_name_rules M2G_MODULE_LEVEL -equal_ports_nets ; -define_name_rules M2G_MODULE_LEVEL -add_dummy_nets ; -define_name_rules M2G_MODULE_LEVEL -max_length 128 -type port ; -define_name_rules M2G_MODULE_LEVEL -max_length 64 -type cell ; -define_name_rules M2G_MODULE_LEVEL -max_length 64 -type net ; - -set default_name_rules M2G_MODULE_LEVEL ; - -set bus_dimension_separator_style {_} -set bus_naming_style {%s[%d]} -set bus_range_separator_style {:} -set bus_inference_descending_sort {true} -set bus_inference_style {%s[%d]} -#set write_name_nets_same_as_ports {false} -set write_name_nets_same_as_ports {true} -set bus_minus_style {-%d} -set bus_extraction_style {%s[%d:%d]} - -set change_names_dont_change_bus_members {false} -set uniquify_naming_style %s_%d - -set compile_instance_name_prefix {U} -set compile_instance_name_suffix {} - -set compile_preserve_subdesign_interfaces {true} -set compile_assume_fully_decoded_three_state_busses {false} -set compile_disable_hierarchical_inverter_opt {true} -set enable_recovery_removal_arcs {false} - -set fsm_auto_inferring {true} -set gen_show_created_symbols {true} -set case_analysis_with_logic_constants {true} -set power_cg_auto_identify {true} -set compile_auto_ungroup_count_leaf_cells {true} -set compile_auto_ungroup_override_wlm {true} - -set compile_delete_unloaded_sequential_cells {true} -set compile_seqmap_propagate_constants {true} -set compile_seqmap_propagate_high_effort {true} -set compile_seqmap_propagate_constants_size_only {true} - -set_svf dc.work/${Design}_${dc_date}/report/${Design}.svf - -#-------------------------------------------------------------- -#void warning Info # -#-------------------------------------------------------------- -#suppress_message HDL-193 -#suppress_message LINT-45 -#suppress_message OPT-1056 -#suppress_message PWR-877 -#set suppress_errors {VHDL-2285} - -#-------------------------------------------------------------- -#read↦ link↦ Check design# -#-------------------------------------------------------------- -source -echo "./dc.work/specific_filelist.tcl" -analyze -f SVERILOG -library work -vcs "-f ./nc.work/sim_filelist.f" -redirect -append -file dc.log {elaborate $Design} -current_design $Design -#link -if { [link] == 0} { - echo "Link failed!" - echo $env(CHECKCODE) - if { $env(CHECKCODE) == "TRUE"} { - exit - } - return -} - -#**set timing_enable_multiple_clocks_per_reg true -check_design > dc.work/${Design}_${dc_date}/report/${Design}_check_design.txt - -echo $env(CHECKCODE) -if { $env(CHECKCODE) == "TRUE"} { - echo "Link success!" - exit -} - -#-------------------------------------------------------------- -# set library -# NOTE: ADD YOUR OWN LIBRARY -# ------------------------------------------------------------- -#set_operating_conditions ssg_cworst_max_0p81v_m40c -#set zerowireload Zero -#set auto_wire_load_selection false -#set_wire_load_mode top -##set_wire_load_model -name "$zerowireload" [current_design] -#current_design $Design -source -echo "${PROJECTPATH}/syn/set_library.tcl" - -#------------------------------------------------------------------ -#set_dont_use -source -echo "${PROJECTPATH}/syn/dont_use.tcl" -#------------------------------------------------------------------ - -#remove_license HDL-Compiler - -#change name before compile -report_names -rules verilog -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_1.rpt -redirect -append -file dc.log {change_names -rules verilog -hierarchy -verbose} -report_names -rules M2G_MODULE_LEVEL -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_2.rpt -redirect -append -file dc.log {change_names -rules M2G_MODULE_LEVEL -hierarchy -verbose} - - -#-------------------------------------------------------------- -# read clock set and input output constraints -# NOTE: CHANGE FILE NAME TO YOUR OWN -# --------------------------------------------------------------- -echo $env(DEBUGSDC) -if { $env(DEBUGSDC) == "TRUE"} { - return -} - -redirect -append -file dc.log {source -echo "$env(SDCPATH)/${Design}.sdc"} -source -echo "$env(SDCPATH)/synopsys.sdc" - -#----------------------------------------------------------------- -#set dont_touch design -#----------------------------------------------------------------- -source -echo ./dc.work/syn_specific.tcl - -uniquify -dont_skip_empty_designs - -#---------------------------------------------------------------------------- -#set UPF file -#NOTE: -# -#load_upf MatrixIP_top_u2.upf -#set upf_allow_DD_primary_with_supply_sets true -#set_voltage 0.81 -object_list {VDD VDD1sw VDD2sw} -#set_voltage 0.0 -object_list {VSS} -##insert_mv_cells -isolation -verbose -#check_mv_design -verbose - -#-------------------------------------------------------------- -#check design -report_port -verbose > dc.work/${Design}_${dc_date}/report/${Design}_port.txt -report_clock > dc.work/${Design}_${dc_date}/report/${Design}_clock.txt - - -set_fix_multiple_port_nets -all -buffer_constants -feedthroughs [ get_designs "*" ] - -current_design $Design - -#set_ultra_optimization true - -set_max_dynamic_power 0.0 - -#ungroup -all -flatten - -#set ports_clock_root [filter_collection [get_attribute [get_clocks] sources] object_class==port] -#group_path -name REGOUT -to [all_outputs] -#group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root] -#group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs] - -group_path -name in2reg -from [all_inputs] -critical_range 1000.0 -group_path -name reg2out -to [all_outputs] -critical_range 1000.0 -group_path -name in2out -from [all_inputs] -to [all_outputs] -critical_range 1000.0 -group_path -name reg2reg -from [all_registers] -to [all_registers] -critical_range 1000.0 - -#set_compile_directives -constant_propagation true [get_cells -hierarchical *] - -set_cost_priority -delay -set_critical_range 0.2 $Design -redirect -append -file dc.log {remove_unconnected_ports [get_cells -hier * ] } - -check_design > dc.work/${Design}_${dc_date}/report/${Design}_check_design_aftercom.txt -analyze_datapath_extraction > dc.work/${Design}_${dc_date}/report/${Design}_analyze_datapath_extraction.rpt - -compile_ultra -no_autoungroup -timing_high_effort -gate_clock -no_seq_output_inversion -scan -#compile_ultra -no_autoungroup -timing_high_effort -gate_clock -no_seq_output_inversion - -#foreach_in_collection desig [remove_from_collection [get_designs "*"] [get_designs {FADDSUB_top}]] { -# lappend rename_design_list $desig -#} - -#rename_design $rename_design_list -prefix FADDSUB_ -rename_design [remove_from_collection [get_designs "*"] $Design] -prefix ${Design}_ - - -#-------------------------------------------------------------- -#write_report - -if { [llength [get_cells main_gate -hier -filter "clock_gating_logic == true"]] != 0 } { - remove_clock_gating_check [get_cells main_gate -hier -filter "clock_gating_logic == true"] -} - - -report_names -rules verilog -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_3.rpt -redirect -append -file dc.log {change_names -rules verilog -hierarchy -verbose} -report_names -rules M2G_MODULE_LEVEL -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_4.rpt -redirect -append -file dc.log {change_names -rules M2G_MODULE_LEVEL -hierarchy -verbose} - -#write_report -write -format verilog -hierarchy $Design -output dc.work/${Design}_${dc_date}/result/${Design}.sv -write -format ddc -hierarchy -output dc.work/${Design}_${dc_date}/report/${Design}.ddc -report_timing -max 1000 -transition_time -capacitance > dc.work/${Design}_${dc_date}/report/${Design}_timing.txt -report_constraint -all_violators > dc.work/${Design}_${dc_date}/report/${Design}_constraint.txt -write_script > dc.work/${Design}_${dc_date}/report/${Design}.sdc -write_sdc -nosplit dc.work/${Design}_${dc_date}/report/${Design}.sdc -report_design > dc.work/${Design}_${dc_date}/report/${Design}_design.txt -report_reference -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_reference.rpt -report_net > dc.work/${Design}_${dc_date}/report/${Design}_net.rpt -report_names -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_names.rpt -report_resources -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_resource.rpt -report_multibit -hier > dc.work/${Design}_${dc_date}/report/${Design}_multibit.rpt -report_power > dc.work/${Design}_${dc_date}/report/${Design}_power.txt -report_qor > dc.work/${Design}_${dc_date}/report/${Design}_qor.txt -report_clock_tree_power > dc.work/${Design}_${dc_date}/report/${Design}_clkpower.txt -report_clock_gating > dc.work/${Design}_${dc_date}/report/${Design}_clock_gating.txt -report_area -nosplit -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_area.txt -report_timing -max 100 -transition_time -capacitance -group in2reg > dc.work/${Design}_${dc_date}/report/${Design}_in2reg -report_timing -max 100 -transition_time -capacitance -group reg2out > dc.work/${Design}_${dc_date}/report/${Design}_reg2out -report_timing -max 100 -transition_time -capacitance -group in2out > dc.work/${Design}_${dc_date}/report/${Design}_in2out -report_timing -max 100 -transition_time -capacitance -group reg2reg > dc.work/${Design}_${dc_date}/report/${Design}_reg2reg -check_timing -include {gated_clock clock_crossing} > dc.work/${Design}_${dc_date}/report/${Design}_check_timing.rpt -#report_timing \ -# -path full_clock \ -# -transition_time \ -# -crosstalk_delta \ -# -capacitance \ -# -input_pins \ -# -nets \ -# -delay max \ -# -derate \ -# -max_paths 100 > ${dc_date}/timing/${DESIGN}_${dc_date}_timing_dc.txt -# - -set_svf -off - -check_mv_design -verbose > dc.work/${Design}_${dc_date}/report/${Design}_check_upf.log - -#remove_design -hierarchy MatrixIP_Core_Scalar_PG -#remove_design -hierarchy MatrixIP_Core_Vector_PG - -#write -format verilog -hierarchy $Design -output dc.work/${Design}_${dc_date}/result/${Design}_hier.sv -#exec rm ../Netlist_9T_125C/${Design}.v -#exec cp dc.work/${Design}_${dc_date}/result/${Design}.sv ../Netlist_9T_125C/${Design}.v -#-------------------------------------------------------------- -#quit - -set dc_date0 [exec date +%Y_%m%d_%H%M] -echo ${dc_date} ${dc_date0} - -exec $env(SCRIPTPATH)/get_DBs_info.sh -exec $env(SCRIPTPATH)/report_dc_summary.sh -exec cp dc.work/${Design}_${dc_date}/report/${Design}_check_design.txt dc.work/${Design}_${dc_date}/check_design.txt -exec cp dc.work/${Design}_${dc_date}/report/${Design}_check_timing.rpt dc.work/${Design}_${dc_date}/check_timing.txt -exec cp dc.log dc.work/${Design}_${dc_date}/dc.log -exec cp command.log dc.work/${Design}_${dc_date}/command.log -exec cp RTL_DC_info.log dc.work/${Design}_${dc_date}/RTL_DC_info.log -exec cp RTL_DC_ID.tcl dc.work/${Design}_${dc_date}/RTL_DC_ID.tcl -exec cp update_RTL_SVN.sh dc.work/${Design}_${dc_date}/update_RTL_SVN.sh - -#remove_sdc -#source -echo "${PROJECTPATH}/syn/SDC/${Design}.sdc" - -source -echo "./dc.work/syn_specific_after.tcl" - -if { [file exists dc.work/${Design}_${dc_date}/result/${Design}.sv] == 1} { -exec mkdir NetlistSubmit/${Design}_${dc_date} -exec cp dc.work/${Design}_${dc_date}/result/${Design}.sv NetlistSubmit/${Design}_${dc_date}/ -exec cp dc.work/${Design}_${dc_date}/report/${Design}_qor.txt NetlistSubmit/${Design}_${dc_date}/ -#exec cp dc.work/${Design}_${dc_date}/report/${Design}_memory_clock.rpt NetlistSubmit/${Design}_${dc_date}/ -} - -echo $env(FLOW) -if { $env(FLOW) == "TRUE"} { - exit -} diff --git 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zUIjHOPH)jIMop}=4M^+g%WEG~Cz*kyN?Vpzdq-PoX;62xX)`vsNjFCNaQYkXxSH)X z?XHV;TCEPGNrfGrXG6n>^3l1J=JUwgl1?24(~2ELXdSZSAX>@J?weT$K`S_#3X?5X z3|je)^vR?g#{OF!$xruz)qu<$Jy}AiJm#;@Or^e97Hc~Zz(;* zq7@u(Ed+wo4{yHEb$`DuPLj};@u}JbCYEgYz_u|I(uYu0hZiBb4jf(#4njj~6|D{E z0F&}m7nDCsNP|x{S2CiMBugH0ar(*Zn`<=D$gN~Ie0hY6D}Cq}bUXeqf{1Qgx8~cCYH7aIy ${dc_date}/check_design.txt - -current_design $DESIGN -set timing_enable_multiple_clocks_per_reg true - -current_design $DESIGN -change_names -rules verilog -hierarchy -verbose > ${dc_date}/change_names_0.v - -set BACKEND false -source "../../SDC/$DESIGN.sdc" - -source "../../SDC/DontUseCells.sdc" - -set_dont_touch_network [all_clocks] - -report_clock -check_timing -include {gated_clock clock_crossing} > ${dc_date}/check_timing.txt - -current_design $DESIGN - -foreach_in_collection design_name [get_designs *] { - current_design $design_name - set_fix_multiple_port_nets -all -buffer_constants - set_fix_multiple_port_nets -feedthroughs - set_max_fanout 40 $design_name -} - -current_design $DESIGN - -#set_wire_load_mode segmented -remove_wire_load_model -set_operating_conditions SS0P99VN40C -set_wire_load_model -name ZeroWLM -uniquify -force - -set_ultra_optimization true -set compile_seqmap_propagate_constants true - -set_driving_cell -lib_cell STN_BUF_S_4 -library RHSTD_ss0p99vn40c [remove_from_collection [all_inputs] {clk rstn}] -set_input_transition 0.05 [all_inputs] -set_max_transition 0.1 $DESIGN -set_load 0.015 [all_outputs] -set_max_fanout 10 $DESIGN -set_max_fanout 1 [all_inputs] -set_fanout_load 10 [all_outputs] -set_max_area 0.0 -#set_max_dynamic_power 0.0 - -set_cost_priority -delay -set_critical_range 0.3 $DESIGN - -#compile_ultra -no_autoungroup -gate_clock -scan -compile_ultra -no_autoungroup -timing_high_effort_script -gate_clock -no_seq_output_inversion -scan -#set_max_capacitance 3.0 $DESIGN -#compile_ultra -incremental - -set_fix_multiple_port_nets -all -buffer_constants -feedthroughs -change_names -rules verilog -hierarchy -verbose > ${dc_date}/change_names_3.v - -write -format ddc -hierarchy $DESIGN -output ${dc_date}/ddc/${DESIGN}_${dc_date}_ultra.ddc - -report_area > ${dc_date}/area/${DESIGN}_${dc_date}_area_ultra.txt -report_power > ${dc_date}/power/${DESIGN}_${dc_date}_power_ultra.txt -report_area -nosplit -hierarchy > ${dc_date}/area/${DESIGN}_${dc_date}_area_ultra_ALL.txt -report_qor > ${dc_date}/qor/${DESIGN}_${dc_date}_qor.txt -report_constraint -all_violators > ${dc_date}/constraint/${DESIGN}_${dc_date}_constraint.txt -write_sdc -nosplit ${dc_date}/sdc/${DESIGN}_${dc_date}.sdc -#report_transitive_fanout -clock_tree > ${dc_date}/clock.info - - -#report_timing -max 50 > ${dc_date}/timing/${DESIGN}_${dc_date}_setup.rpt -#report_timing -delay min -max 50 > ${dc_date}/timing/${DESIGN}_${dc_date}_hold.rpt - -report_timing \ - -path full_clock \ - -transition_time \ - -crosstalk_delta \ - -capacitance \ - -input_pins \ - -nets \ - -delay max \ - -derate \ - -max_paths 100 > ${dc_date}/timing/${DESIGN}_${dc_date}_timing_detailed.txt - -set_svf -off - -write -format verilog -hierarchy $DESIGN -output ${dc_date}/result/${DESIGN}_${dc_date}_ultra.v - -check_timing -include {gated_clock clock_crossing} > ${dc_date}/check_timing_1.txt - -exec date - -exit diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/cdc_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/cdc_goal.tcl deleted file mode 100644 index 3361831..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/cdc_goal.tcl +++ /dev/null @@ -1,120 +0,0 @@ -#--------------------------------------------------------- -# CDC Hierarchical flow settings -#--------------------------------------------------------- -#set_option decompile_block_constraints yes -#set_option abstract_file_name_style short -#set_option include_block_interface abstract -#set_option use_block_interface yes - -#--------------------------------------------------------- -# sdc constraint to check cdc settings -#--------------------------------------------------------- -#set_option sdc2sgdc yes -#set_option sdc2sgdcfile ./${top-module-name}.sdc2sgdc.out - -#--------------------------------------------------------- -# CDC goal settings -#--------------------------------------------------------- -proc cdc_setup_check_add_settings {} { - -#set_option sdc_domain_mode sta_scg -#set_parameter sdc_generated_clocks yes; ## sdc generated clocks translated as sgdc clocks -#set_parameter pt supermode ; ##supports largest set of SDC queries -#set_parameter show_all_sdc_violations yes ; ##enables reporting of *all* issues in sdc -#set_parameter tc_ignored_commands sdc_ignored.txt; ## file containing list of sdc commands to be ignored for cdc -#set_parameter tc_stop_parsing_ignored_commands yes; ## avoids parsing of sdc commands ignored in tc_ignored_commands file -set_parameter use_inferred_abstract_port no -set_goal_option overloadrules { Reset_check12+severity=Error+msgLabel=NORMAL_WARNING Reset_check12+severity=Info+msgLabel=CORNER_WARNING } -} - -proc cdc_verify_struct_add_settings {} { - -#set_goal_option addrule { Ac_abstract01 } ; ##used for CDC hierarchical flow -#set_goal_option block_abstract yes ; ##used for CDC hierarchical flow -set_goal_option report { CDC-detailed-report SynchInfo moresimple} -set_parameter dump_sync_info detailed_mod -set_parameter show_module_in_spreadsheet yes -set_parameter enable_ac_sync_qualdepth yes -set_parameter conv_sync_as_src yes -set_parameter conv_src_seq_depth 0 -set_parameter check_multiclock_bbox yes -set_parameter cdc_qualifier_depth 3 -set_parameter conv_sync_seq_depth 1 -set_parameter handle_combo_arc yes -set_parameter allow_combo_logic yes -set_parameter report_common_reset yes -set_parameter allow_merged_qualifier strict -set_parameter show_clock_tag_debug_data yes - -set_goal_option addrules { Clock_sync05a Clock_sync06a } -set_goal_option overloadrule { Clock_sync05a+severity=Error } -set_goal_option overloadrule { Clock_sync06a+severity=Error } -set_goal_option overloadrules Reset_sync02+severity=Error - -#set_parameter enable_sync no ; ## disable automatically recognize synchronization scheme -#set_parameter enable_clock_gate_sync no ;## disable automatically recognize synchronization scheme -#set_parameter enable_multiflop_sync no ; ## disbale automatically recognize synchronization scheme -#set_parameter enable_mux_sync none ; ## disable automatically recognize synchronization scheme -#set_parameter enable_and_sync no ; ## disable automatically recognize synchronization scheme -#set_parameter glitch_protect_cell "gp_and,gp_mux" ; ## specify glitch protect cell naem - -#set_parameter synchronize_cells "sync1,sync2" ; ## user defined synchronizer for scalar control signal -#set_parameter reset_synchronize_cells "sync1,sync2" ; ## user defined synchronizer for scalar control signal -#set_parameter synchronize_data_cells "sync1,sync2" ; ## user defined synchronizer for vector control signal -#set_parameter msg_inst_mod_report all ; ## - -#set_parameter report_all_flops yes ; ## report all flops for Reset_sync02 -#set_parameter enable_reset_cone_spreadsheet yes ; ## enable spreadsheet for Reset_sync02 -} - -proc cdc_verify_add_settings {} { - -#set_parameter fa_proof_mode cdr; ## enable coverage driven formal (cdf) mode -#set_parameter fa_enable_cdr_coverage yes; ## with previous -#set_parameter fa_enable_cdr_reactive no; ## with previous -#set_parameter fa_coverage_witness yes; ## show waveform for partially-proved in cdf mode -#set_parameter fa_atime 200; ## increase maximum time (in sec) spent verifying each property -#set_parameter fa_enable_rca yes; ## enable root cause analysis for 0% coverage and vacuously-proved properties -##set_parameter fa_msgmode audit; ## enable cdc_verify to create property file then quit without verifying -##set_parameter fa_propfile ; ## enables manual selection of properties to verify (useful for focusing effort) -#set_parameter cdc_bus_compress none; ## make Ac_glitch03 and Ac_cdc01a check all bits of vectored destination -set_parameter cdc_dump_assertions sva -set_parameter fa_audit yes - -} - -current_goal cdc/cdc_setup -#set_goal_option addrules {Setup_port01 Setup_blackbox01} -current_goal none - -current_goal cdc/cdc_setup_check -read_file -type awl waiver/cdc.awl -cdc_setup_check_add_settings -current_goal none - - - - -current_goal cdc/clock_reset_integrity -read_file -type awl waiver/cdc.awl - -current_goal none - - - - -current_goal cdc/cdc_verify_struct -read_file -type awl waiver/cdc.awl -cdc_setup_check_add_settings -cdc_verify_struct_add_settings -current_goal none - - - - -current_goal cdc/cdc_verify -read_file -type awl waiver/cdc.awl -cdc_setup_check_add_settings -cdc_verify_struct_add_settings -cdc_verify_add_settings -current_goal none diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/common_options.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/common_options.tcl deleted file mode 100644 index 5735127..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/common_options.tcl +++ /dev/null @@ -1,22 +0,0 @@ -set_option project_read_only yes -set_option mthresh 1000000 -set_option dw yes -set_option disable_amg yes -set_option show_lib yes -set_option allow_duplicate_files true -set_option allow_module_override yes -set_option sort yes -set_option prefer_tech_lib yes -set_option enable_pgnetlist_all_products yes -set_option enable_pgnetlist yes -set_option max_err_count 0 -set_option perflog yes -set_option enable_unified_naming_search yes -set_option nosavepolicies all -set_option report_max_inst {-1} -set_option report_inst_backref yes -set_option report_ip_waiver yes -set_option enable_elapsed_time yes -set_option disable_html_report {datasheet dashboard html} -set_option pragma {synopsys synthesis} - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/compile.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/compile.tcl deleted file mode 100644 index a33e599..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/compile.tcl +++ /dev/null @@ -1,34 +0,0 @@ -sh mkdir synopsysdc -sh mkdir synopsysdc/grlib -define_design_lib grlib -path synopsysdc/grlib -sh mkdir synopsysdc/techmap -define_design_lib techmap -path synopsysdc/techmap -sh mkdir synopsysdc/gaisler -define_design_lib gaisler -path synopsysdc/gaisler -sh mkdir synopsysdc/work -define_design_lib work -path synopsysdc/work -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/stdlib/version.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/stdlib/config.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/stdlib/stdlib.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/stdlib/stdio.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/util/util.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/amba/amba.vhd -analyze -f VHDL -library grlib $PROJECTPATH/LEON3LIB/grlib/amba/devices.vhd -analyze -f VHDL -library techmap $PROJECTPATH/SPI/gencomp.vhd -analyze -f VHDL -library gaisler $PROJECTPATH/LEON3LIB/gaisler/uart/uart.vhd -analyze -f VHDL -library work $PROJECTPATH/UART/CONV.vhd -analyze -f VHDL -library work $PROJECTPATH/UART/CONV_1.vhd -analyze -f VHDL -library work $PROJECTPATH/UART/apbuart.vhd -analyze -f VHDL -library work $PROJECTPATH/UART/apbuart_top.vhd -analyze -f VHDL -library techmap $PROJECTPATH/SPI/SPI_syncram_2p_tx.vhd -analyze -f VHDL -library techmap $PROJECTPATH/SPI/SPI_syncram_2p_rx.vhd -analyze -f VHDL -library gaisler $PROJECTPATH/SPI/spictrlx_extended.vhd - -if {$DESIGN=={SMC_Top}} then { -analyze -f SVERILOG -library work -define {_USE_SYNED_COREPAC_ _USE_SYNED_SMC_BANKPORT_} $PROJECTPATH/DM6672VList.v -} else { -analyze -f SVERILOG -library work -define {_USE_SYNED_COREPAC_} $PROJECTPATH/DM6672VList.v -} - -analyze -f VERILOG -library work $PROJECTPATH/CorePac/MBIST_Ctrl/mgc_utility.v - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/copyLib.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/copyLib.tcl deleted file mode 100644 index 28fdda7..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/copyLib.tcl +++ /dev/null @@ -1,25 +0,0 @@ -source -echo "$env(RELATIVEPATH)/ProjectPathSetting.tcl" -set run_dc true -source "${PROJECTPATH}/syn/synopsys_dc.setup" - -#echo $design_library - -foreach lib $design_library { - set strs [string trimright $lib db] - #echo $strs - if {$strs == "cdn_hs_phy_top."} { - break - } - echo ${strs}lib - #78-82 - exec find /space/PRJ_Back_End/FT-M8024V/ -name ${strs}lib | xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - exec find /space/PRJ_Back_End/FT-M8024V/ -name "u028efuhc01603218400_wc.lib" | grep "V1P1" | xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - #only read ,cann't gzip - exec find /space/PRJ_Back_End/FT-M8024V/ -name "*FXTDC012NSHJ0C_ssg0p81vm40c.lib*" | xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - #two - exec find /space2/Library/UMC28HPC/IP -name "*FXPLL357HJ0C_ssg0p81vm40c.lib*" | grep -v "Z-old_version" |xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - exec find /space/PRJ_Back_End/FT-M8024V/ -name "*TCSU2802_core_WC.lib*" |xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - exec find /space/PRJ_Back_End/FT-M8024V/ -name "*foj0c_qrs18_io_ssg0p81v1p62vm40c.lib*" | grep "V1.6.7" | xargs -n1 -I \{\} cp \{\} ${PROJECTPATH}/syn/db-8024/tmp - #echo $libs -} -exit diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/custom_options.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/custom_options.tcl deleted file mode 100644 index b3c0265..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/custom_options.tcl +++ /dev/null @@ -1,48 +0,0 @@ -#--------------------------------------------------------- -# Increase the threshold limit for the size of the macro -# in order to completely simulate the macro. -# Resolve FLAT_504 message -#--------------------------------------------------------- -set_option define_cell_sim_depth 14 - -#--------------------------------------------------------- -# Enable module based report for block owner to review -#--------------------------------------------------------- -#set_option enable_module_based_reporting yes - -#--------------------------------------------------------- -# Option to enable SystemVerilog syntax -#--------------------------------------------------------- -set_option enableSV09 yes - -#--------------------------------------------------------- -# Option to enable Verilog2005 syntax -#--------------------------------------------------------- -set_option enableV05 yes - -#--------------------------------------------------------- -# Libraries setting -#--------------------------------------------------------- -#set_option v /path/to/your/library/file.v -#set_option y /path/to/your/library/directory -#set_option libext { .v .sv .vhd .vh } - -#--------------------------------------------------------- -# define macro and include file path setting -#--------------------------------------------------------- -#set_option define your-macro -#set_option incdir /path/to/your/include/directory - - -#--------------------------------------------------------- -# grey box or blackbox setting -#--------------------------------------------------------- -#set_option stop eth_miim -#set_option stop module-name -set_option stop DW_lp_fp_multifunc -#set_option stopfile RTL-file-name -#set_option stopdir HDL-directory -#set_option ignoredu module-name -#set_option ignorefile RTL-file-name -#set_option ignoredir HDL-directory - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/formality.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/formality.tcl deleted file mode 100644 index 71ae6f6..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/formality.tcl +++ /dev/null @@ -1,136 +0,0 @@ -source "./ProjectPathSetting.tcl" - -exec date - -source "./setModuleName.tcl" - -set PP [exec bash $env(SCRIPTPATH)/setPP.sh] -echo "PP = ${PP}" - -set netlistfile ./${PP}/result/$Design.sv -#set sdcfile ./${PP}/report/$Design.sdc -set svffile ./${PP}/report/$Design.svf - -############################################ -#setup -############################################ -set run_dc false -set run_pt false -set synopsys_auto_setup true -#set hdlin_unresolved_modules black_box -#set hdlin_dwroot /space/CAD_Front_End/Synopsys2013/H-2013.03-SP2/ -#set hdlin_dwroot /CAD/Synopsys2015/syn_vK-2015.06/ -set hdlin_dwroot /space/CAD_Front_End/Synopsys2019/syn/ - -if {$Design=={PCIE_Top}} then { -set hdlin_ignore_translate true -set verification_verify_unread_tech_cell_pins false -} - -############################################ -#SVF -############################################ -set_svf $svffile - -source -echo "${PROJECTPATH}/syn/synopsys_dc.setup" - -############################################ -#Read db -############################################ -#read_db RHSTD_ss0p99vn40c.db -read_db $link_library - -if {$Design=={SMC_Top}} then { -read_db $PROJECTPATH/syn/db_sc12l28/SMC_BankMem.db -} - -############################################ -#RTL code -############################################ -if { [string match *fullchip* $Design]} then { -echo "current design is $Design" -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/stdlib/version.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/stdlib/config.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/stdlib/stdlib.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/stdlib/stdio.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/util/util.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/amba/amba.vhd -read_vhdl -container r -libname grlib $PROJECTPATH/src/LEON3LIB/grlib/amba/devices.vhd -read_vhdl -container r -libname techmap $PROJECTPATH/src/SPI/rtl/gencomp.vhd -read_vhdl -container r -libname gaisler $PROJECTPATH/src/SPI/rtl/SPI_syncram_2p_tx.vhd -read_vhdl -container r -libname gaisler $PROJECTPATH/src/SPI/rtl/SPI_syncram_2p_rx.vhd -read_vhdl -container r -libname gaisler $PROJECTPATH/src/SPI/rtl/spictrlx_extended.vhd -} - -read_sverilog -container r -libname work -define {_USE_SYNED_COREPAC_} -f ./nc.work/sim_filelist.f - -###read_verilog -container r -libname work $PROJECTPATH/CorePac/MBIST_Ctrl/mgc_utility.v - -set_top r:/work/$Design - - -############################################ -#netlist -############################################ -read_verilog -container i -libname work -01 $netlistfile - -set_top i:/work/$Design - -if {$Design=={PCIE_Top}} then { -set_constant -type port r:/WORK/PCIE_Top/mbist_en 0 -set_constant -type port i:/WORK/PCIE_Top/mbist_en 0 -set_constant -type port r:/WORK/PCIE_Top/test_en 0 -set_constant -type port i:/WORK/PCIE_Top/test_en 0 -set_constant -type port r:/WORK/PCIE_Top/test_clk 0 -set_constant -type port i:/WORK/PCIE_Top/test_clk 0 -set_constant -type port r:/WORK/PCIE_Top/scan_reset 0 -set_constant -type port i:/WORK/PCIE_Top/scan_reset 0 - -} -############################################ -#match -############################################ -#if {$Design=={RapidIO_top}} then { -#set_constant -type port r:/WORK/RapidIO_top/mbist_en 0 -#set_constant -type port i:/WORK/RapidIO_top/mbist_en 0 -#} - -match - -############################################ -#verify -############################################ -if {$Design=={M8024V_FullChip}} then { -set_dont_verify { -r:/WORK/M8024V_FullChip/AAAA_M8024V_top/AAA_efuse/efuse_ctrl_state/u028efuhc01603218400/VDD -r:/WORK/M8024V_FullChip/AAAA_M8024V_top/AAA_efuse/efuse_ctrl_state/u028efuhc01603218400/VSS -r:/WORK/M8024V_FullChip/AAAA_M8024V_top/AAA_efuse/efuse_ctrl_state/u028efuhc01603218400/VQPS -} -} - -if {$Design=={M66AK_FullChip}} then { -set_dont_verify { -r:/WORK/M66AK_FullChip/AAAA_M66AK/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VDD -r:/WORK/M66AK_FullChip/AAAA_M66AK/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VSS -r:/WORK/M66AK_FullChip/AAAA_M66AK/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VQPS -} -} - -if {$Design=={M6674_FullChip}} then { -set_dont_verify { -r:/WORK/M6674_FullChip/AAAA_M6674/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VDD -r:/WORK/M6674_FullChip/AAAA_M6674/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VSS -r:/WORK/M6674_FullChip/AAAA_M6674/AAA_EFUSE/efuse_ctrl_state/u028efuhc01603218400/VQPS -} -} - -verify - -exec date - -exec cp fm.log ${PP}/fm.log -exec cp formality_svf/svf.txt ${PP}/fm_svf.txt - -exit - -##debug## diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/genus_flow.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/genus_flow.tcl deleted file mode 100644 index ac7dbbf..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/genus_flow.tcl +++ /dev/null @@ -1,644 +0,0 @@ - -#if {[file exists /proc/cpuinfo]} { -# sh grep "model name" /proc/cpuinfo -# sh grep "cpu MHz" /proc/cpuinfo -#} -# -#puts "Hostname : [info hostname]" - -############################################################################## -## Preset global variables and attributes -############################################################################## - -source -echo "./ProjectPathSetting.tcl" - -source -echo "./setModuleName.tcl" -#set Design fullchip_top -#for example : set Design M66AK_FullChip - -######set Generic & Map & Optional's effort -set GEN_EFF medium -set MAP_OPT_EFF high -set DATE [clock format [clock seconds] -format "%b%d-%T"] -#set ET_WORKDIR -set _OUTPUTS_PATH ${Design}_${DATE}/outputs_${DATE} -set _REPORTS_PATH ${Design}_${DATE}/reports_${DATE} -set _LOG_PATH ${Design}_${DATE}/logs_${DATE} -set_db invs_temp_dir ${Design}_${DATE}/invs_temp_dir_${DATE} -set_db innovus_executable "/space/CAD_Back_End/Cadence20/INNOVUS20.11.000-ISR1/bin/innovus" -set_db statistics_log_data true -set_db source_verbose true -set_db / .information_level 9 - -##Uncomment and specify machine names to enable super-threading. -###set_db / .super_thread_servers {} -###For design size of 1.5M - 5M gates, use 8 to 16 CPUs. For designs > 5M gates, use 16 to 32 CPUs -set_db / .max_cpus_per_server 32 - -set_db init_blackbox_for_undefined false -set_db ui_respects_preserve false -##Default undriven/unconnected setting is 'none'. -set_db / .hdl_unconnected_value none -set_db hdl_track_filename_row_col true -set_db "message:GLO-32" .truncate false -set_db "message:GLO-34" .truncate false - -############################################################################## -#set lib or hdl search path -############################################################################### -set_db / .init_lib_search_path " \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/SerDes/Latest/pma/timing/9M_2Xa1Xd_h_3Xe_vhv_2Z/lib_pg/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/SerDes_X1/Latest/pma/timing/1P11M_DV_3DM_Q1_3Q2_2B_2TMa_ALPA2_14SHK/lib_pg/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/Memory/Latest/memory_lib_dbs/ssgs_ccw0p72vn40c/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/RVT/lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/LVT/lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/ULVT/lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/VTsensor/Latest/Lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/PLL/P1232/Latest/lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/GPIO/Latest/syn/1p8v/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/efuse/Latest/S14NSFPEFUSE_PIPO1KB_V0.2.3/Lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/PSensor/Latest/Lib/ \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/SerDes/Latest \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/SerDes/Latest/upcs/include \ - /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/SerDes/Latest/phy/include \ - /space/PRJ_Front_End/M7004V/src/DSPCORE/ARF/lib/ \ - /space/PRJ_Front_End/M7004V/src/DSPCORE/VRF/lib/ \ - $PROJECTPATH/syn/db \ - " -set_db / .init_hdl_search_path " \ - ./src \ - /home/admin/liuchang/M7004V/src/LEON3LIB/grlib/stdlib \ - /home/admin/liuchang/M7004V/src/LEON3LIB/grlib/util \ - /home/admin/liuchang/M7004V/src/LEON3LIB/gaisler/uart \ - /home/admin/liuchang/M7004V/src/LEON3LIB/grlib/amba \ - /home/admin/liuchang/M7004V/src/SPI/rtl \ - " - -############################################################### -## Library setup -############################################################### -set_db library "RHSTD_LVT_ssg0p72vm40c_ccs.lib" - -read_libs " \ - RHSTD_LVT_ssg0p72vm40c_ccs.lib \ - RHSTD_RVT_ssg0p72vm40c_ccs.lib \ - RHSTD_ULVT_ssg0p72vm40c_ccs.lib \ - S14NSFPVT_V0.1.1_ssg_V1p62v0p72_-40C.lib \ - P1232_ssg0p72vm40c.lib \ - SPC14NSFPD18RN_ss_V0p72_-40C.lib \ - S14NSFPEFUSE_PIPO1KB_V0.1.1_ssg_V1p62v0p72_-40C.lib \ - S14NSFPPS_V0.1.1_ssg_V0p72_-40C.lib \ - AM_RAM1024W39B.lib \ - ARF_16X36_6W_7R_WC.lib \ - VRF_32X32_8W_14R_WC.lib \ - BTB.lib \ - CAC_RAM_TP_128W67.lib \ - CrossNet_MEM32W100.lib \ - CrossNet_MEM32W120.lib \ - CrossNet_MEM32W68.lib \ - CrossNet_MEM32W84.lib \ - CrossNet_MEM256W33.lib \ - CrossNet_MEM256W54.lib \ - CrossNet_MEM256W58.lib \ - CrossNet_MEM256W61.lib \ - DCACHE_DATA.lib \ - DCACHE_DATA_ECC.lib \ - DCACHE_TAG.lib \ - DCACHE_TAG_ECC.lib \ - DMA_RFSP64W39B.lib \ - GHB.lib \ - gsm_data_sp_8192w137b.lib \ - gsm_tag_sp_1024w23b.lib \ - ICACHE_DATA.lib \ - ICACHE_TAG.lib \ - IP.lib \ - L1P_RAMSP256W23B.lib \ - L1P_RAMSP256W33B.lib \ - L2CACHE_DATA_ECC_4K.lib \ - L2CACHE_TAGS.lib \ - L2_PREFETCH_STRIDE_QUEUE.lib \ - L2_SNOOP_TAG.lib \ - L2_TLB.lib \ - RAMSP512W13B.lib \ - RAMSP512W28B.lib \ - RAMSP_D768W76.lib \ - RAMTP_D128W72.lib \ - RAMTP_D32W100.lib \ - RAMTP_D32W118.lib \ - RAMTP_D32W46.lib \ - RAMTP_D32W66.lib \ - RAMTP_D32W84.lib \ - RAMTP_D32W72.lib \ - RAMTP_D352W72.lib \ - RAMTP_D416W74.lib \ - RAMTP_D48W70.lib \ - RAMTP_D512W15.lib \ - RAMTP_D512W74.lib \ - RAMTP_D544W32.lib \ - RAMTP_D544W40.lib \ - RBL_512w64b_ROM0.lib \ - RBL_512w64b_ROM1.lib \ - RBL_512w64b_ROM2.lib \ - RBL_512w64b_ROM3.lib \ - SPI_syncram_2p.lib \ - Txfifo_512x76.lib \ - xgmac_dmi_sram.lib \ - xgmac_ec_ef_sram.lib \ - xgmac_fifo.lib \ - dwc_e25mp_pma_x4_ns_ss0p72vn40c_cworst_CCworst_pg.lib.gz \ - dwc_e25mp_pma_x1_ns_ss0p72vn40c_rcworst_CCworst_pg.lib \ - RA14S_1024x72.lib \ - RA14S_32x72.lib \ - SRIO_SP_256W40.lib \ - SRIO_SP_64W128.lib \ - SRIO_SP_64W16.lib \ - SRIO_TP_1024W36.lib \ - SRIO_TP_128W12.lib \ - SRIO_TP_128W20.lib \ - SRIO_TP_128W30.lib \ - SRIO_TP_128W76.lib \ - SRIO_TP_256W13.lib \ - SRIO_TP_256W70.lib \ - SRIO_TP_256W84.lib \ - SRIO_TP_288W72.lib \ - SRIO_TP_320W10.lib \ - SRIO_TP_320W128.lib \ - SRIO_TP_32W102.lib \ - SRIO_TP_32W70.lib \ - SRIO_TP_32W84.lib \ - SRIO_TP_32W88.lib \ - SRIO_TP_512W72.lib \ - SRIO_TP_512W74.lib \ - SRIO_TP_64W70.lib \ - SRIO_TP_64W92.lib \ - gsm_sub_top.lib \ - CORTEXA15.lib \ - gsm_top.lib \ - mt32_core_wrapper.lib \ - RA14S_top.lib \ - SRIO_top.lib \ - dmu.lib \ - " - -#set_operating_conditions ssgnp_0p675v_125c_cworst_CCworst_T -#source -echo "../common/dc_setup.tcl" -#source -echo "../common/dc_file_RH.tcl" - -#################################################################################### -#Physical Flow needs the files (LEF CAP_TABLE QRC DEF) -################################################################################### -#set_db / .init_lef_files "" -####You can read lef files in two ways. read_physical -lef or source -echo "...." -####read_physical -lef -#read_physical -lef "/space3/Library/SMIC12SFe/Techfile/PRTechFile/INNOVUS_12SFE_9T_v1p0b/TF/1P11M_DV_3DM_Q1_3Q2_2B_2TMa_ALPA2.lef \ -# /space3/Library/SMIC12SFe/Techfile/PRTechFile/INNOVUS_12SFE_9T_v1p0/TF/DFM_via_SFP/1P11M_DV_3DM_Q1_3Q2_2B_2TMa_DFM_via_SFP.lef \ -# /space/PRJ_Back_End/FT-M7004V_RH/CoreLib/Latest/LVT/lef/RHSTD_LVT.lef \ -# /home/project/FT-M7004V_RH/GPIO/Latest/lef/SPC14NSFPD18RN_1P11M_DV_3DM_Q1_3Q2_2B_2TMa.lef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM32W100/CrossNet_MEM32W100.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM32W68/CrossNet_MEM32W68.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM32W84/CrossNet_MEM32W84.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM32W120/CrossNet_MEM32W120.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM256W33/CrossNet_MEM256W33.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM256W54/CrossNet_MEM256W54.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM256W58/CrossNet_MEM256W58.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/crossnet/CrossNet_MEM256W61/CrossNet_MEM256W61.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/spi/SPI_syncram_2p/SPI_syncram_2p.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/rgmii/Txfifo_512x76/Txfifo_512x76.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/boot/RBL_512w64b_ROM1/RBL_512w64b_ROM1.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/boot/RBL_512w64b_ROM2/RBL_512w64b_ROM2.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/boot/RBL_512w64b_ROM0/RBL_512w64b_ROM0.plef \ -# /home/project/FT-M7004V_RH/Memory/Latest/memory/boot/RBL_512w64b_ROM3/RBL_512w64b_ROM3.plef \ -# /home/project/FT-M7004V_RH/PLL/P1232/Latest/lef/P1232.lef \ -# /home/project/FT-M7004V_RH/efuse/V1P0/S14NSFPEFUSE_PIPO1KB_V0.2.3/Lef/S14NSFPEFUSE_PIPO1KB_V0.2.3_5M.lef \ -# /space3/Library/7004V/Block_B4DFT/CORTEXA15/lef/CORTEXA15.lef \ -# /space3/Library/7004V/Block_B4DFT/gsm_sub_top/lef/gsm_sub_top.lef \ -# /space3/Library/7004V/Block_B4DFT/mt32_core_wrapper/lef/mt32_core_wrapper.lef \ -# /space3/Library/7004V/Block_B4DFT/pcie_top_wrapper/lef/pcie_top_wrapper_H.lef \ -# /space3/Library/7004V/Block_B4DFT/RA14S_top/lef/RA14S_top.lef \ -# /space3/Library/7004V/Block_B4DFT/SRIO_top/lef/SRIO_top_V.lef \ -# /space3/Library/7004V/Block_B4DFT/xgmac_x1_top_wrapper/lef/xgmac_x1_top_wrapper.lef \ -# /home/project/FT-M7004V_RH/VTsensor/Latest/Lef/S14NSFPVT_V0.3.1_6M.lef" - -#source -echo "/space3/Library/7004V/Block_B4DFT/FullChip_top/lef/fullchip_top.lef" -###for example : source -echo "lef_for_M66AK_FullChip.tcl" -## Provide either cap_table_file or the qrc_tech_file -#set_db / .cap_table_file "........." -#for example : set_db / .cap_table_file "/space2/Library/UMC28HPC/arm_tech/r14p0/cadence_captable/1p8m1a1u/Cmax.captbl" -#read_qrc "/space3/Library/SMIC12SFe/Techfile/QRC/SMIC_CCIQRC_12SFE_0818_1P11M_DV_3DM_Q1_3Q2_2B_2TMa_ALPA2_14SHK_V1.0_REV4_1/rulefiles/CMAX/qrcTechFile" -#for example : read_qrc "/space2/Library/UMC28HPC/Techfile/QRC/UMC_G-DF-LOGIC_MIXED_MODE28N-1P8M1A1U-HPC_AL28K_QRC-LPE_V0.4.P1/Cmax/qrcTechFile" -##generates _reg[] format -## - - - -################################################# -#Making DRC the Highest Priority -################################################### - -set_db / .drc_first true - - - -############################################# -#Datapath -############################################### -set_db dp_analytical_opt standard - - - -########################################################### -#insert clock gate -############################################################ -set_db / .lp_insert_clock_gating true - - - - -#################################################################### -## Load Design -#################################################################### -read_hdl -f ./nc.work/sim_filelist.f -#read_hdl -language sv -define _SYN_TOP_ "sys_filelist.v" -#read_hdl "../../../netlist_toDFT/RH/fullchip_top/AsyncClockSwitching_3_0_0.v ../../../netlist_toDFT/RH/fullchip_top/AsyncClockSwitching_2_0_0.v" -read_hdl -language vhdl -library grlib stdio.vhd -read_hdl -language vhdl -library grlib config.vhd -read_hdl -language vhdl -library grlib version.vhd -read_hdl -language vhdl -library grlib stdlib.vhd -read_hdl -language vhdl -library grlib amba.vhd - -read_hdl -language vhdl -library grlib util.vhd -read_hdl -language vhdl -library gaisler uart.vhd -read_hdl -language vhdl -library grlib devices.vhd -read_hdl -language vhdl -library techmap gencomp.vhd -read_hdl -language vhdl -library grlib spictrlx_extended.vhd -read_hdl -language vhdl -library grlib SPI_syncram_2p_rx.vhd -read_hdl -language vhdl -library grlib SPI_syncram_2p_tx.vhd -#for example:read_hdl -sv "66xDSPList_2.v" - -elaborate $Design -puts "Runtime & Memory after 'read_hdl'" -time_info Elaboration - -init_design -check_design -unresolved -check_timing_intent - -exit - - -#create_ple_model $Design -out_file PLE_file -################################################################################## -#DEF -#################################################################################### -#set_db read_def_libcell_mismatch_error false -#read_def "/space3/Library/7004V/Block_B4DFT/FullChip_top/def/fullchip_top.def.gz" -#for example: read_def "/home/user/dft/jn/FT-M66AK/DEF/M66AK_FullChip.def" - - - -##################################################################### -### Constraints Setup -##################################################################### -read_sdc "/home/user1/dft1/FT-M7004V/netlist_toDFT/RH/fullchip_top/fullchip_top.sdc" -#for example:read_sdc /home/user/dft/jn/FT-M66AK/GENUS_FULLCHIP_CWORST/submit/M66AK_FullChip/M66AK_FullChip.sdc - - - - -####################################################################### -#create new directory -####################################################################### -# -if {![file exists ${_LOG_PATH}]} { - file mkdir ${_LOG_PATH} - puts "Creating directory ${_LOG_PATH}"} - -## -if {![file exists ${_OUTPUTS_PATH}]} { - file mkdir ${_OUTPUTS_PATH} - puts "Creating directory ${_OUTPUTS_PATH}" -} -# -if {![file exists ${_REPORTS_PATH}]} { - file mkdir ${_REPORTS_PATH} - puts "Creating directory ${_REPORTS_PATH}" -} - - -################################################################################## -#Timing Setup -################################################################################## - -set_db time_recovery_arcs false - -#report_timing -lint -# -# - - -################################################################################### -#dont -#################################################################################### -#source -echo "/home/user/dft/jn/FT-M3000+/GENUS/VPE/common/set_dont_use.tcl" -#set_dont_touch mz_fmac -#set_dont_touch [get_cells -hierarchical -filter "ref_name == PREICG_X5B_A12PP140ZTR_C30"] -#set_dont_touch VRF_32X64_8W_14R_1 -#set_dont_touch VRF_32X64_8W_14R_0 -#[ -hierarchical | -of_objects list [-leaf] -#| pattern [-hsc string] [-regexp [-nocase]] ] -#[-quiet] -#get_cells [-hierarchical -filter ["ref_name == PREICG_X5B_A12PP140ZTR_C30"| "is_dont_touch {true}"] - - - -################################################################################### -## Define cost groups (clock-clock, clock-output, input-clock, input-output) -################################################################################### - -## Uncomment to remove already existing costgroups before creating new ones. -## delete_obj [vfind /designs/* -cost_group *] - -if {[llength [all_registers]] > 0} { - define_cost_group -name I2R -design $Design - define_cost_group -name R2O -design $Design - define_cost_group -name R2R -design $Design - - path_group -from [all_inputs] -to [all_registers] -group I2R -name I2R - path_group -from [all_registers] -to [all_outputs] -group R2O -name R2O - path_group -from [all_registers] -to [all_registers] -group R2R -name R2R -} - -define_cost_group -name I2O -design $Design -path_group -from [all_inputs] -to [all_outputs] -group I2O -name I2O -#foreach cg [vfind / -cost_group *] { -##Divide into corresponding PATH GROUPs and report -# report_timing -cost_group [list $cg] >> $_REPORTS_PATH/${Design}_pretim.rpt -#} -report_timing -group R2R > $_REPORTS_PATH/${Design}_R2R_pretim.rpt -report_timing -group I2R > $_REPORTS_PATH/${Design}_I2R_pretim.rpt -report_timing -group R2O > $_REPORTS_PATH/${Design}_R2O_pretim.rpt -report_timing -group I2O > $_REPORTS_PATH/${Design}_I2O_pretim.rpt - -#set_db auto_ungroup none -#ungroup -threshold 5 - - -################################################################################################## -## DFF ---> SDFF Mapping to Complex Sequential Cells -################################################################################################## - -set_db / .dft_scan_style muxed_scan -set_db / .dft_prefix DFT_ -# For VDIO customers, it is recommended to set the value of the next two attributes to false. -set_db / .use_scan_seqs_for_non_dft true -set_db "design:$Design" .dft_scan_map_mode force_all - - -###################################################################################### -##### Retime -###################################################################################### -# -# -#set rt_modules {module:/ module:/ module:/} -#foreach mod $rt_modules { -# set_db $mod .retime true -# ####Uncomment to prevent registers from being moved across the subdesign boundaries -# ##set_db $subd .retime_hard_region true -# ####Uncomment to minimize issues with Conformal LEC -# ##set_db $mod .boundary_opto false -#} -#####Setting 'retime' attribute on the top-level as shown below -#####is not recommended due to possible verification/ECO issues unless for very small designs -###set_db "design:$Design" .retime true -# -#####set dont_retime on registers which should not be retimed -#set dont_rt_flops "inst: inst: inst: ..." -#foreach rtf $rt_flops { -# set_db $rtf .dont_retime true -#} -## Enable verification flow -#set_db / .retime_verification_flow true - -#################################################### -#### To turn off sequential merging on the design -#### uncomment & use the following attributes. -set_db / .optimize_merge_flops true -set_db / .optimize_merge_latches true -#### For a particular instance use attribute 'optimize_merge_seqs' to turn off sequential merging. - - - -########################################### -#Setting Boundary Optimization -########################################### -set_db boundary_opto true -set_db boundary_optimize_constant_hpins true -set_db boundary_optimize_equal_opposite_hpins true -set_db boundary_optimize_feedthrough_hpins true -set_db boundary_optimize_invert_hpins true - - - -############################################## -#Optimizing Total Negative Slack -############################################## -set_db tns_opto true -set_db tns_critical_range 0.2 - -################################## -#Datapath -#################################### -set_db "design:$Design" .dp_csa basic -set_db dp_rewriting advanced -set_db dp_speculation basic -set_db dp_sharing advanced - - -###################################################### -# Allow merging of combinational hierarchical instances -###################################################### - -#set_db merge_combinational_hier_instances true - - - -############################################################### -#Low Power -################################################################## - -set_db "design:$Design" .lp_clock_gating_auto_cost_grouping true -set_db lp_clock_gating_infer_enable true - -#declone_clock_gate -hierarchical -##Power root attributes -#set_db / .lp_clock_gating_prefix -set_db / .lp_power_analysis_effort high -set_db / .lp_power_unit mW -set_db / .lp_toggle_rate_unit /ns -set_db "design:$Design" .lp_clock_gating_extract_common_enable true -set_db lp_insert_discrete_clock_gating_logic true - - - -####################################################################################### -## Leakage/Dynamic power/Clock Gating setup. -####################################################################################### -## The attribute has been set to default value "medium" -## you can try setting it to high to explore MVT QoR for low power optimization -set_db / .leakage_power_effort medium -#set_db "design:$Design" .lp_clock_gating_cell [vfind /lib* -lib_cell ] -#set_db "design:$Design" .max_leakage_power 0.0 -set_db "design:$Design" .lp_power_optimization_weight 0.99 -set_db "design:$Design" .max_dynamic_power 100 - -#set_db "design:$Design" .lp_clock_gating_test_signal -## read_tcf -## read_saif -## read_vcd - -#decrypt PLE_file - -#################################################################################################### -## Synthesizing to generic -#################################################################################################### - -set_db / .syn_generic_effort $GEN_EFF -syn_generic -physical - -puts "Runtime & Memory after 'syn_generic -physical'" -time_info GENERIC -report_dp > $_REPORTS_PATH/generic/${Design}_datapath.rpt -write_snapshot -outdir $_REPORTS_PATH -tag generic -report_summary -directory $_REPORTS_PATH - - -#### Build RTL power models -#build_rtl_power_models -design $Design -clean_up_netlist [-clock_gating_logic] [-relative ] -#report power -rtl - - - -#################################################################### -#Enabling Cell Merging to Multibit Cells -#################################################################### - -set_db use_multibit_cells true - -#################################################################################################### -## Synthesizing to gates -#################################################################################################### - - -## Add '-auto_identify_shift_registers' to 'syn_map' to automatically -## identify functional shift register segments. Not applicable for n2n flow. -set_db / .syn_map_effort $MAP_OPT_EFF - -set_db dp_ungroup_during_syn_map true -set_db optimize_net_area true - -syn_map -physical -puts "Runtime & Memory after 'syn_map -physical'" -time_info MAPPED -write_snapshot -outdir $_REPORTS_PATH -tag map -report_summary -directory $_REPORTS_PATH -report_dp > $_REPORTS_PATH/map/${Design}_datapath.rpt - - -#foreach cg [vfind / -cost_group *] { -# report_timing -cost_group [list $cg] > $_REPORTS_PATH/${Design}_[vbasename $cg]_post_map.rpt -#} -report_timing -group R2R > $_REPORTS_PATH/${Design}_R2R_post_map.rpt -report_timing -group I2R > $_REPORTS_PATH/${Design}_I2R_post_map.rpt -report_timing -group R2O > $_REPORTS_PATH/${Design}_R2O_post_map.rpt -report_timing -group I2O > $_REPORTS_PATH/${Design}_I2O_post_map.rpt - -###The files are used for conformal -write_do_lec -revised_design fv_map -logfile ${_LOG_PATH}/rtl2intermediate.lec.log > ${_OUTPUTS_PATH}/rtl2intermediate.lec.do - -####################################################################################################### -## Optimize Netlist -####################################################################################################### -set_db / .syn_opt_effort $MAP_OPT_EFF -syn_opt -physical -write_snapshot -outdir $_REPORTS_PATH -tag syn_opt -report_summary -directory $_REPORTS_PATH - -puts "Runtime & Memory after 'syn_opt -physical'" -time_info OPT - -#foreach cg [vfind / -cost_group *] { -# report_timing -cost_group [list $cg] > $_REPORTS_PATH/${Design}_[vbasename $cg]_post_opt.rpt -#} -report_timing -group R2R > $_REPORTS_PATH/${Design}_R2R_post_opt.rpt -report_timing -group I2R > $_REPORTS_PATH/${Design}_I2R_post_opt.rpt -report_timing -group R2O > $_REPORTS_PATH/${Design}_R2O_post_opt.rpt -report_timing -group I2O > $_REPORTS_PATH/${Design}_I2O_post_opt.rpt - - - -## Uncomment to remove assigns & insert tiehilo cells during Incremental synthesis -##set_db / .remove_assigns true -##set_remove_assign_options -buffer_or_inverter -design -##set_db / .use_tiehilo_for_const - -###################################################################################### -#incremental opto -###################################################################################### -#########Actually,incremental opto should be run in the Genus Physical Flow. -#########However,it always reports errors in this flow(3rd).This problem has not been solved yet.Thus,we shield incremental opto momentarily. -#########We can use incremental opto in 1st(Simple PLE Flow)\2nd(Spatial Flow) Flow and other cases except 3rd(Genus Physical Flow) Flow. - -## An effort of low was selected to minimize runtime of incremental opto. -## If your timing is not met, rerun incremental opto with a different effort level -#syn_opt -physical -incremental -#write_snapshot -outdir $_REPORTS_PATH -tag syn_opt_low_incr -#report_summary -directory $_REPORTS_PATH -#puts "Runtime & Memory after 'syn_opt -physical -incremental'" -#time_info INCREMENTAL_POST_SCAN_CHAINS - - -############################################# -#Preserving Instances and Modules -############################################## -set_db "design:$Design" .preserve true - - - -###################################################################################################### -## write backend file set (verilog, SDC, config, etc.) -###################################################################################################### -report_area -detail >$_REPORTS_PATH/${Design}_area_detail.rpt -report_clock_gating > $_REPORTS_PATH/${Design}_clockgating.rpt -report_power > $_REPORTS_PATH/${Design}_power.rpt -report_gates -power > $_REPORTS_PATH/${Design}_gates_power.rpt -report_area > $_REPORTS_PATH/${Design}_area.rpt -report_dp > $_REPORTS_PATH/${Design}_datapath_incr.rpt -report_messages > $_REPORTS_PATH/${Design}_messages.rpt -write_snapshot -outdir $_REPORTS_PATH -tag final -report_summary -directory $_REPORTS_PATH -write_hdl > ${_OUTPUTS_PATH}/${Design}_m.v -write_script > ${_OUTPUTS_PATH}/${Design}_m.script -write_sdc > ${_OUTPUTS_PATH}/${Design}_m.sdc -report_ple > $_REPORTS_PATH/ple.rpt -check_design -all > Check_D -write_design -innovus -#write_design -innovus > ${_OUTPUTS_PATH}/${Design}_genp_output.v -#write_design -innovus -base_name > invs_temp_dir/${Design}_genp_output.v - - -################################# -### write_do_lec -################################# -write_do_lec -golden_design fv_map -revised_design ${_OUTPUTS_PATH}/${Design}_m.v -logfile ${_LOG_PATH}/intermediate2final.lec.log > ${_OUTPUTS_PATH}/intermediate2final.lec.do -##Uncomment if the RTL is to be compared with the final netlist.. -write_do_lec -revised_design ${_OUTPUTS_PATH}/${Design}_m.v -logfile ${_LOG_PATH}/rtl2final.lec.log > ${_OUTPUTS_PATH}/rtl2final.lec.do - -puts "Final Runtime & Memory." -time_info FINAL -puts "============================" -puts "Synthesis Finished ........." -puts "============================" - -file copy [get_db / .stdout_log] ${_LOG_PATH}/. - -##quit diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/lib_to_db.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/lib_to_db.tcl deleted file mode 100644 index 382e1da..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/lib_to_db.tcl +++ /dev/null @@ -1,7 +0,0 @@ -set PP [exec bash $env(SCRIPTPATH)/setPP.sh] -echo "PP = ${PP}" - -source "setModuleName.tcl" -read_lib ./${PP}/result/$Design.lib -write_lib $Design -o ./${PP}/result/$Design.db -exit diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/lint_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/lint_goal.tcl deleted file mode 100644 index 7a532ad..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/lint_goal.tcl +++ /dev/null @@ -1,25 +0,0 @@ -#--------------------------------------------------------- -# Lint Hierarchical flow settings -#--------------------------------------------------------- -#set_option decompile_block_constraints yes -#set_option abstract_file_name_style short -#set_option include_block_interface abstract -#set_option use_block_interface yes - -#--------------------------------------------------------- -# Lint turbo flow settings -#--------------------------------------------------------- -#set_option turbo yes -#set_option smart_rule_execution yes -#set_option honor_spq_parameter_with_turbo yes -#set_option disable_turbo_param yes - -current_goal lint/lint_rtl -read_file -type awl $env(SPYGLASSWORK)/waiver/lint.awl -source $env(TCLPATH)/spyglass_lint_rules.tcl -#set_goal_option ignorerules {W164a W164b} -current_goal none - -current_goal lint/design_audit -set_goal_option report {Audit} -current_goal none diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/power_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/power_goal.tcl deleted file mode 100644 index 37b43cf..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/power_goal.tcl +++ /dev/null @@ -1,113 +0,0 @@ -#--------------------------------------------------------- -# power product specific options -#--------------------------------------------------------- -set_option enable_precompile_vlog no -set_option remove_work yes -set_option include_opt_data yes - -#--------------------------------------- -# Synthesis control settings -#--------------------------------------- -# Hierarchical boundary optimization (HBO) can be enabled if SpyGlass reported -# RTL design area is very much higher than reference design run area -# Change the below variable value to 'yes' to enable HBO in the relevant goals -set ENABLE_HBO_FLOW no - -#current_methodology $SPYGLASS_HOME/GuideWare/2018.09-EarlyAdopter/block/rtl_handoff -#--------------------------------------- -# Globally used parameter settings -#--------------------------------------- - -#Tcl proc which defines commonly used PE settings -proc pwr_recommended_est_setting_proc {} { - #global PROJECT_DIR_PATH - # Set the clock gating threshold to match that used by power synthesis - set_parameter sgsyn_clock_gating_threshold 3 - # Set the targeted synthesis to select scan flops - set_goal_option use_scan_flops yes - # Enables monitor on clock and enable nets to improve accuracy - set_parameter pe_enable_monitor_on_clock_nets yes - set_parameter pe_enable_monitor_on_enable_nets yes - #To increase amount of nets covered under monitors - set_parameter pe_logic_depth 25 - # Enable multi-process synthesis to save runtime - global env - if { [ file exists $env(TCLPATH)/synth_options.tcl ] } { - set_option sgsyn_opt_file $env(TCLPATH)/synth_options.tcl - } - #To display the additional clock-gating efficiency metrics - set_parameter pe_enable_advance_cgemetric 1 - set_parameter pe_num_unset_nets 2000000 - #set_parameter pe_generate_fsdb 1 - #set_parameter pe_enable_component_power_graph 1 - #set_parameter pe_enable_component_activity_graph 1 - #set_parameter pe_report_power_for_each_simfile 1 - #set_parameter pe_num_clock_cycles_avg_power 10 -} -# end pwr_recommended_est_setting_proc -################### Optional GOAL ################################## -## Grading vectors and finding activity hotspots ## -#################################################################### -current_goal power/power_activity_check - # Specifies the intervals (in terms of number of cycles of the fastest clock) - # at which activity values should be averaged. - set_parameter pe_num_clock_cycles_avg_act 100 - # Enables monitor on clock and enable nets to improve accuracy - set_parameter pe_enable_monitor_on_clock_nets yes - set_parameter pe_enable_monitor_on_enable_nets yes - set_parameter pe_num_unset_nets 2000000 -current_goal none - -################### Mandatory GOAL ################################# -## Power Audit for checking the data integrity ## -#################################################################### -current_goal power/power_audit - # Use settings defined in the Tcl proc - pwr_recommended_est_setting_proc -current_goal none - -proc DefinePowerEstGoal {goal_name} { - global ENABLE_HBO_FLOW - - ################### Optional GOAL ################################ - ## Power Estimation on Original RTL without calibration data ## - ################################################################## - #current_goal power/$goal_name -scenario NoCalibData - current_goal power/$goal_name - # Use settings defined in the Tcl proc - pwr_recommended_est_setting_proc - # HBO flow is enabled if the top level variable is set - if { $ENABLE_HBO_FLOW == "yes" } { - set_goal_option enable_hbo yes - } - ##Uncomment below parameters to display component power/activity graphs in n-cycle mode - #set_parameter pe_num_clock_cycles_avg_power 100 - #set_parameter pe_enable_component_power_graph 1 - #set_parameter pe_enable_component_activity_graph 1 - current_goal none - } -# end proc DefinePowerEstGoal - -#power_est_average : power estimation. -DefinePowerEstGoal power_est_average -#power_est_profiling : power estimation + profiling. -DefinePowerEstGoal power_est_profiling - -################### Recommended GOAL ############################### -## CGE profiling across multiple simulation files (New in 2017.03)## -## This is a LCA feature in 2017.03 and needs additional license ## -#################################################################### -#current_goal power/power_cge_profiling -scenario NoCalibData -current_goal power/power_cge_profiling - # Use settings defined in the Tcl proc - pwr_recommended_est_setting_proc - # HBO flow is enabled if the top level variable is set - if { $ENABLE_HBO_FLOW == "yes" } { - set_goal_option enable_hbo yes - } - - - - -current_goal none - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/pt.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/pt.tcl deleted file mode 100644 index af8ecad..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/pt.tcl +++ /dev/null @@ -1,84 +0,0 @@ -source "./ProjectPathSetting.tcl" - -set sh_enable_page_mode true -set power_enable_analysis true -set run_dc false -set run_pt true - -source "./setModuleName.tcl" -set pt_date [exec date +%Y_%m%d_%H%M] - -set PP [exec bash $env(SCRIPTPATH)/setPP.sh] -echo "PP = ${PP}" - -source "${PROJECTPATH}/syn/synopsys_dc.setup" - -set timing_non_unate_clock_compatibility true - -echo $env(FLAT) -if { $env(FLAT) == "TRUE"} { -source "./dc.work/filelist_pt.v" -set sdcfile1 $env(SDCPATH)/${Design}_flatten.sdc -} else { -set netlistfile ./${PP}/result/$Design.sv -set sdcfile1 $env(SDCPATH)/${Design}.sdc -} -#set sdcfile1 ./${PP}/report/$Design.sdc -set sdcfile2 ${PROJECTPATH}/syn/SDC/synopsys.sdc -set specialfile ./dc.work/syn_specific.tcl - -read_verilog $netlistfile -current_design $Design - -link_design - -source -echo $sdcfile1 -source -echo $sdcfile2 -source -echo $specialfile -source -echo "${PROJECTPATH}/syn/set_library.tcl" - -echo $env(DEBUGSDC) -if { $env(DEBUGSDC) == "TRUE"} { - return -} - -check_timing -include {clock_crossing} -verbose > check_timing_pt.txt -if { $env(FLAT) == "TRUE"} { -exec perl $env(SCRIPTPATH)/clock_cross.pl check_timing_pt.txt ${Design}_FLAT_clock_cross.log -} else { -exec perl $env(SCRIPTPATH)/clock_cross.pl check_timing_pt.txt ${Design}_clock_cross.log -} - -group_path -name in2reg -from [all_inputs] -group_path -name reg2out -to [all_outputs] -group_path -name in2out -from [all_inputs] -to [all_outputs] -group_path -name reg2reg -from [all_registers] -to [all_registers] - -report_timing -group [get_path_groups] -max_paths 1000 -transition_time -capacitance > report_timing_pt.txt - -echo $env(CHECKTIMING) -if { $env(CHECKTIMING) == "TRUE"} { - return -} - -if { ! [string match *FullChip $Design]} then { -echo "current design is $Design" -set extract_model_clock_transition_limit 0.4 -set extract_model_capacitance_limit 0.4 -set extract_model_data_transition_limit 0.4 -set extract_model_num_capacitance_points 5 -set extract_model_num_clock_transition_points 5 -set extract_model_num_data_transition_points 5 -extract_model -output ./${PP}/result/$Design -format lib -library_cell -} - -exec cp pt.log ${PP}/pt.log -exec cp check_timing_pt.txt ${PP}/check_timing_pt.txt -exec cp report_timing_pt.txt ${PP}/report_timing_pt.txt -if { $env(FLAT) == "TRUE"} { -exec cp ${Design}_FLAT_clock_cross.log ${PP}/${Design}_FLAT_clock_cross.log -} else { -exec cp ${Design}_clock_cross.log ${PP}/${Design}_clock_cross.log -} - -exit diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/rdc_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/rdc_goal.tcl deleted file mode 100644 index 89d60e0..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/rdc_goal.tcl +++ /dev/null @@ -1,59 +0,0 @@ -#--------------------------------------------------------- -# sdc constraint to check cdc settings -#--------------------------------------------------------- -#set_option sdc2sgdc yes -#set_option sdc2sgdcfile ./${top-module-name}.sdc2sgdc.out - -proc cdc_verify_struct_add_settings {} { - -#set_goal_option addrule { Ac_abstract01 } ; ##used for CDC hierarchical flow -#set_goal_option block_abstract yes ; ##used for CDC hierarchical flow -set_goal_option report { CDC-detailed-report SynchInfo } -set_parameter dump_sync_info detailed_mod -set_parameter show_module_in_spreadsheet yes -set_parameter enable_ac_sync_qualdepth yes -set_parameter conv_sync_as_src yes -set_parameter conv_src_seq_depth 0 -set_parameter check_multiclock_bbox yes -set_parameter cdc_qualifier_depth 3 -set_parameter conv_sync_seq_depth 1 -set_parameter handle_combo_arc yes -set_parameter allow_combo_logic yes -set_parameter report_common_reset yes -set_parameter allow_merged_qualifier strict - -set_goal_option addrules { Clock_sync05a Clock_sync06a } -set_goal_option overloadrule { Clock_sync05a+severity=Error } -set_goal_option overloadrule { Clock_sync06a+severity=Error } -set_goal_option overloadrules Reset_sync02+severity=Error - -#set_parameter enable_sync no ; ## disable automatically recognize synchronization scheme -#set_parameter enable_clock_gate_sync no ;## disable automatically recognize synchronization scheme -#set_parameter enable_multiflop_sync no ; ## disbale automatically recognize synchronization scheme -#set_parameter enable_mux_sync none ; ## disable automatically recognize synchronization scheme -#set_parameter enable_and_sync no ; ## disable automatically recognize synchronization scheme -#set_parameter glitch_protect_cell "gp_and,gp_mux" ; ## specify glitch protect cell naem - -#set_parameter synchronize_cells "sync1,sync2" ; ## user defined synchronizer for scalar control signal -#set_parameter reset_synchronize_cells "sync1,sync2" ; ## user defined synchronizer for scalar control signal -#set_parameter synchronize_data_cells "sync1,sync2" ; ## user defined synchronizer for vector control signal -#set_parameter msg_inst_mod_report all ; ## - -#set_parameter report_all_flops yes ; ## report all flops for Reset_sync02 -#set_parameter enable_reset_cone_spreadsheet yes ; ## enable spreadsheet for Reset_sync02 -} - -proc rdc_verify_struct_add_settings {} { -#set_goal_option treat_import_as_ip_block yes -#set_parameter report_flop_reset_info yes -set_parameter report_reset_type all -} - -current_goal rdc/rdc_verify_struct -read_file -type awl waiver/rdc.awl -cdc_verify_struct_add_settings -rdc_verify_struct_add_settings -current_goal none - - - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/sdc_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/sdc_goal.tcl deleted file mode 100644 index 195f057..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/sdc_goal.tcl +++ /dev/null @@ -1,42 +0,0 @@ - -proc sdc_add_settings {} { - -} - -current_goal constraints/sdc_gen -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - - -current_goal constraints/sdc_audit -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - -current_goal constraints/sdc_check -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - -current_goal constraints/sdc_exception_struct -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - - -current_goal constraints/sdc_redundancy -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - -current_goal constraints/sdc_equiv -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - -current_goal constraints/sdc_hier_equiv -read_file -type awl waiver/sdc.awl -sdc_add_settings -current_goal none - diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/spyglass_lint_rules.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/spyglass_lint_rules.tcl deleted file mode 100644 index 3618e20..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/spyglass_lint_rules.tcl +++ /dev/null @@ -1,140 +0,0 @@ -set_goal_option rules { -ArrayIndex -BitOrder-ML -#checkOPPinConnectedToNet_a -CheckTimeUnitandPrecision-ML -CombLoop -DeadCode -DisallowCaseX-ML -DisallowXInCaseZ-ML -HangingInstInput-ML -HangingInst-ML -#HangingInstOutput-ML -FlopClockConstant -FlopEConst -NoExprInPort-ML -SepStateMachine -SetBeforeRead-ML -#sim_race01 -sim_race02 -STARC05-2.2.3.3 -STARC05-2.3.6.1 -STARC05-2.8.1.6 -STARC05-2.10.3.5 -STARC05-2.11.3.1 -STARC05-3.2.3.1 -STARC05-3.2.3.2 -STARC05-2.3.2.2 -STARC-1.4.3.4 -STARC-2.3.6.1 -STARC-2.8.1.4 -STARC-3.2.3.2 -SYNTH_5255 -SYNTH_5192 -UndrivenInTerm-ML -W120 -W122 -W123 -W154 -W18 -W19 -W192 -W193 -W245 -W263 -W287a -W337 -W398 -W414 -W415 -W415a -W422 -W423 -W442a -W480 -W490 -W502 -WRN_27 -} - -set_goal_option overloadrules W398+severity=ERROR -set_goal_option overloadrules W480+severity=ERROR -set_goal_option overloadrules W122+severity=ERROR -set_goal_option overloadrules W123+severity=ERROR -set_goal_option overloadrules FlopClockConstant+severity=ERROR -set_goal_option overloadrules W415+severity=ERROR -set_goal_option overloadrules W415a+severity=WARNING ## -set_goal_option overloadrules STARC-3.2.3.2+severity=ERROR -set_goal_option overloadrules W120+severity=WARNING -set_goal_option overloadrules W154+severity=ERROR -set_goal_option overloadrules W18+severity=ERROR -set_goal_option overloadrules W19+severity=ERROR -set_goal_option overloadrules W192+severity=ERROR -set_goal_option overloadrules W193+severity=ERROR -set_goal_option overloadrules W423+severity=ERROR -set_goal_option overloadrules ArrayIndex+severity=ERROR -set_goal_option overloadrules DisallowCaseX-ML+severity=ERROR -set_goal_option overloadrules STARC-2.3.6.1+severity=ERROR -set_goal_option overloadrules STARC-2.8.1.4+severity=ERROR -set_goal_option overloadrules STARC05-3.2.3.1+severity=ERROR -set_goal_option overloadrules STARC05-2.3.2.2+severity=ERROR -set_goal_option overloadrules UndrivenInTerm-ML+severity=ERROR -set_goal_option overloadrules STARC05-2.2.3.3+severity=ERROR -#set_goal_option overloadrules checkOPPinConnectedToNet_a+severity=WARNING -set_goal_option overloadrules CombLoop+severity=ERROR -set_goal_option overloadrules CheckTimeUnitandPrecision-ML+severity=ERROR -set_goal_option overloadrules DisallowXInCaseZ-ML+severity=ERROR -set_goal_option overloadrules HangingInstInput-ML+severity=ERROR -set_goal_option overloadrules HangingInst-ML+severity=ERROR -#set_goal_option overloadrules HangingInstOutput-ML+severity=WARNING -set_goal_option overloadrules STARC-1.4.3.4+severity=ERROR -set_goal_option overloadrules STARC05-2.11.3.1+severity=ERROR -set_goal_option overloadrules W263+severity=ERROR -set_goal_option overloadrules FlopEConst+severity=ERROR -set_goal_option overloadrules W287a+severity=ERROR -set_goal_option overloadrules BitOrder-ML+severity=ERROR -set_goal_option overloadrules STARC05-2.10.3.5+severity=ERROR -set_goal_option overloadrules SepStateMachine+severity=ERROR -set_goal_option overloadrules SYNTH_5255+severity=ERROR -set_goal_option overloadrules W442a+severity=ERROR -set_goal_option overloadrules W337+severity=ERROR -set_goal_option overloadrules W414+severity=ERROR -set_goal_option overloadrules W422+severity=ERROR -set_goal_option overloadrules SYNTH_5192+severity=ERROR -set_goal_option overloadrules SetBeforeRead-ML+severity=ERROR -set_goal_option overloadrules STARC05-2.3.6.1+severity=ERROR -set_goal_option overloadrules STARC05-3.2.3.2+severity=ERROR -#set_goal_option overloadrules sim_race01+severity=WARNING -set_goal_option overloadrules sim_race02+severity=ERROR -set_goal_option overloadrules WRN_27+severity=ERROR -set_goal_option overloadrules W490+severity=ERROR -set_goal_option overloadrules STARC05-2.8.1.6+severity=ERROR -set_goal_option overloadrules W245+severity=ERROR -set_goal_option overloadrules W502+severity=ERROR -set_goal_option overloadrules W71+severity=WARNING -set_goal_option overloadrules W116+severity=WARNING -set_goal_option overloadrules W362+severity=WARNING -set_goal_option overloadrules UndrivenInTerm-ML+severity=WARNING -set_goal_option overloadrules W164a+severity=WARNING -set_goal_option overloadrules NoExprInPort-ML+severity=WARNING -set_goal_option overloadrules DeadCode+severity=WARNING -set_goal_option overloadrules W240+severity=WARNING -set_goal_option overloadrules STARC-2.6.2.2+severity=WARNING -set_goal_option overloadrules W164b+severity=WARNING -set_goal_option overloadrules SignedUnsignedExpr-ML+severity=WARNING - - -set_parameter assume_driver_load both -set_parameter checkInHierarchy yes -set_parameter checkRTLCInst yes -set_parameter handle_greybox yes -set_parameter instname {/^[a-zA-Z0-9_]+$/} -set_parameter check_static_value yes -set_parameter strict yes -set_parameter report_reset_type all -set_parameter report_underflow_expressions yes -set_parameter report_max_val_overflow yes -set_parameter handle_equivalent_drivers yes -set_parameter checkconstassign yes -set_parameter check_bbox_driver yes -set_parameter ignore_sync_reset yes diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/syn_main.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/syn_main.tcl deleted file mode 100644 index c6dbde1..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/syn_main.tcl +++ /dev/null @@ -1,347 +0,0 @@ -set run_dc true -set run_pt false - -set RTL_DC_ID "" -set RTL_SIM_ID "" - -source -echo "./ProjectPathSetting.tcl" - -#-------------------------------------------------------------- -# NOTE: CHANGE DESIGN NAME TO YOUR OWN -source -echo "./setModuleName.tcl" - -source -echo "./synopsys_dc.setup" - -if { [string match *FullChip $Design]} then { - echo "current design is $Design" - #source -echo "RTL_SIM_ID.tcl" - #source -echo "RTL_DC_ID.tcl" - if { $RTL_DC_ID != $RTL_SIM_ID} then { - echo "RTL_DC_ID != RTL_SIM_ID" - echo "RTL_DC_ID = $RTL_DC_ID" - echo "RTL_SIM_ID = $RTL_SIM_ID" - return - } -} - -#-------------------------------------------------------------- -#Reload ddc -echo $env(LOADDDC) -if { $env(LOADDDC) == "TRUE"} { - read_ddc $env(PP)/report/${Design}.ddc - return -} -#-------------------------------------------------------------- -set dc_date [exec date +%Y_%m%d_%H%M] -exec mkdir dc.work/${Design}_${dc_date} -exec mkdir dc.work/${Design}_${dc_date}/result -exec mkdir dc.work/${Design}_${dc_date}/report - -remove_design -all - -#-------------------------------------------------------------- - -set view_command_win {true} -set_host_options -max_cores 16 - -set compile_enable_async_mux_mapping {true} -set template_naming_style {%s_%p} -set template_parameter_style {%d} -set template_separator_style {_} - -set hdl_keep_licenses {false} -set hdlin_ff_always_async_set_reset {true} -set hdlin_latch_always_async_set_reset {true} -set hdlin_ff_always_sync_set_reset {false} -##set hdlin_use_carry_in true -set hdlin_check_no_latch {true} -set hdlin_mux_size_limit {32} -set hdlin_shorten_long_module_name true -set hdlin_while_loop_iterations 8192 -set hdlin_module_name_limit 128 - -set verilogout_equation {false} -set verilogout_single_bit {false} -set verilogout_higher_designs_first {true} -set verilogout_no_tri {true} -#set verilogout_show_unconnected_pins {false} -set verilogout_show_unconnected_pins {true} - -define_name_rules M2G_MODULE_LEVEL -allowed "A-Z a-z 0-9 _" ; -define_name_rules M2G_MODULE_LEVEL -first_restricted "0-9" ; -define_name_rules M2G_MODULE_LEVEL -replacement_char "_" ; -define_name_rules M2G_MODULE_LEVEL -collapse_name_space ; -define_name_rules M2G_MODULE_LEVEL -case_insensitive ; -define_name_rules M2G_MODULE_LEVEL -remove_internal_net_bus ; -define_name_rules M2G_MODULE_LEVEL -equal_ports_nets ; -define_name_rules M2G_MODULE_LEVEL -add_dummy_nets ; -define_name_rules M2G_MODULE_LEVEL -max_length 128 -type port ; -define_name_rules M2G_MODULE_LEVEL -max_length 64 -type cell ; -define_name_rules M2G_MODULE_LEVEL -max_length 64 -type net ; - -set default_name_rules M2G_MODULE_LEVEL ; - -set bus_dimension_separator_style {_} -set bus_naming_style {%s[%d]} -set bus_range_separator_style {:} -set bus_inference_descending_sort {true} -set bus_inference_style {%s[%d]} -#set write_name_nets_same_as_ports {false} -set write_name_nets_same_as_ports {true} -set bus_minus_style {-%d} -set bus_extraction_style {%s[%d:%d]} - -set change_names_dont_change_bus_members {false} -set uniquify_naming_style %s_%d - -set compile_instance_name_prefix {U} -set compile_instance_name_suffix {} - -set compile_preserve_subdesign_interfaces {true} -set compile_assume_fully_decoded_three_state_busses {false} -set compile_disable_hierarchical_inverter_opt {true} -set enable_recovery_removal_arcs {false} - -set fsm_auto_inferring {true} -set gen_show_created_symbols {true} -set case_analysis_with_logic_constants {true} -set power_cg_auto_identify {true} -set compile_auto_ungroup_count_leaf_cells {true} -set compile_auto_ungroup_override_wlm {true} - -set compile_delete_unloaded_sequential_cells {true} -set compile_seqmap_propagate_constants {true} -set compile_seqmap_propagate_high_effort {true} -set compile_seqmap_propagate_constants_size_only {true} - -set_svf dc.work/${Design}_${dc_date}/report/${Design}.svf - -#-------------------------------------------------------------- -#void warning Info # -#-------------------------------------------------------------- -#suppress_message HDL-193 -#suppress_message LINT-45 -#suppress_message OPT-1056 -#suppress_message PWR-877 -#set suppress_errors {VHDL-2285} - -#-------------------------------------------------------------- -#read↦ link↦ Check design# -#-------------------------------------------------------------- -set DESIGN_RTL_DIR ../cv32e40p-master/rtl - -source -echo "./dc.work/specific_filelist.tcl" -analyze -f SVERILOG -library work -vcs "-f ./nc.work/sim_filelist.f" -redirect -append -file dc.log {elaborate $Design} -current_design $Design -#link -if { [link] == 0} { - echo "Link failed!" - echo $env(CHECKCODE) - if { $env(CHECKCODE) == "TRUE"} { - exit - } - return -} - -#**set timing_enable_multiple_clocks_per_reg true -check_design > dc.work/${Design}_${dc_date}/report/${Design}_check_design.txt - -echo $env(CHECKCODE) -if { $env(CHECKCODE) == "TRUE"} { - echo "Link success!" - exit -} - -#-------------------------------------------------------------- -# set library -# NOTE: ADD YOUR OWN LIBRARY -# ------------------------------------------------------------- -#set_operating_conditions ssg_cworst_max_0p81v_m40c -#set zerowireload Zero -#set auto_wire_load_selection false -#set_wire_load_mode top -##set_wire_load_model -name "$zerowireload" [current_design] -#current_design $Design -source -echo "${PROJECTPATH}/syn/set_library.tcl" - -#------------------------------------------------------------------ -#set_dont_use -source -echo "${PROJECTPATH}/syn/dont_use.tcl" -#------------------------------------------------------------------ - -#remove_license HDL-Compiler - -#change name before compile -report_names -rules verilog -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_1.rpt -redirect -append -file dc.log {change_names -rules verilog -hierarchy -verbose} -report_names -rules M2G_MODULE_LEVEL -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_2.rpt -redirect -append -file dc.log {change_names -rules M2G_MODULE_LEVEL -hierarchy -verbose} - - -#-------------------------------------------------------------- -# read clock set and input output constraints -# NOTE: CHANGE FILE NAME TO YOUR OWN -# --------------------------------------------------------------- -echo $env(DEBUGSDC) -if { $env(DEBUGSDC) == "TRUE"} { - return -} - -redirect -append -file dc.log {source -echo "$env(SDCPATH)/${Design}.sdc"} -source -echo "$env(SDCPATH)/synopsys.sdc" - -#----------------------------------------------------------------- -#set dont_touch design -#----------------------------------------------------------------- -source -echo ./dc.work/syn_specific.tcl - -uniquify -dont_skip_empty_designs - -#---------------------------------------------------------------------------- -#set UPF file -#NOTE: -# -#load_upf MatrixIP_top_u2.upf -#set upf_allow_DD_primary_with_supply_sets true -#set_voltage 0.81 -object_list {VDD VDD1sw VDD2sw} -#set_voltage 0.0 -object_list {VSS} -##insert_mv_cells -isolation -verbose -#check_mv_design -verbose - -#-------------------------------------------------------------- -#check design -report_port -verbose > dc.work/${Design}_${dc_date}/report/${Design}_port.txt -report_clock > dc.work/${Design}_${dc_date}/report/${Design}_clock.txt - - -set_fix_multiple_port_nets -all -buffer_constants -feedthroughs [ get_designs "*" ] - -current_design $Design - -#set_ultra_optimization true - -set_max_dynamic_power 0.0 - -#ungroup -all -flatten - -#set ports_clock_root [filter_collection [get_attribute [get_clocks] sources] object_class==port] -#group_path -name REGOUT -to [all_outputs] -#group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root] -#group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs] - -group_path -name in2reg -from [all_inputs] -critical_range 1000.0 -group_path -name reg2out -to [all_outputs] -critical_range 1000.0 -group_path -name in2out -from [all_inputs] -to [all_outputs] -critical_range 1000.0 -group_path -name reg2reg -from [all_registers] -to [all_registers] -critical_range 1000.0 - -#set_compile_directives -constant_propagation true [get_cells -hierarchical *] - -set_cost_priority -delay -set_critical_range 0.2 $Design -redirect -append -file dc.log {remove_unconnected_ports [get_cells -hier * ] } - -check_design > dc.work/${Design}_${dc_date}/report/${Design}_check_design_aftercom.txt -analyze_datapath_extraction > dc.work/${Design}_${dc_date}/report/${Design}_analyze_datapath_extraction.rpt - -compile_ultra -no_autoungroup -timing_high_effort -gate_clock -no_seq_output_inversion -scan -#compile_ultra -no_autoungroup -timing_high_effort -gate_clock -no_seq_output_inversion - -#foreach_in_collection desig [remove_from_collection [get_designs "*"] [get_designs {FADDSUB_top}]] { -# lappend rename_design_list $desig -#} - -#rename_design $rename_design_list -prefix FADDSUB_ -rename_design [remove_from_collection [get_designs "*"] $Design] -prefix ${Design}_ - - -#-------------------------------------------------------------- -#write_report - -if { [llength [get_cells main_gate -hier -filter "clock_gating_logic == true"]] != 0 } { - remove_clock_gating_check [get_cells main_gate -hier -filter "clock_gating_logic == true"] -} - - -report_names -rules verilog -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_3.rpt -redirect -append -file dc.log {change_names -rules verilog -hierarchy -verbose} -report_names -rules M2G_MODULE_LEVEL -hierarchy > dc.work/${Design}_${dc_date}/report/rename_info_4.rpt -redirect -append -file dc.log {change_names -rules M2G_MODULE_LEVEL -hierarchy -verbose} - -#write_report -write -format verilog -hierarchy $Design -output dc.work/${Design}_${dc_date}/result/${Design}.sv -write -format ddc -hierarchy -output dc.work/${Design}_${dc_date}/report/${Design}.ddc -report_timing -max 1000 -transition_time -capacitance > dc.work/${Design}_${dc_date}/report/${Design}_timing.txt -report_constraint -all_violators > dc.work/${Design}_${dc_date}/report/${Design}_constraint.txt -write_script > dc.work/${Design}_${dc_date}/report/${Design}.sdc -write_sdc -nosplit dc.work/${Design}_${dc_date}/report/${Design}.sdc -report_design > dc.work/${Design}_${dc_date}/report/${Design}_design.txt -report_reference -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_reference.rpt -report_net > dc.work/${Design}_${dc_date}/report/${Design}_net.rpt -report_names -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_names.rpt -report_resources -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_resource.rpt -report_multibit -hier > dc.work/${Design}_${dc_date}/report/${Design}_multibit.rpt -report_power > dc.work/${Design}_${dc_date}/report/${Design}_power.txt -report_qor > dc.work/${Design}_${dc_date}/report/${Design}_qor.txt -report_clock_tree_power > dc.work/${Design}_${dc_date}/report/${Design}_clkpower.txt -report_clock_gating > dc.work/${Design}_${dc_date}/report/${Design}_clock_gating.txt -report_area -nosplit -hierarchy > dc.work/${Design}_${dc_date}/report/${Design}_area.txt -report_timing -max 100 -transition_time -capacitance -group in2reg > dc.work/${Design}_${dc_date}/report/${Design}_in2reg -report_timing -max 100 -transition_time -capacitance -group reg2out > dc.work/${Design}_${dc_date}/report/${Design}_reg2out -report_timing -max 100 -transition_time -capacitance -group in2out > dc.work/${Design}_${dc_date}/report/${Design}_in2out -report_timing -max 100 -transition_time -capacitance -group reg2reg > dc.work/${Design}_${dc_date}/report/${Design}_reg2reg -check_timing -include {gated_clock clock_crossing} > dc.work/${Design}_${dc_date}/report/${Design}_check_timing.rpt -#report_timing \ -# -path full_clock \ -# -transition_time \ -# -crosstalk_delta \ -# -capacitance \ -# -input_pins \ -# -nets \ -# -delay max \ -# -derate \ -# -max_paths 100 > ${dc_date}/timing/${DESIGN}_${dc_date}_timing_dc.txt -# - -set_svf -off - -check_mv_design -verbose > dc.work/${Design}_${dc_date}/report/${Design}_check_upf.log - -#remove_design -hierarchy MatrixIP_Core_Scalar_PG -#remove_design -hierarchy MatrixIP_Core_Vector_PG - -#write -format verilog -hierarchy $Design -output dc.work/${Design}_${dc_date}/result/${Design}_hier.sv -#exec rm ../Netlist_9T_125C/${Design}.v -#exec cp dc.work/${Design}_${dc_date}/result/${Design}.sv ../Netlist_9T_125C/${Design}.v -#-------------------------------------------------------------- -#quit - -set dc_date0 [exec date +%Y_%m%d_%H%M] -echo ${dc_date} ${dc_date0} - -exec $env(SCRIPTPATH)/get_DBs_info.sh -exec $env(SCRIPTPATH)/report_dc_summary.sh -exec cp dc.work/${Design}_${dc_date}/report/${Design}_check_design.txt dc.work/${Design}_${dc_date}/check_design.txt -exec cp dc.work/${Design}_${dc_date}/report/${Design}_check_timing.rpt dc.work/${Design}_${dc_date}/check_timing.txt -exec cp dc.log dc.work/${Design}_${dc_date}/dc.log -exec cp command.log dc.work/${Design}_${dc_date}/command.log -exec cp RTL_DC_info.log dc.work/${Design}_${dc_date}/RTL_DC_info.log -exec cp RTL_DC_ID.tcl dc.work/${Design}_${dc_date}/RTL_DC_ID.tcl -exec cp update_RTL_SVN.sh dc.work/${Design}_${dc_date}/update_RTL_SVN.sh - -#remove_sdc -#source -echo "${PROJECTPATH}/syn/SDC/${Design}.sdc" - -source -echo "./dc.work/syn_specific_after.tcl" - -if { [file exists dc.work/${Design}_${dc_date}/result/${Design}.sv] == 1} { -exec mkdir NetlistSubmit/${Design}_${dc_date} -exec cp dc.work/${Design}_${dc_date}/result/${Design}.sv NetlistSubmit/${Design}_${dc_date}/ -exec cp dc.work/${Design}_${dc_date}/report/${Design}_qor.txt NetlistSubmit/${Design}_${dc_date}/ -#exec cp dc.work/${Design}_${dc_date}/report/${Design}_memory_clock.rpt NetlistSubmit/${Design}_${dc_date}/ -} - -echo $env(FLOW) -if { $env(FLOW) == "TRUE"} { - exit -} diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/synth_options.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/synth_options.tcl deleted file mode 100644 index bf11fa2..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/synth_options.tcl +++ /dev/null @@ -1,12 +0,0 @@ -# File added as part of PowerKit_M2017.03-SP1_v1 - -# Synthesis command to enable multi process synthesis -syn_set_global_option enable_multi_process 2 -# Synthesis command to control maximum number of parallel synth process -syn_set_global_option max_core_count_for_multi_process 4 - -# To enable new ABC engine -# Disabled by default i.e old ABC engine is used -# Enable only under product team guidance. -# Usefull in case of Syntheis crash or Higher synth Area with old ABC -##syn_set_global_option select_new_ABC 1 diff --git a/src/UWE_projectCode/tmp/tmp/Tcls/txv_goal.tcl b/src/UWE_projectCode/tmp/tmp/Tcls/txv_goal.tcl deleted file mode 100644 index fe53347..0000000 --- a/src/UWE_projectCode/tmp/tmp/Tcls/txv_goal.tcl +++ /dev/null @@ -1,34 +0,0 @@ -proc txv_fp_add_settings {} { -set_parameter tc_domain_mode STA -set_parameter pt no -} - - -proc txv_mcp_add_settings {} { -set_parameter tc_domain_mode STA -set_parameter pt no -set_goal_option addrules {Txv_Gen_Assert} -set_goal_option ignorerules {Txv_MCP01} -} - -current_goal txv_verification/fp_verification -read_file -type awl waiver/txv.awl -txv_fp_add_settings -current_goal none - -current_goal txv_verification/mcp_verification -read_file -type awl waiver/txv.awl -txv_mcp_add_settings -current_goal none - -current_goal txv_verification/mcp_verification -scenario TBA -read_file -type awl waiver/txv.awl -txv_mcp_add_settings -set_parameter txv_mcp_time_based_sva_gen yes -current_goal none - -current_goal txv_verification/fp_mcp_verification -read_file -type awl waiver/txv.awl -txv_mcp_add_settings -txv_fp_add_settings -current_goal none diff --git a/src/UWE_projectCode/tmp/tmp/Template/command.log b/src/UWE_projectCode/tmp/tmp/Template/command.log deleted file mode 100644 index 5a5892d..0000000 --- a/src/UWE_projectCode/tmp/tmp/Template/command.log +++ /dev/null @@ -1,6627 +0,0 @@ -#@ # -#@ # Running dc_shell Version O-2018.06-SP1 for linux64 -- Jul 19, 2018 -#@ # Date: Tue Feb 28 19:57:38 2023 -#@ # Run by: UWE@Frontend -#@ - -source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.synopsys_dc.setup -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.synopsys_dc.setup - -#@ # -#@ # ".synopsys_dc.setup" Initialization File for -#@ # -#@ # Dc_Shell and Design_Analyzer -#@ # -#@ # The variables in this file define the behavior of many parts -#@ # of the Synopsys Synthesis Tools. Upon installation, they should -#@ # be reviewed and modified to fit your site's needs. Each engineer -#@ # can have a .synopsys file in his/her home directory or current -#@ # directory to override variable settings in this file. -#@ # -#@ # Each logical grouping of variables is commented as to their -#@ # nature and effect on the Synthesis Commands. Examples of -#@ # variable groups are the Compile Variable Group, which affects -#@ # the designs produced by the COMPILE command, and the Schematic -#@ # Variable Group, which affects the output of the create_schematic -#@ # command. -#@ # -#@ # You can type "man _variables" in dc_shell or -#@ # design_analyzer to get help about a group of variables. -#@ # For instance, to get help about the "system" variable group, -#@ # type "help system_variables". You can also type -#@ # "man ", to get help on the that variable's -#@ # group. -#@ # -#@ -#@ # System variables -#@ set sh_command_abbrev_mode "Anywhere" -#@ set sh_continue_on_error "true" -#@ update_app_var -default true sh_continue_on_error -#@ set sh_enable_page_mode "true" -#@ update_app_var -default true sh_enable_page_mode -#@ set sh_source_uses_search_path "true" -#@ update_app_var -default true sh_source_uses_search_path -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "dc_sms_shell" } { -#@ set sh_new_variable_message "false" -#@ update_app_var -default false sh_new_variable_message -#@ } else { -#@ set sh_new_variable_message "true" -#@ update_app_var -default true sh_new_variable_message -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell"} { -#@ set html_log_enable "false" -#@ set html_log_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "de_shell"} { -#@ set de_log_html_filename "default.html" -#@ } -#@ -#@ if {$synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell"} { -#@ lappend auto_path [file join ${synopsys_root} auxx syn lib] -#@ package require cae -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tm.tcl - -#@ # -*- tcl -*- -#@ # -#@ # Searching for Tcl Modules. Defines a procedure, declares it as the primary -#@ # command for finding packages, however also uses the former 'package unknown' -#@ # command as a fallback. -#@ # -#@ # Locates all possible packages in a directory via a less restricted glob. The -#@ # targeted directory is derived from the name of the requested package, i.e. -#@ # the TM scan will look only at directories which can contain the requested -#@ # package. It will register all packages it found in the directory so that -#@ # future requests have a higher chance of being fulfilled by the ifneeded -#@ # database without having to come to us again. -#@ # -#@ # We do not remember where we have been and simply rescan targeted directories -#@ # when invoked again. The reasoning is this: -#@ # -#@ # - The only way we get back to the same directory is if someone is trying to -#@ # [package require] something that wasn't there on the first scan. -#@ # -#@ # Either -#@ # 1) It is there now: If we rescan, you get it; if not you don't. -#@ # -#@ # This covers the possibility that the application asked for a package -#@ # late, and the package was actually added to the installation after the -#@ # application was started. It shoukld still be able to find it. -#@ # -#@ # 2) It still is not there: Either way, you don't get it, but the rescan -#@ # takes time. This is however an error case and we dont't care that much -#@ # about it -#@ # -#@ # 3) It was there the first time; but for some reason a "package forget" has -#@ # been run, and "package" doesn't know about it anymore. -#@ # -#@ # This can be an indication that the application wishes to reload some -#@ # functionality. And should work as well. -#@ # -#@ # Note that this also strikes a balance between doing a glob targeting a -#@ # single package, and thus most likely requiring multiple globs of the same -#@ # directory when the application is asking for many packages, and trying to -#@ # glob for _everything_ in all subdirectories when looking for a package, -#@ # which comes with a heavy startup cost. -#@ # -#@ # We scan for regular packages only if no satisfying module was found. -#@ -#@ namespace eval ::tcl::tm { -#@ # Default paths. None yet. -#@ -#@ variable paths {} -#@ -#@ # The regex pattern a file name has to match to make it a Tcl Module. -#@ -#@ set pkgpattern {^([_[:alpha:]][:_[:alnum:]]*)-([[:digit:]].*)[.]tm$} -#@ -#@ # Export the public API -#@ -#@ namespace export path -#@ namespace ensemble create -command path -subcommands {add remove list} -#@ } -#@ -#@ # ::tcl::tm::path implementations -- -#@ # -#@ # Public API to the module path. See specification. -#@ # -#@ # Arguments -#@ # cmd - The subcommand to execute -#@ # args - The paths to add/remove. Must not appear querying the -#@ # path with 'list'. -#@ # -#@ # Results -#@ # No result for subcommands 'add' and 'remove'. A list of paths for -#@ # 'list'. -#@ # -#@ # Sideeffects -#@ # The subcommands 'add' and 'remove' manipulate the list of paths to -#@ # search for Tcl Modules. The subcommand 'list' has no sideeffects. -#@ -#@ proc ::tcl::tm::add {args} { -#@ # PART OF THE ::tcl::tm::path ENSEMBLE -#@ # -#@ # The path is added at the head to the list of module paths. -#@ # -#@ # The command enforces the restriction that no path may be an ancestor -#@ # directory of any other path on the list. If the new path violates this -#@ # restriction an error wil be raised. -#@ # -#@ # If the path is already present as is no error will be raised and no -#@ # action will be taken. -#@ -#@ variable paths -#@ -#@ # We use a copy of the path as source during validation, and extend it as -#@ # well. Because we not only have to detect if the new paths are bogus with -#@ # respect to the existing paths, but also between themselves. Otherwise we -#@ # can still add bogus paths, by specifying them in a single call. This -#@ # makes the use of the new paths simpler as well, a trivial assignment of -#@ # the collected paths to the official state var. -#@ -#@ set newpaths $paths -#@ foreach p $args { -#@ if {$p in $newpaths} { -#@ # Ignore a path already on the list. -#@ continue -#@ } -#@ -#@ # Search for paths which are subdirectories of the new one. If there -#@ # are any then the new path violates the restriction about ancestors. -#@ -#@ set pos [lsearch -glob $newpaths ${p}/*] -#@ # Cannot use "in", we need the position for the message. -#@ if {$pos >= 0} { -#@ return -code error "$p is ancestor of existing module path [lindex $newpaths $pos]." -#@ } -#@ -#@ # Now look for existing paths which are ancestors of the new one. This -#@ # reverse question forces us to loop over the existing paths, as each -#@ # element is the pattern, not the new path :( -#@ -#@ foreach ep $newpaths { -#@ if {[string match ${ep}/* $p]} { -#@ return -code error "$p is subdirectory of existing module path $ep." -#@ } -#@ } -#@ -#@ set newpaths [linsert $newpaths 0 $p] -#@ } -#@ -#@ # The validation of the input is complete and successful, and everything -#@ # in newpaths is either an old path, or added. We can now extend the -#@ # official list of paths, a simple assignment is sufficient. -#@ -#@ set paths $newpaths -#@ return -#@ } -#@ -#@ proc ::tcl::tm::remove {args} { -#@ # PART OF THE ::tcl::tm::path ENSEMBLE -#@ # -#@ # Removes the path from the list of module paths. The command is silently -#@ # ignored if the path is not on the list. -#@ -#@ variable paths -#@ -#@ foreach p $args { -#@ set pos [lsearch -exact $paths $p] -#@ if {$pos >= 0} { -#@ set paths [lreplace $paths $pos $pos] -#@ } -#@ } -#@ } -#@ -#@ proc ::tcl::tm::list {} { -#@ # PART OF THE ::tcl::tm::path ENSEMBLE -#@ -#@ variable paths -#@ return $paths -#@ } -#@ -#@ # ::tcl::tm::UnknownHandler -- -#@ # -#@ # Unknown handler for Tcl Modules, i.e. packages in module form. -#@ # -#@ # Arguments -#@ # original - Original [package unknown] procedure. -#@ # name - Name of desired package. -#@ # version - Version of desired package. Can be the -#@ # empty string. -#@ # exact - Either -exact or ommitted. -#@ # -#@ # Name, version, and exact are used to determine satisfaction. The -#@ # original is called iff no satisfaction was achieved. The name is also -#@ # used to compute the directory to target in the search. -#@ # -#@ # Results -#@ # None. -#@ # -#@ # Sideeffects -#@ # May populate the package ifneeded database with additional provide -#@ # scripts. -#@ -#@ proc ::tcl::tm::UnknownHandler {original name args} { -#@ # Import the list of paths to search for packages in module form. -#@ # Import the pattern used to check package names in detail. -#@ -#@ variable paths -#@ variable pkgpattern -#@ -#@ # Without paths to search we can do nothing. (Except falling back to the -#@ # regular search). -#@ -#@ if {[llength $paths]} { -#@ set pkgpath [string map {:: /} $name] -#@ set pkgroot [file dirname $pkgpath] -#@ if {$pkgroot eq "."} { -#@ set pkgroot "" -#@ } -#@ -#@ # We don't remember a copy of the paths while looping. Tcl Modules are -#@ # unable to change the list while we are searching for them. This also -#@ # simplifies the loop, as we cannot get additional directories while -#@ # iterating over the list. A simple foreach is sufficient. -#@ -#@ set satisfied 0 -#@ foreach path $paths { -#@ if {![interp issafe] && ![file exists $path]} { -#@ continue -#@ } -#@ set currentsearchpath [file join $path $pkgroot] -#@ if {![interp issafe] && ![file exists $currentsearchpath]} { -#@ continue -#@ } -#@ set strip [llength [file split $path]] -#@ -#@ # We can't use glob in safe interps, so enclose the following in a -#@ # catch statement, where we get the module files out of the -#@ # subdirectories. In other words, Tcl Modules are not-functional -#@ # in such an interpreter. This is the same as for the command -#@ # "tclPkgUnknown", i.e. the search for regular packages. -#@ -#@ catch { -#@ # We always look for _all_ possible modules in the current -#@ # path, to get the max result out of the glob. -#@ -#@ foreach file [glob -nocomplain -directory $currentsearchpath *.tm] { -#@ set pkgfilename [join [lrange [file split $file] $strip end] ::] -#@ -#@ if {![regexp -- $pkgpattern $pkgfilename --> pkgname pkgversion]} { -#@ # Ignore everything not matching our pattern for -#@ # package names. -#@ continue -#@ } -#@ try { -#@ package vcompare $pkgversion 0 -#@ } on error {} { -#@ # Ignore everything where the version part is not -#@ # acceptable to "package vcompare". -#@ continue -#@ } -#@ -#@ if {[package ifneeded $pkgname $pkgversion] ne {}} { -#@ # There's already a provide script registered for -#@ # this version of this package. Since all units of -#@ # code claiming to be the same version of the same -#@ # package ought to be identical, just stick with -#@ # the one we already have. -#@ continue -#@ } -#@ -#@ # We have found a candidate, generate a "provide script" -#@ # for it, and remember it. Note that we are using ::list -#@ # to do this; locally [list] means something else without -#@ # the namespace specifier. -#@ -#@ # NOTE. When making changes to the format of the provide -#@ # command generated below CHECK that the 'LOCATE' -#@ # procedure in core file 'platform/shell.tcl' still -#@ # understands it, or, if not, update its implementation -#@ # appropriately. -#@ # -#@ # Right now LOCATE's implementation assumes that the path -#@ # of the package file is the last element in the list. -#@ -#@ package ifneeded $pkgname $pkgversion "[::list package provide $pkgname $pkgversion];[::list source -encoding utf-8 $file]" -#@ -#@ # We abort in this unknown handler only if we got a -#@ # satisfying candidate for the requested package. -#@ # Otherwise we still have to fallback to the regular -#@ # package search to complete the processing. -#@ -#@ if {($pkgname eq $name) -#@ && [package vsatisfies $pkgversion {*}$args]} { -#@ set satisfied 1 -#@ -#@ # We do not abort the loop, and keep adding provide -#@ # scripts for every candidate in the directory, just -#@ # remember to not fall back to the regular search -#@ # anymore. -#@ } -#@ } -#@ } -#@ } -#@ -#@ if {$satisfied} { -#@ return -#@ } -#@ } -#@ -#@ # Fallback to previous command, if existing. See comment above about -#@ # ::list... -#@ -#@ if {[llength $original]} { -#@ uplevel 1 $original [::linsert $args 0 $name] -#@ } -#@ } -#@ -#@ # ::tcl::tm::Defaults -- -#@ # -#@ # Determines the default search paths. -#@ # -#@ # Arguments -#@ # None -#@ # -#@ # Results -#@ # None. -#@ # -#@ # Sideeffects -#@ # May add paths to the list of defaults. -#@ -#@ proc ::tcl::tm::Defaults {} { -#@ global env tcl_platform -#@ -#@ lassign [split [info tclversion] .] major minor -#@ set exe [file normalize [info nameofexecutable]] -#@ -#@ # Note that we're using [::list], not [list] because [list] means -#@ # something other than [::list] in this namespace. -#@ roots [::list [file dirname [info library]] [file join [file dirname [file dirname $exe]] lib] ] -#@ -#@ if {$tcl_platform(platform) eq "windows"} { -#@ set sep ";" -#@ } else { -#@ set sep ":" -#@ } -#@ for {set n $minor} {$n >= 0} {incr n -1} { -#@ foreach ev [::list TCL${major}.${n}_TM_PATH TCL${major}_${n}_TM_PATH ] { -#@ if {![info exists env($ev)]} continue -#@ foreach p [split $env($ev) $sep] { -#@ path add $p -#@ } -#@ } -#@ } -#@ return -#@ } -#@ -#@ # ::tcl::tm::roots -- -#@ # -#@ # Public API to the module path. See specification. -#@ # -#@ # Arguments -#@ # paths - List of 'root' paths to derive search paths from. -#@ # -#@ # Results -#@ # No result. -#@ # -#@ # Sideeffects -#@ # Calls 'path add' to paths to the list of module search paths. -#@ -#@ proc ::tcl::tm::roots {paths} { -#@ lassign [split [package present Tcl] .] major minor -#@ foreach pa $paths { -#@ set p [file join $pa tcl$major] -#@ for {set n $minor} {$n >= 0} {incr n -1} { -#@ set px [file join $p ${major}.${n}] -#@ if {![interp issafe]} {set px [file normalize $px]} -#@ path add $px -#@ } -#@ set px [file join $p site-tcl] -#@ if {![interp issafe]} {set px [file normalize $px]} -#@ path add $px -#@ } -#@ return -#@ } -#@ -#@ # Initialization. Set up the default paths, then insert the new handler into -#@ # the chain. -#@ -#@ if {![interp issafe]} {::tcl::tm::Defaults} -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tm.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/package.tcl - -#@ # package.tcl -- -#@ # -#@ # utility procs formerly in init.tcl which can be loaded on demand -#@ # for package management. -#@ # -#@ # Copyright (c) 1991-1993 The Regents of the University of California. -#@ # Copyright (c) 1994-1998 Sun Microsystems, Inc. -#@ # -#@ # See the file "license.terms" for information on usage and redistribution -#@ # of this file, and for a DISCLAIMER OF ALL WARRANTIES. -#@ # -#@ -#@ namespace eval tcl::Pkg {} -#@ -#@ # ::tcl::Pkg::CompareExtension -- -#@ # -#@ # Used internally by pkg_mkIndex to compare the extension of a file to a given -#@ # extension. On Windows, it uses a case-insensitive comparison because the -#@ # file system can be file insensitive. -#@ # -#@ # Arguments: -#@ # fileName name of a file whose extension is compared -#@ # ext (optional) The extension to compare against; you must -#@ # provide the starting dot. -#@ # Defaults to [info sharedlibextension] -#@ # -#@ # Results: -#@ # Returns 1 if the extension matches, 0 otherwise -#@ -#@ proc tcl::Pkg::CompareExtension {fileName {ext {}}} { -#@ global tcl_platform -#@ if {$ext eq ""} {set ext [info sharedlibextension]} -#@ if {$tcl_platform(platform) eq "windows"} { -#@ return [string equal -nocase [file extension $fileName] $ext] -#@ } else { -#@ # Some unices add trailing numbers after the .so, so -#@ # we could have something like '.so.1.2'. -#@ set root $fileName -#@ while {1} { -#@ set currExt [file extension $root] -#@ if {$currExt eq $ext} { -#@ return 1 -#@ } -#@ -#@ # The current extension does not match; if it is not a numeric -#@ # value, quit, as we are only looking to ignore version number -#@ # extensions. Otherwise we might return 1 in this case: -#@ # tcl::Pkg::CompareExtension foo.so.bar .so -#@ # which should not match. -#@ -#@ if {![string is integer -strict [string range $currExt 1 end]]} { -#@ return 0 -#@ } -#@ set root [file rootname $root] -#@ } -#@ } -#@ } -#@ -#@ # pkg_mkIndex -- -#@ # This procedure creates a package index in a given directory. The package -#@ # index consists of a "pkgIndex.tcl" file whose contents are a Tcl script that -#@ # sets up package information with "package require" commands. The commands -#@ # describe all of the packages defined by the files given as arguments. -#@ # -#@ # Arguments: -#@ # -direct (optional) If this flag is present, the generated -#@ # code in pkgMkIndex.tcl will cause the package to be -#@ # loaded when "package require" is executed, rather -#@ # than lazily when the first reference to an exported -#@ # procedure in the package is made. -#@ # -verbose (optional) Verbose output; the name of each file that -#@ # was successfully rocessed is printed out. Additionally, -#@ # if processing of a file failed a message is printed. -#@ # -load pat (optional) Preload any packages whose names match -#@ # the pattern. Used to handle DLLs that depend on -#@ # other packages during their Init procedure. -#@ # dir - Name of the directory in which to create the index. -#@ # args - Any number of additional arguments, each giving -#@ # a glob pattern that matches the names of one or -#@ # more shared libraries or Tcl script files in -#@ # dir. -#@ -#@ proc pkg_mkIndex {args} { -#@ set usage {"pkg_mkIndex ?-direct? ?-lazy? ?-load pattern? ?-verbose? ?--? dir ?pattern ...?"} -#@ -#@ set argCount [llength $args] -#@ if {$argCount < 1} { -#@ return -code error "wrong # args: should be\n$usage" -#@ } -#@ -#@ set more "" -#@ set direct 1 -#@ set doVerbose 0 -#@ set loadPat "" -#@ for {set idx 0} {$idx < $argCount} {incr idx} { -#@ set flag [lindex $args $idx] -#@ switch -glob -- $flag { -#@ -- { -#@ # done with the flags -#@ incr idx -#@ break -#@ } -#@ -verbose { -#@ set doVerbose 1 -#@ } -#@ -lazy { -#@ set direct 0 -#@ append more " -lazy" -#@ } -#@ -direct { -#@ append more " -direct" -#@ } -#@ -load { -#@ incr idx -#@ set loadPat [lindex $args $idx] -#@ append more " -load $loadPat" -#@ } -#@ -* { -#@ return -code error "unknown flag $flag: should be\n$usage" -#@ } -#@ default { -#@ # done with the flags -#@ break -#@ } -#@ } -#@ } -#@ -#@ set dir [lindex $args $idx] -#@ set patternList [lrange $args [expr {$idx + 1}] end] -#@ if {![llength $patternList]} { -#@ set patternList [list "*.tcl" "*[info sharedlibextension]"] -#@ } -#@ -#@ try { -#@ set fileList [glob -directory $dir -tails -types {r f} -- {*}$patternList] -#@ } on error {msg opt} { -#@ return -options $opt $msg -#@ } -#@ foreach file $fileList { -#@ # For each file, figure out what commands and packages it provides. -#@ # To do this, create a child interpreter, load the file into the -#@ # interpreter, and get a list of the new commands and packages that -#@ # are defined. -#@ -#@ if {$file eq "pkgIndex.tcl"} { -#@ continue -#@ } -#@ -#@ set c [interp create] -#@ -#@ # Load into the child any packages currently loaded in the parent -#@ # interpreter that match the -load pattern. -#@ -#@ if {$loadPat ne ""} { -#@ if {$doVerbose} { -#@ tclLog "currently loaded packages: '[info loaded]'" -#@ tclLog "trying to load all packages matching $loadPat" -#@ } -#@ if {![llength [info loaded]]} { -#@ tclLog "warning: no packages are currently loaded, nothing" -#@ tclLog "can possibly match '$loadPat'" -#@ } -#@ } -#@ foreach pkg [info loaded] { -#@ if {![string match -nocase $loadPat [lindex $pkg 1]]} { -#@ continue -#@ } -#@ if {$doVerbose} { -#@ tclLog "package [lindex $pkg 1] matches '$loadPat'" -#@ } -#@ try { -#@ load [lindex $pkg 0] [lindex $pkg 1] $c -#@ } on error err { -#@ if {$doVerbose} { -#@ tclLog "warning: load [lindex $pkg 0] [lindex $pkg 1]\nfailed with: $err" -#@ } -#@ } on ok {} { -#@ if {$doVerbose} { -#@ tclLog "loaded [lindex $pkg 0] [lindex $pkg 1]" -#@ } -#@ } -#@ if {[lindex $pkg 1] eq "Tk"} { -#@ # Withdraw . if Tk was loaded, to avoid showing a window. -#@ $c eval [list wm withdraw .] -#@ } -#@ } -#@ -#@ $c eval { -#@ # Stub out the package command so packages can require other -#@ # packages. -#@ -#@ rename package __package_orig -#@ proc package {what args} { -#@ switch -- $what { -#@ require { -#@ return; # Ignore transitive requires -#@ } -#@ default { -#@ __package_orig $what {*}$args -#@ } -#@ } -#@ } -#@ proc tclPkgUnknown args {} -#@ package unknown tclPkgUnknown -#@ -#@ # Stub out the unknown command so package can call into each other -#@ # during their initialilzation. -#@ -#@ proc unknown {args} {} -#@ -#@ # Stub out the auto_import mechanism -#@ -#@ proc auto_import {args} {} -#@ -#@ # reserve the ::tcl namespace for support procs and temporary -#@ # variables. This might make it awkward to generate a -#@ # pkgIndex.tcl file for the ::tcl namespace. -#@ -#@ namespace eval ::tcl { -#@ variable dir ;# Current directory being processed -#@ variable file ;# Current file being processed -#@ variable direct ;# -direct flag value -#@ variable x ;# Loop variable -#@ variable debug ;# For debugging -#@ variable type ;# "load" or "source", for -direct -#@ variable namespaces ;# Existing namespaces (e.g., ::tcl) -#@ variable packages ;# Existing packages (e.g., Tcl) -#@ variable origCmds ;# Existing commands -#@ variable newCmds ;# Newly created commands -#@ variable newPkgs {} ;# Newly created packages -#@ } -#@ } -#@ -#@ $c eval [list set ::tcl::dir $dir] -#@ $c eval [list set ::tcl::file $file] -#@ $c eval [list set ::tcl::direct $direct] -#@ -#@ # Download needed procedures into the slave because we've just deleted -#@ # the unknown procedure. This doesn't handle procedures with default -#@ # arguments. -#@ -#@ foreach p {::tcl::Pkg::CompareExtension} { -#@ $c eval [list namespace eval [namespace qualifiers $p] {}] -#@ $c eval [list proc $p [info args $p] [info body $p]] -#@ } -#@ -#@ try { -#@ $c eval { -#@ set ::tcl::debug "loading or sourcing" -#@ -#@ # we need to track command defined by each package even in the -#@ # -direct case, because they are needed internally by the -#@ # "partial pkgIndex.tcl" step above. -#@ -#@ proc ::tcl::GetAllNamespaces {{root ::}} { -#@ set list $root -#@ foreach ns [namespace children $root] { -#@ lappend list {*}[::tcl::GetAllNamespaces $ns] -#@ } -#@ return $list -#@ } -#@ -#@ # init the list of existing namespaces, packages, commands -#@ -#@ foreach ::tcl::x [::tcl::GetAllNamespaces] { -#@ set ::tcl::namespaces($::tcl::x) 1 -#@ } -#@ foreach ::tcl::x [package names] { -#@ if {[package provide $::tcl::x] ne ""} { -#@ set ::tcl::packages($::tcl::x) 1 -#@ } -#@ } -#@ set ::tcl::origCmds [info commands] -#@ -#@ # Try to load the file if it has the shared library extension, -#@ # otherwise source it. It's important not to try to load -#@ # files that aren't shared libraries, because on some systems -#@ # (like SunOS) the loader will abort the whole application -#@ # when it gets an error. -#@ -#@ if {[::tcl::Pkg::CompareExtension $::tcl::file [info sharedlibextension]]} { -#@ # The "file join ." command below is necessary. Without -#@ # it, if the file name has no \'s and we're on UNIX, the -#@ # load command will invoke the LD_LIBRARY_PATH search -#@ # mechanism, which could cause the wrong file to be used. -#@ -#@ set ::tcl::debug loading -#@ load [file join $::tcl::dir $::tcl::file] -#@ set ::tcl::type load -#@ } else { -#@ set ::tcl::debug sourcing -#@ source [file join $::tcl::dir $::tcl::file] -#@ set ::tcl::type source -#@ } -#@ -#@ # As a performance optimization, if we are creating direct -#@ # load packages, don't bother figuring out the set of commands -#@ # created by the new packages. We only need that list for -#@ # setting up the autoloading used in the non-direct case. -#@ if {!$::tcl::direct} { -#@ # See what new namespaces appeared, and import commands -#@ # from them. Only exported commands go into the index. -#@ -#@ foreach ::tcl::x [::tcl::GetAllNamespaces] { -#@ if {![info exists ::tcl::namespaces($::tcl::x)]} { -#@ namespace import -force ${::tcl::x}::* -#@ } -#@ -#@ # Figure out what commands appeared -#@ -#@ foreach ::tcl::x [info commands] { -#@ set ::tcl::newCmds($::tcl::x) 1 -#@ } -#@ foreach ::tcl::x $::tcl::origCmds { -#@ unset -nocomplain ::tcl::newCmds($::tcl::x) -#@ } -#@ foreach ::tcl::x [array names ::tcl::newCmds] { -#@ # determine which namespace a command comes from -#@ -#@ set ::tcl::abs [namespace origin $::tcl::x] -#@ -#@ # special case so that global names have no -#@ # leading ::, this is required by the unknown -#@ # command -#@ -#@ set ::tcl::abs [lindex [auto_qualify $::tcl::abs ::] 0] -#@ -#@ if {$::tcl::x ne $::tcl::abs} { -#@ # Name changed during qualification -#@ -#@ set ::tcl::newCmds($::tcl::abs) 1 -#@ unset ::tcl::newCmds($::tcl::x) -#@ } -#@ } -#@ } -#@ } -#@ -#@ # Look through the packages that appeared, and if there is a -#@ # version provided, then record it -#@ -#@ foreach ::tcl::x [package names] { -#@ if {[package provide $::tcl::x] ne "" -#@ && ![info exists ::tcl::packages($::tcl::x)]} { -#@ lappend ::tcl::newPkgs [list $::tcl::x [package provide $::tcl::x]] -#@ } -#@ } -#@ } -#@ } on error msg { -#@ set what [$c eval set ::tcl::debug] -#@ if {$doVerbose} { -#@ tclLog "warning: error while $what $file: $msg" -#@ } -#@ } on ok {} { -#@ set what [$c eval set ::tcl::debug] -#@ if {$doVerbose} { -#@ tclLog "successful $what of $file" -#@ } -#@ set type [$c eval set ::tcl::type] -#@ set cmds [lsort [$c eval array names ::tcl::newCmds]] -#@ set pkgs [$c eval set ::tcl::newPkgs] -#@ if {$doVerbose} { -#@ if {!$direct} { -#@ tclLog "commands provided were $cmds" -#@ } -#@ tclLog "packages provided were $pkgs" -#@ } -#@ if {[llength $pkgs] > 1} { -#@ tclLog "warning: \"$file\" provides more than one package ($pkgs)" -#@ } -#@ foreach pkg $pkgs { -#@ # cmds is empty/not used in the direct case -#@ lappend files($pkg) [list $file $type $cmds] -#@ } -#@ -#@ if {$doVerbose} { -#@ tclLog "processed $file" -#@ } -#@ } -#@ interp delete $c -#@ } -#@ -#@ append index "# Tcl package index file, version 1.1\n" -#@ append index "# This file is generated by the \"pkg_mkIndex$more\" command\n" -#@ append index "# and sourced either when an application starts up or\n" -#@ append index "# by a \"package unknown\" script. It invokes the\n" -#@ append index "# \"package ifneeded\" command to set up package-related\n" -#@ append index "# information so that packages will be loaded automatically\n" -#@ append index "# in response to \"package require\" commands. When this\n" -#@ append index "# script is sourced, the variable \$dir must contain the\n" -#@ append index "# full path name of this file's directory.\n" -#@ -#@ foreach pkg [lsort [array names files]] { -#@ set cmd {} -#@ lassign $pkg name version -#@ lappend cmd ::tcl::Pkg::Create -name $name -version $version -#@ foreach spec [lsort -index 0 $files($pkg)] { -#@ foreach {file type procs} $spec { -#@ if {$direct} { -#@ set procs {} -#@ } -#@ lappend cmd "-$type" [list $file $procs] -#@ } -#@ } -#@ append index "\n[eval $cmd]" -#@ } -#@ -#@ set f [open [file join $dir pkgIndex.tcl] w] -#@ puts $f $index -#@ close $f -#@ } -#@ -#@ # tclPkgSetup -- -#@ # This is a utility procedure use by pkgIndex.tcl files. It is invoked as -#@ # part of a "package ifneeded" script. It calls "package provide" to indicate -#@ # that a package is available, then sets entries in the auto_index array so -#@ # that the package's files will be auto-loaded when the commands are used. -#@ # -#@ # Arguments: -#@ # dir - Directory containing all the files for this package. -#@ # pkg - Name of the package (no version number). -#@ # version - Version number for the package, such as 2.1.3. -#@ # files - List of files that constitute the package. Each -#@ # element is a sub-list with three elements. The first -#@ # is the name of a file relative to $dir, the second is -#@ # "load" or "source", indicating whether the file is a -#@ # loadable binary or a script to source, and the third -#@ # is a list of commands defined by this file. -#@ -#@ proc tclPkgSetup {dir pkg version files} { -#@ global auto_index -#@ -#@ package provide $pkg $version -#@ foreach fileInfo $files { -#@ set f [lindex $fileInfo 0] -#@ set type [lindex $fileInfo 1] -#@ foreach cmd [lindex $fileInfo 2] { -#@ if {$type eq "load"} { -#@ set auto_index($cmd) [list load [file join $dir $f] $pkg] -#@ } else { -#@ set auto_index($cmd) [list source [file join $dir $f]] -#@ } -#@ } -#@ } -#@ } -#@ -#@ # tclPkgUnknown -- -#@ # This procedure provides the default for the "package unknown" function. It -#@ # is invoked when a package that's needed can't be found. It scans the -#@ # auto_path directories and their immediate children looking for pkgIndex.tcl -#@ # files and sources any such files that are found to setup the package -#@ # database. As it searches, it will recognize changes to the auto_path and -#@ # scan any new directories. -#@ # -#@ # Arguments: -#@ # name - Name of desired package. Not used. -#@ # version - Version of desired package. Not used. -#@ # exact - Either "-exact" or omitted. Not used. -#@ -#@ proc tclPkgUnknown {name args} { -#@ global auto_path env -#@ -#@ if {![info exists auto_path]} { -#@ return -#@ } -#@ # Cache the auto_path, because it may change while we run through the -#@ # first set of pkgIndex.tcl files -#@ set old_path [set use_path $auto_path] -#@ while {[llength $use_path]} { -#@ set dir [lindex $use_path end] -#@ -#@ # Make sure we only scan each directory one time. -#@ if {[info exists tclSeenPath($dir)]} { -#@ set use_path [lrange $use_path 0 end-1] -#@ continue -#@ } -#@ set tclSeenPath($dir) 1 -#@ -#@ # we can't use glob in safe interps, so enclose the following in a -#@ # catch statement, where we get the pkgIndex files out of the -#@ # subdirectories -#@ catch { -#@ foreach file [glob -directory $dir -join -nocomplain * pkgIndex.tcl] { -#@ set dir [file dirname $file] -#@ if {![info exists procdDirs($dir)]} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ } -#@ set dir [lindex $use_path end] -#@ if {![info exists procdDirs($dir)]} { -#@ set file [file join $dir pkgIndex.tcl] -#@ # safe interps usually don't have "file exists", -#@ if {([interp issafe] || [file exists $file])} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ -#@ set use_path [lrange $use_path 0 end-1] -#@ -#@ # Check whether any of the index scripts we [source]d above set a new -#@ # value for $::auto_path. If so, then find any new directories on the -#@ # $::auto_path, and lappend them to the $use_path we are working from. -#@ # This gives index scripts the (arguably unwise) power to expand the -#@ # index script search path while the search is in progress. -#@ set index 0 -#@ if {[llength $old_path] == [llength $auto_path]} { -#@ foreach dir $auto_path old $old_path { -#@ if {$dir ne $old} { -#@ # This entry in $::auto_path has changed. -#@ break -#@ } -#@ incr index -#@ } -#@ } -#@ -#@ # $index now points to the first element of $auto_path that has -#@ # changed, or the beginning if $auto_path has changed length Scan the -#@ # new elements of $auto_path for directories to add to $use_path. -#@ # Don't add directories we've already seen, or ones already on the -#@ # $use_path. -#@ foreach dir [lrange $auto_path $index end] { -#@ if {![info exists tclSeenPath($dir)] && ($dir ni $use_path)} { -#@ lappend use_path $dir -#@ } -#@ } -#@ set old_path $auto_path -#@ } -#@ } -#@ -#@ # tcl::MacOSXPkgUnknown -- -#@ # This procedure extends the "package unknown" function for MacOSX. It scans -#@ # the Resources/Scripts directories of the immediate children of the auto_path -#@ # directories for pkgIndex files. -#@ # -#@ # Arguments: -#@ # original - original [package unknown] procedure -#@ # name - Name of desired package. Not used. -#@ # version - Version of desired package. Not used. -#@ # exact - Either "-exact" or omitted. Not used. -#@ -#@ proc tcl::MacOSXPkgUnknown {original name args} { -#@ # First do the cross-platform default search -#@ uplevel 1 $original [linsert $args 0 $name] -#@ -#@ # Now do MacOSX specific searching -#@ global auto_path -#@ -#@ if {![info exists auto_path]} { -#@ return -#@ } -#@ # Cache the auto_path, because it may change while we run through the -#@ # first set of pkgIndex.tcl files -#@ set old_path [set use_path $auto_path] -#@ while {[llength $use_path]} { -#@ set dir [lindex $use_path end] -#@ -#@ # Make sure we only scan each directory one time. -#@ if {[info exists tclSeenPath($dir)]} { -#@ set use_path [lrange $use_path 0 end-1] -#@ continue -#@ } -#@ set tclSeenPath($dir) 1 -#@ -#@ # get the pkgIndex files out of the subdirectories -#@ foreach file [glob -directory $dir -join -nocomplain * Resources Scripts pkgIndex.tcl] { -#@ set dir [file dirname $file] -#@ if {![info exists procdDirs($dir)]} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ set use_path [lrange $use_path 0 end-1] -#@ -#@ # Check whether any of the index scripts we [source]d above set a new -#@ # value for $::auto_path. If so, then find any new directories on the -#@ # $::auto_path, and lappend them to the $use_path we are working from. -#@ # This gives index scripts the (arguably unwise) power to expand the -#@ # index script search path while the search is in progress. -#@ set index 0 -#@ if {[llength $old_path] == [llength $auto_path]} { -#@ foreach dir $auto_path old $old_path { -#@ if {$dir ne $old} { -#@ # This entry in $::auto_path has changed. -#@ break -#@ } -#@ incr index -#@ } -#@ } -#@ -#@ # $index now points to the first element of $auto_path that has -#@ # changed, or the beginning if $auto_path has changed length Scan the -#@ # new elements of $auto_path for directories to add to $use_path. -#@ # Don't add directories we've already seen, or ones already on the -#@ # $use_path. -#@ foreach dir [lrange $auto_path $index end] { -#@ if {![info exists tclSeenPath($dir)] && ($dir ni $use_path)} { -#@ lappend use_path $dir -#@ } -#@ } -#@ set old_path $auto_path -#@ } -#@ } -#@ -#@ # ::tcl::Pkg::Create -- -#@ # -#@ # Given a package specification generate a "package ifneeded" statement -#@ # for the package, suitable for inclusion in a pkgIndex.tcl file. -#@ # -#@ # Arguments: -#@ # args arguments used by the Create function: -#@ # -name packageName -#@ # -version packageVersion -#@ # -load {filename ?{procs}?} -#@ # ... -#@ # -source {filename ?{procs}?} -#@ # ... -#@ # -#@ # Any number of -load and -source parameters may be -#@ # specified, so long as there is at least one -load or -#@ # -source parameter. If the procs component of a module -#@ # specifier is left off, that module will be set up for -#@ # direct loading; otherwise, it will be set up for lazy -#@ # loading. If both -source and -load are specified, the -#@ # -load'ed files will be loaded first, followed by the -#@ # -source'd files. -#@ # -#@ # Results: -#@ # An appropriate "package ifneeded" statement for the package. -#@ -#@ proc ::tcl::Pkg::Create {args} { -#@ append err(usage) "[lindex [info level 0] 0] " -#@ append err(usage) "-name packageName -version packageVersion" -#@ append err(usage) "?-load {filename ?{procs}?}? ... " -#@ append err(usage) "?-source {filename ?{procs}?}? ..." -#@ -#@ set err(wrongNumArgs) "wrong # args: should be \"$err(usage)\"" -#@ set err(valueMissing) "value for \"%s\" missing: should be \"$err(usage)\"" -#@ set err(unknownOpt) "unknown option \"%s\": should be \"$err(usage)\"" -#@ set err(noLoadOrSource) "at least one of -load and -source must be given" -#@ -#@ # process arguments -#@ set len [llength $args] -#@ if {$len < 6} { -#@ error $err(wrongNumArgs) -#@ } -#@ -#@ # Initialize parameters -#@ array set opts {-name {} -version {} -source {} -load {}} -#@ -#@ # process parameters -#@ for {set i 0} {$i < $len} {incr i} { -#@ set flag [lindex $args $i] -#@ incr i -#@ switch -glob -- $flag { -#@ "-name" - -#@ "-version" { -#@ if {$i >= $len} { -#@ error [format $err(valueMissing) $flag] -#@ } -#@ set opts($flag) [lindex $args $i] -#@ } -#@ "-source" - -#@ "-load" { -#@ if {$i >= $len} { -#@ error [format $err(valueMissing) $flag] -#@ } -#@ lappend opts($flag) [lindex $args $i] -#@ } -#@ default { -#@ error [format $err(unknownOpt) [lindex $args $i]] -#@ } -#@ } -#@ } -#@ -#@ # Validate the parameters -#@ if {![llength $opts(-name)]} { -#@ error [format $err(valueMissing) "-name"] -#@ } -#@ if {![llength $opts(-version)]} { -#@ error [format $err(valueMissing) "-version"] -#@ } -#@ -#@ if {!([llength $opts(-source)] || [llength $opts(-load)])} { -#@ error $err(noLoadOrSource) -#@ } -#@ -#@ # OK, now everything is good. Generate the package ifneeded statment. -#@ set cmdline "package ifneeded $opts(-name) $opts(-version) " -#@ -#@ set cmdList {} -#@ set lazyFileList {} -#@ -#@ # Handle -load and -source specs -#@ foreach key {load source} { -#@ foreach filespec $opts(-$key) { -#@ lassign $filespec filename proclist -#@ -#@ if { [llength $proclist] == 0 } { -#@ set cmd "\[list $key \[file join \$dir [list $filename]\]\]" -#@ lappend cmdList $cmd -#@ } else { -#@ lappend lazyFileList [list $filename $key $proclist] -#@ } -#@ } -#@ } -#@ -#@ if {[llength $lazyFileList]} { -#@ lappend cmdList "\[list tclPkgSetup \$dir $opts(-name) $opts(-version) [list $lazyFileList]\]" -#@ } -#@ append cmdline [join $cmdList "\\n"] -#@ return $cmdline -#@ } -#@ -#@ interp alias {} ::pkg::create {} ::tcl::Pkg::Create -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/package.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/pkgIndex.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ package ifneeded cae 1.0 [list source [file join $dir syn.tcl]] -#@ package ifneeded cae::utils 1.0 [list source [file join $dir utils utils.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/iwidgets4.1/pkgIndex.tcl - -#@ # Tcl package index file -#@ package ifneeded iwidgets 4.1 " -#@ package require itk 4 -#@ namespace eval ::iwidgets { -#@ namespace export * -#@ variable library [file dirname [info script]] -#@ variable version 4.1 -#@ } -#@ source [file join $dir colors.itcl] -#@ source [file join $dir roman.itcl] -#@ source [file join $dir buttonbox.itk] -#@ source [file join $dir calendar.itk] -#@ source [file join $dir canvasprintbox.itk] -#@ source [file join $dir shell.itk] -#@ source [file join $dir dialogshell.itk] -#@ source [file join $dir dialog.itk] -#@ source [file join $dir canvasprintdialog.itk] -#@ source [file join $dir labeledframe.itk] -#@ source [file join $dir checkbox.itk] -#@ source [file join $dir labeledwidget.itk] -#@ source [file join $dir entryfield.itk] -#@ source [file join $dir combobox.itk] -#@ source [file join $dir datefield.itk] -#@ source [file join $dir dateentry.itk] -#@ source [file join $dir disjointlistbox.itk] -#@ source [file join $dir extbutton.itk] -#@ source [file join $dir extfileselectionbox.itk] -#@ source [file join $dir extfileselectiondialog.itk] -#@ source [file join $dir feedback.itk] -#@ source [file join $dir fileselectionbox.itk] -#@ source [file join $dir fileselectiondialog.itk] -#@ source [file join $dir finddialog.itk] -#@ source [file join $dir scrolledwidget.itk] -#@ source [file join $dir hierarchy.itk] -#@ source [file join $dir hyperhelp.itk] -#@ source [file join $dir mainwindow.itk] -#@ source [file join $dir menubar.itk] -#@ source [file join $dir messagebox.itk] -#@ source [file join $dir messagedialog.itk] -#@ source [file join $dir notebook.itk] -#@ source [file join $dir optionmenu.itk] -#@ source [file join $dir panedwindow.itk] -#@ source [file join $dir pane.itk] -#@ source [file join $dir promptdialog.itk] -#@ source [file join $dir pushbutton.itk] -#@ source [file join $dir radiobox.itk] -#@ source [file join $dir regexpfield.itk] -#@ source [file join $dir scrolledcanvas.itk] -#@ source [file join $dir scrolledframe.itk] -#@ source [file join $dir scrolledtext.itk] -#@ source [file join $dir scrolledhtml.itk] -#@ source [file join $dir scrolledlistbox.itk] -#@ source [file join $dir selectionbox.itk] -#@ source [file join $dir selectiondialog.itk] -#@ source [file join $dir spindate.itk] -#@ source [file join $dir spinner.itk] -#@ source [file join $dir spinint.itk] -#@ source [file join $dir spintime.itk] -#@ source [file join $dir tabnotebook.itk] -#@ source [file join $dir tabset.itk] -#@ source [file join $dir timefield.itk] -#@ source [file join $dir timeentry.itk] -#@ source [file join $dir toolbar.itk] -#@ source [file join $dir watch.itk] -#@ package provide iwidgets 4.1 -#@ " -#@ -#@ package ifneeded Iwidgets 4.1 " -#@ package require iwidgets 4.1 -#@ package provide Iwidgets 4.1 -#@ " -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/iwidgets4.1/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTclPro/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsTclPro 1.0 [list source [file join $dir snpsTclPro.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTclPro/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTest/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsTest 1.0 [list source [file join $dir snpsTest.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTest/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsUtils/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsUtils 1.0 [list source [file join $dir snpsUtils.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsUtils/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/pkgIndex.tcl - -#@ package ifneeded Itcl 3.4 {load {} Itcl} -#@ package ifneeded tbcload 1.7 {load {} tbcload} -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/reg/pkgIndex.tcl - -#@ if {([info commands ::tcl::pkgconfig] eq "") -#@ || ([info sharedlibextension] ne ".dll")} return -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/reg/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/dde/pkgIndex.tcl - -#@ if {([info commands ::tcl::pkgconfig] eq "") -#@ || ([info sharedlibextension] ne ".dll")} return -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/dde/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/platform/pkgIndex.tcl - -#@ package ifneeded platform 1.0.13 [list source [file join $dir platform.tcl]] -#@ package ifneeded platform::shell 1.1.4 [list source [file join $dir shell.tcl]] -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/platform/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tcltest/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ if {![package vsatisfies [package provide Tcl] 8.5]} {return} -#@ package ifneeded tcltest 2.3.8 [list source [file join $dir tcltest.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tcltest/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http/pkgIndex.tcl - -#@ if {![package vsatisfies [package provide Tcl] 8.6]} {return} -#@ package ifneeded http 2.8.8 [list tclPkgSetup $dir http 2.8.8 {{http.tcl source {::http::config ::http::formatQuery ::http::geturl ::http::reset ::http::wait ::http::register ::http::unregister ::http::mapReply}}}] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/msgcat/pkgIndex.tcl - -#@ if {![package vsatisfies [package provide Tcl] 8.5]} {return} -#@ package ifneeded msgcat 1.5.2 [list source [file join $dir msgcat.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/msgcat/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http1.0/pkgIndex.tcl - -#@ # Tcl package index file, version 1.0 -#@ # This file is generated by the "pkg_mkIndex" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded http 1.0 [list tclPkgSetup $dir http 1.0 {{http.tcl source {httpCopyDone httpCopyStart httpEof httpEvent httpFinish httpMapReply httpProxyRequired http_code http_config http_data http_formatQuery http_get http_reset http_size http_status http_wait}}}] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http1.0/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/opt/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ if {![package vsatisfies [package provide Tcl] 8.2]} {return} -#@ package ifneeded opt 0.4.6 [list source [file join $dir optparse.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/opt/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/syn.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ # primary file of syn package -#@ -#@ # require all the sub-packages (if any) -#@ -#@ # name of the provided package -#@ -#@ package provide cae 1.0 -#@ -#@ # create command group after loading sub packages -#@ # because last group is listed first by "help" -#@ -#@ create_command_group "syn" -info "synthesis utilities" -#@ -#@ namespace eval ::cae { -#@ variable selfdir [file dirname [info script]] -#@ variable scripts [list auto_path_groups.tcl ] -#@ variable script -#@ } -#@ -#@ # source encrypted version if available -#@ # encrypted commands must use "define_proc_attributes -hide_body" -#@ -#@ foreach ::cae::script ${::cae::scripts} { -#@ if { [file exists ${::cae::selfdir}/${::cae::script}.e] } { -#@ source ${::cae::selfdir}/${::cae::script}.e -#@ } else { -#@ source ${::cae::selfdir}/${::cae::script} -#@ } -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/auto_path_groups.tcl - -#@ # Copyright (c) 2016-2017 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ package require cae::utils -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/utils/utils.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ # primary file of cae::utils package -#@ -#@ # name of the provided package -#@ -#@ package provide cae::utils 1.0 -#@ -#@ namespace eval ::cae::utils { -#@ } -#@ -#@ proc ::cae::utils::msg { type s } { -#@ switch -glob -- ${type} { -#@ i* { return "INFO: ${s}" } -#@ w* { return "WARNING: ${s}" } -#@ e* { return "ERROR: ${s}" } -#@ } -#@ return -#@ } -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/utils/utils.tcl - -#@ -#@ namespace eval ::cae { -#@ -#@ # note: check if these are all necessary -#@ variable auto_path_groups_messages {ATTR-3 OPT-806 OPT-774 UID-101 TIM-134 TIM-99 OPT-806 MWUI-203 MW-212 TIM-112} -#@ -#@ # default prefix for path groups -#@ variable auto_path_groups_prefix synopsys_pg_ -#@ # default slack for path groups -#@ variable auto_path_groups_slack 0.0 -#@ # default max for path groups -#@ variable auto_path_groups_max 0 -#@ # default verbosity -#@ variable auto_path_groups_verbose false -#@ # default priority -#@ variable auto_path_groups_priority 1 -#@ # default min_regs_per_hierarchy -#@ variable auto_path_groups_min_regs_per_hierarchy 10 -#@ # registers path group suffix -#@ variable auto_path_groups_reg_suffix to_regs_ -#@ # macro path group suffix -#@ variable auto_path_groups_to_macro_suffix to_macros_ -#@ # macro path group suffix -#@ variable auto_path_groups_from_macro_suffix from_macros_ -#@ # ICG path group suffix -#@ variable auto_path_groups_icg_suffix to_ICGs -#@ # input path group suffix -#@ variable auto_path_groups_input_suffix inputs -#@ # output path group suffix -#@ variable auto_path_groups_output_suffix outputs -#@ # feedthrough path group suffix -#@ variable auto_path_groups_feedthrough_suffix feedthrough -#@ # user path groups -#@ variable auto_path_groups_user_path_groups_file auto_path_groups.user_path_groups.tcl -#@ } -#@ -#@ proc create_auto_path_groups { args } { -#@ variable ::cae::auto_path_groups_messages -#@ variable ::cae::auto_path_groups_prefix -#@ variable ::cae::auto_path_groups_slack -#@ variable ::cae::auto_path_groups_max -#@ variable ::cae::auto_path_groups_verbose -#@ variable ::cae::auto_path_groups_priority -#@ variable ::cae::auto_path_groups_min_regs_per_hierarchy -#@ variable ::cae::auto_path_groups_reg_suffix -#@ variable ::cae::auto_path_groups_to_macro_suffix -#@ variable ::cae::auto_path_groups_from_macro_suffix -#@ variable ::cae::auto_path_groups_icg_suffix -#@ variable ::cae::auto_path_groups_input_suffix -#@ variable ::cae::auto_path_groups_output_suffix -#@ variable ::cae::auto_path_groups_feedthrough_suffix -#@ variable ::cae::auto_path_groups_user_path_groups_file -#@ -#@ set options(-slack) ${auto_path_groups_slack} -#@ set options(-max) ${auto_path_groups_max} -#@ set options(-prefix) ${auto_path_groups_prefix} -#@ set options(-verbose) ${auto_path_groups_verbose} -#@ set options(-priority) ${auto_path_groups_priority} -#@ set options(-min_regs_per_hierarchy) ${auto_path_groups_min_regs_per_hierarchy} -#@ set options(-exclude) [list] -#@ set options(-user_path_groups_file) ${auto_path_groups_user_path_groups_file} -#@ -#@ parse_proc_arguments -args ${args} options -#@ -#@ if { [info exists options(-file)] } { -#@ if { [catch {open $options(-file) w} fileId] } { -#@ return -code error [::cae::utils::msg e ${fileId}] -#@ } -#@ } -#@ -#@ # save user path groups -#@ if { ![info exists options(-skip)] } { -#@ echo [::cae::utils::msg i "Saving user path groups to $options(-user_path_groups_file)..."] -#@ if { [file exist $options(-user_path_groups_file)] } { -#@ echo [::cae::utils::msg w "File $options(-user_path_groups_file) already exists and will be overwritten..."] -#@ } -#@ if { [catch {open "| grep \"^group_path\" > $options(-user_path_groups_file)" w} channelId] } { -#@ return -code error [::cae::utils::msg e ${channelId}] -#@ } -#@ redirect -channel ${channelId} { write_script -nosplit } -#@ set r [catch {close ${channelId}} msg] -#@ switch ${r} { -#@ 0 { echo [::cae::utils::msg i "User path groups saved"] } -#@ 1 { echo [::cae::utils::msg i "No user path groups to save"] } -#@ default { return -code error [::cae::utils::msg e ${msg}] } -#@ } -#@ } -#@ -#@ set total 0 -#@ -#@ suppress_message ${auto_path_groups_messages} -#@ switch -- $options(-mode) { -#@ "rtl" { -#@ # create one path group per hierarchy -#@ -#@ echo [::cae::utils::msg i "Collecting hierarchies without optimize_registers..."] -#@ set optimize_registers_cells [get_cells -hier -filter {is_hierarchical==true && optimize_registers==true}] -#@ if { $options(-verbose) } { -#@ set optimize_registers_cells_names [lsort [get_object_name ${optimize_registers_cells}]] -#@ echo [::cae::utils::msg i "cells with optimize_registers: ${optimize_registers_cells_names}"] -#@ } -#@ set optimize_registers_sub_cells {} -#@ foreach_in_collection cell ${optimize_registers_cells} { -#@ redirect -file /dev/null {current_instance ${cell}} -#@ append_to_collection optimize_registers_sub_cells [get_cells -hier -filter {is_hierarchical==true && (optimize_registers==false || undefined(optimize_registers))}] -#@ } -#@ redirect -file /dev/null {current_instance} -#@ if { $options(-verbose) } { -#@ set optimize_registers_sub_cells_names [lsort [get_object_name ${optimize_registers_sub_cells}]] -#@ echo [::cae::utils::msg i "sub-cells of cells with optimize_registers: ${optimize_registers_sub_cells_names}"] -#@ } -#@ set path_group_cells [get_cells -hier -filter {is_hierarchical==true && is_sequential==true && (optimize_registers==false || undefined(optimize_registers))}] -#@ set path_group_cells [remove_from_collection ${path_group_cells} ${optimize_registers_sub_cells}] -#@ -#@ echo [::cae::utils::msg i "Collected [sizeof_collection ${path_group_cells}] hierarchies without optimize_registers"] -#@ -#@ set path_group_names [lsort [get_object_name ${path_group_cells}]] -#@ -#@ if { $options(-verbose) } { -#@ echo [::cae::utils::msg i "cells for which path groups will be created:"] -#@ foreach path_group_name ${path_group_names} { -#@ echo [::cae::utils::msg i " ${path_group_name}"] -#@ } -#@ } -#@ -#@ echo [::cae::utils::msg i "Creating path groups for hierarchies without optimize_registers..."] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ set number_of_registers [sizeof_collection [get_cells ${path_group_name}/* -filter "is_hierarchical==false && is_sequential==true"]] -#@ if { ${number_of_registers} > $options(-min_regs_per_hierarchy) } { -#@ echo [::cae::utils::msg i "Number of sequential cells found in ${path_group_name} hierarchy: ${number_of_registers}"] -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells ${path_group_name}/* -filter \"is_hierarchical==false && is_sequential==true\"\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } else { -#@ echo [::cae::utils::msg i "Not enough sequential cells found in ${path_group_name} hierarchy (${number_of_registers}), skipping..."] -#@ } -#@ } -#@ echo [::cae::utils::msg i "Number of reg path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } -#@ "mapped" { -#@ # create one path group per hierarchy not meeting timing -#@ -#@ array unset fail -#@ echo [::cae::utils::msg i "Collecting hierarchies with timing violations..."] -#@ foreach_in_collection pin [all_registers -data_pins] { -#@ set slack [get_attribute ${pin} max_slack] -#@ if { ${slack} < $options(-slack) && ${slack} != "" } { -#@ set cell [get_cells -of_objects ${pin}] -#@ set full_name [get_attribute ${cell} full_name] -#@ set name [get_attribute ${cell} name] -#@ if {[string length ${full_name}] > [string length ${name}]} { -#@ set length [expr [string length ${full_name}] - [string length ${name}] - 1] -#@ set hierarchy [string range ${full_name} 0 [expr ${length} - 1]] -#@ } else { -#@ set hierarchy "" -#@ } -#@ if { ![info exists fail(${hierarchy})] || -#@ ([info exists fail(${hierarchy})] && ${slack} < $fail(${hierarchy})) } { -#@ set fail(${hierarchy}) ${slack} -#@ } -#@ } -#@ } -#@ echo [::cae::utils::msg i "Collected [array size fail] hierarchies with timing violations"] -#@ -#@ if { $options(-max) > 0 } { -#@ echo [::cae::utils::msg i "Keeping only $options(-max) hierarchies with worst timing violations"] -#@ set hierarchy_slack_list [lsort -stride 2 -index 1 -real -increasing [array get fail]] -#@ set hierarchy_slack_list [lrange ${hierarchy_slack_list} 0 [expr {2 * $options(-max) - 1}]] -#@ array unset fail -#@ array set fail ${hierarchy_slack_list} -#@ } -#@ -#@ set path_group_names [lsort [array names fail]] -#@ -#@ if { $options(-verbose) } { -#@ echo [::cae::utils::msg i "hierarchies for which path groups will be created:"] -#@ foreach path_group_name ${path_group_names} { -#@ echo [::cae::utils::msg i " ${path_group_name} $fail(${path_group_name})"] -#@ } -#@ } -#@ -#@ echo [::cae::utils::msg i "Creating path groups for hierarchies with timing violations..."] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ if { ${path_group_name} == "" } { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells * -filter {is_hierarchical==false && is_sequential==true}\] -priority $options(-priority)" -#@ } else { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells ${path_group_name}/* -filter {is_hierarchical==false && is_sequential==true}\] -priority $options(-priority)" -#@ } -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } -#@ echo [::cae::utils::msg i "Number of reg path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ -#@ } -#@ -#@ } -#@ -#@ # macro path groups -#@ if { [lsearch $options(-exclude) macro] == -1} { -#@ echo [::cae::utils::msg i "Creating macro path groups..."] -#@ if { [shell_is_in_topographical_mode] } { -#@ #set macro_cells [all_macro_cells] -#@ set macro_cells [remove_from_collection [all_macro_cells] [get_cells -quiet -hier -all -filter "is_physical_only==true"]] -#@ } else { -#@ set macro_cells [get_cells -hier * -filter "is_macro_cell == true"] -#@ } -#@ if { [sizeof_collection ${macro_cells}] != 0 } { -#@ set path_group_names [get_object_name ${macro_cells}] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_to_macro_suffix}${counter} -to \[get_cells ${path_group_name}\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_from_macro_suffix}${counter} -from \[get_cells ${path_group_name}\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } -#@ echo [::cae::utils::msg i "Number of macro path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } else { -#@ echo [::cae::utils::msg i "No macro found, skipping..."] -#@ } -#@ } -#@ -#@ # ICG path groups -#@ if { [lsearch $options(-exclude) ICG] == -1} { -#@ echo [::cae::utils::msg i "Creating ICG path groups..."] -#@ set all_icg_cells [get_cells -hier -filter "full_name=~*latch || full_name=~*u_clkgate && defined(clock_gating_integrated_cell)"] -#@ if { [sizeof_collection ${all_icg_cells}] } { -#@ set counter 0 -#@ set command "group_path -name $options(-prefix)${auto_path_groups_icg_suffix} -to \[get_cells -hier -filter \"full_name=~*latch || full_name=~*u_clkgate && defined(clock_gating_integrated_cell)\"\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ echo [::cae::utils::msg i "Number of ICG path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } else { -#@ echo [::cae::utils::msg i "No ICG found, skipping..."] -#@ } -#@ } -#@ -#@ # IO path groups -#@ if { [lsearch $options(-exclude) IO] == -1} { -#@ echo [::cae::utils::msg i "Creating IO path groups..."] -#@ set counter 0 -#@ set command "group_path -name $options(-prefix)${auto_path_groups_input_suffix} -from \[ remove_from_collection \[all_inputs\] \[get_ports \[get_attribute \[get_clocks -filter defined(sources)\] sources\]\] \]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_output_suffix} -to \[all_outputs\]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_feedthrough_suffix} -from \[ remove_from_collection \[all_inputs\] \[get_ports \[get_attribute \[get_clocks -filter defined(sources)\] sources\]\] \] -to \[all_outputs\]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ echo [::cae::utils::msg i "Number of IO path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } -#@ -#@ unsuppress_message ${auto_path_groups_messages} -#@ -#@ echo [::cae::utils::msg i "Total number of path groups created: ${total}"] -#@ -#@ if { [info exists options(-file)] } { -#@ close ${fileId} -#@ } -#@ -#@ return -#@ } -#@ -#@ define_proc_attributes create_auto_path_groups -command_group syn -dont_abbrev -hide_body -info "Creates path groups for current design" -define_args { -#@ { -mode "creates path groups for unmapped/mapped netlist" mode one_of_string {required value_help {values {rtl mapped}}} } -#@ { -exclude "excludes specific path groups (IO ICG macro) (default: empty list)" list list {optional} } -#@ { -slack "slack value used to select hierarchy violating timing (default: 0.0) - mapped mode only" slack float optional } -#@ { -max "maximum number of paths groups (default: 0=unlimited) - mapped mode only" max int optional } -#@ { -min_regs_per_hierarchy "minimum number of registers per hierarchy (default: 10) - rtl mode only" min_regs int optional } -#@ { -prefix "path group name prefix (default: synopsys_pg_)" prefix string optional } -#@ { -file "file name to dump group_path commands" file_name string optional } -#@ { -verbose "verbose mode" "" boolean optional } -#@ { -user_path_groups_file "save user path groups to this file" file_name string optional } -#@ { -skip "do not save user path groups" "" boolean optional } -#@ } -#@ -#@ proc remove_auto_path_groups { args } { -#@ variable ::cae::auto_path_groups_messages -#@ variable ::cae::auto_path_groups_prefix -#@ variable ::cae::auto_path_groups_verbose -#@ variable ::cae::auto_path_groups_user_path_groups_file -#@ -#@ set options(-prefix) ${auto_path_groups_prefix} -#@ set options(-verbose) ${auto_path_groups_verbose} -#@ set options(-user_path_groups_file) ${auto_path_groups_user_path_groups_file} -#@ -#@ parse_proc_arguments -args ${args} options -#@ -#@ if { [info exists options(-file)] } { -#@ if {[catch {open $options(-file) w } fileId] } { -#@ return -code error [::cae::utils::msg e ${fileId}] -#@ } -#@ } -#@ -#@ suppress_message ${auto_path_groups_messages} -#@ set path_group_names [get_object_name [get_path_group -filter "full_name =~ $options(-prefix)*"]] -#@ foreach path_group_name ${path_group_names} { -#@ set command "remove_path_group ${path_group_name}" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ } -#@ echo [::cae::utils::msg i "Number of path groups removed: [llength ${path_group_names}]"] -#@ unsuppress_message ${auto_path_groups_messages} -#@ -#@ if { [info exists options(-file)] } { -#@ close ${fileId} -#@ } -#@ -#@ # restore user path groups -#@ if { ![info exists options(-skip)] } { -#@ echo [::cae::utils::msg i "Restoring user path groups from $options(-user_path_groups_file)..."] -#@ if { [file exist $options(-user_path_groups_file)] } { -#@ if { [file size $options(-user_path_groups_file)] != 0} { -#@ source -continue_on_error $options(-user_path_groups_file) -#@ } else { -#@ echo [::cae::utils::msg i "No user path groups to restore"] -#@ } -#@ file delete -force $options(-user_path_groups_file) -#@ } else { -#@ echo [::cae::utils::msg w "File $options(-user_path_groups_file) doesn't exist"] -#@ } -#@ } -#@ -#@ return -#@ } -#@ -#@ define_proc_attributes remove_auto_path_groups -command_group syn -dont_abbrev -hide_body -info "Removes path groups for current design" -define_args { -#@ { -prefix "path group name prefix (default: synopsys_pg)" prefix string optional } -#@ { -file "file name to dump group_path commands" file_name string optional } -#@ { -verbose "verbose mode" "" boolean optional } -#@ { -user_path_groups_file "restore user path groups from this file" file_name string optional } -#@ { -skip "do not restore user path groups" "" boolean optional } -#@ } -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/auto_path_groups.tcl - -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/syn.tcl - -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "linux64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_opt.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_cmd.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_rpt.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || [string match -nocase {*dc_shell*} $synopsys_program_name] || [string match -nocase {*de_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/write_timing_context.tcl.e; -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/write_scenarios.tbc; -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ if {[catch {set token [array startsearch loc_ary]}]} { -#@ return $ret -#@ } -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: filter_collection -#@ # Description: DC wrapper for filter_collection with fixes of direction filter -#@ # -#@ # This is a fix for DC's filter using "direction" attribute. This -#@ # attribute is of integer type, but user wants a string format -#@ ############################################################################## -#@ if {[string match -nocase {*icc_shell*} $synopsys_program_name] == 0} { -#@ rename -force -hidden filter_collection _real_filter_collection -#@ proc filter_collection {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set regexp "" -#@ set nocase "" -#@ if {[info exist ra(-regexp)]} { -#@ set regexp "-regexp" -#@ } -#@ if {[info exist ra(-nocase)]} { -#@ set nocase "-nocase" -#@ } -#@ set coll $ra(collection1) -#@ -#@ # _real_filter_collection silently returns in this error condition -#@ if {[catch {set coll_size [sizeof_collection $coll]}] || $coll_size <= 0} { -#@ return [list] -#@ } -#@ -#@ if {$::sh_translate_direction_attribute == true} { -#@ set filter_expr [replace_direction $coll $ra(expression)] -#@ } else { -#@ set filter_expr $ra(expression) -#@ } -#@ -#@ # if $ra(expression) is not empty but filter_expr is, collection is heterogrnous -#@ # and expression has "direction" as substring. We have to walk through all objects -#@ if {[string length $filter_expr] == 0 && [string length $ra(expression)] != 0} { -#@ set part1 [format {_real_filter_collection %s %s } $regexp $nocase] -#@ set results "" -#@ set subclxn "" -#@ set subsize [expr [sizeof_collection $coll]/80 + 10] -#@ set counter 0 -#@ foreach_in_collection obj $coll { -#@ incr counter -#@ set cmd [format {%s %s {%s}} $part1 $obj [replace_direction $obj $ra(expression)]] -#@ append_to_collection subclxn [uplevel #0 $cmd] -#@ if {[expr $counter % $subsize] == 0} { -#@ append_to_collection results $subclxn -#@ set subclxn "" -#@ } -#@ } -#@ if {[sizeof_collection $subclxn] != 0} { -#@ append_to_collection results $subclxn -#@ } -#@ return $results -#@ } else { -#@ set cmd [format {_real_filter_collection %s %s %s {%s}} $regexp $nocase $coll $filter_expr] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ define_proc_attributes filter_collection -info " Filter a collection, resulting in new collection " -permanent -define_args { {-regexp "Operators =~ and !~ use regular expressions" "" boolean {optional}} {-nocase "Case insensitive string match" "" boolean {optional}} {collection1 "Collection to filter" "collection1" string {required}} {expression "Filter expression" "expression" string {required}} } -#@ -#@ } -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ set bus_multiple_name_separator_style ",," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_enable_hier_map "FALSE" -#@ set hdlin_sv_interface_only_modules "" -#@ set hdlin_sv_enable_rtl_attributes "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_enable_elaborate_update "true" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_sv_enable_rtl_attributes" -#@ group_variable hdl "hdlin_enable_hier_map" -#@ group_variable hdl "hdlin_sv_interface_only_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_enable_elaborate_update" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.dc_name_rules - -#@ # -#@ -#@ # .dc_name_rules Initialization file for -#@ -#@ # Dc_Shell and Design_Analyzer -#@ -#@ # This files defines name rules for target systems. Change_names -#@ # will use this rules to fix the object names. -#@ -#@ #*/ -#@ -#@ -#@ define_name_rules sverilog -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules sverilog -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules sverilog -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules sverilog -reserved { "always" "always_comb" "always_ff" "always_latch" "and" "assert" "assert_strobe" "assign" "automatic" "begin" "bit" "break" "buf" "bufif0" "bufif1" "byte" "case" "casex" "casez" "cell" "changed" "char" "cmos" "config" "const" "continue" "deassign" "default" "defparam" "design" "disable" "do" "edge" "else" "end" "endcase" "endconfig" "endfunction" "endgenerate" "endinterface" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "endtransition" "enum" "event" "export" "extern" "for" "force" "forever" "fork" "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" "iff" "ifnone" "import" "incdir" "include" "initial" "inout" "input" "instance" "int" "integer" "interface" "join" "large" "liblist" "library" "localparam" "logic" "longint" "longreal" "macromodule" "medium" "modport" "module" "nand" "negedge" "nmos" "nor" "noshowcancelled" "not" "notif0" "notif1" "or" "output" "packed" "parameter" "pmos" "posedge" "primitive" "process" "priority" "pull0" "pull1" "pullup" "pulldown" "pulsestyle_onevent" "pulsestyle_ondetect" "rcmos" "real" "realtime" "reg" "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "shortint" "shortreal" "showcancelled" "signed" "small" "specify" "specparam" "static" "strong0" "strong1" "struct" "supply0" "supply1" "table" "task" "time" "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "transition" "tri" "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" "unique" "use" "unsigned" "vectored" "void" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ define_name_rules verilog -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules verilog -reserved { "always" "and" "assign" "automatic" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cell" "cmos" "config" "deassign" "default" "defparam" "design" "disable" "edge" "else" "end" "endcase" "endconfig" "endfunction" "endgenerate" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "generate" "genvar" "highz0" "highz1" "if" "ifnone" "incdir" "include" "initial" "inout" "input" "instance" "integer" "join" "large" "liblist" "library" "localparam" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" "noshowcancelled" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pullup" "pulldown" "pulsestyle_onevent" "pulsestyle_ondetect" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "showcancelled" "signed" "small" "specify" "specparam" "strong0" "strong1" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "unsigned" "use" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ define_name_rules verilog_1995 -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog_1995 -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog_1995 -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules verilog_1995 -reserved { "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cell" "cmos" "deassign" "default" "defparam" "design" "disable" "edge" "else" "end" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "ifnone" "initial" "inout" "input" "integer" "join" "large" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pullup" "pulldown" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "small" "specify" "specparam" "strong0" "strong1" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ define_name_rules vhdl -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" \ -#@ "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -target_bus_naming_style "%s(%d)" -replacement_char "x" -special vhdl -#@ define_name_rules vhdl -type net -allowed "A-Z a-z _ 0-9 " -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -type port -allowed "A-Z a-z _ 0-9 " -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -type cell -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -map { {{"__","_"},{"_$",""}} } -#@ -#@ ####/* Name rule for VHDL */ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.dc_name_rules - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set lc_run_from_legacy_library_compiler "true" -#@ -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ # make lc man pages search path override the default man page search path -#@ set man_path [linsert $man_path 0 $::env(SYNOPSYS_LC_ROOT)/doc/lc/man] -#@ } else { -#@ set lc_link "$::synopsys_root/$::sh_arch/syn/bin/lc_shell_exec" -#@ while { [file exists $lc_link] && [file type $lc_link] == "link"} { -#@ set lc_link [file readlink $lc_link] -#@ } -#@ # resolve symbol-link to get $exec_path of lc_shell_exec -#@ if { [file exists $lc_link] } { -#@ set LC_ROOT [file dirname [file dirname [file dirname [file dirname $lc_link]]]] -#@ set man_path [linsert $man_path 0 $LC_ROOT/doc/lc/man] -#@ } -#@ } -#@ -#@ source ${synopsys_root}/auxx/syn/lc_commands.tbc -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lc_commands.tbc - -#@ ############################################################################## -#@ # Author : Liping Zhao -#@ # History: 2016/11/21 created -#@ # Description: This is the source tcl file of run_nglc.tbc. -#@ # The procs are all for run library compiler under the hood. -#@ # These procs are exracted from .synopsys_dc.setup -#@ ############################################################################## -#@ # TclPro::Compiler::Include -#@ -#@ if {[catch {package require tbcload 1.6} err] == 1} { -#@ return -code error "[info script]: The TclPro ByteCode Loader is not available or does not support the correct version -- $err" -#@ } -#@ tbcload::bceval { -#@ TclPro ByteCode 2 0 1.7 8.5 -#@ 44 0 426 61 0 0 312 0 12 44 44 -1 -1 -#@ 426 -#@ `:G,f=!CM1qv2&|=!A8#>!*BEKs!6#o9v.EW< -#@ !E;kpvJSapvQXxOwI1IOwI1IOwI1IOwI1IOwI1IOwI1IOwI1IOw -#@ 44 -#@ I%%n#;c(;v0g>a'?qwn#I%%n#I%%n#I%%n#I%%n#I%%n#I%%n#Hq^R# -#@ 61 -#@ x -#@ 4 -#@ ,CHr@ -#@ x -#@ 23 -#@ lj|Z?!aiaEw>m#H8&Z)F5mNaEt-E- -#@ x -#@ 1 -#@ A! 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    :v8P60%.EW pkgname pkgversion]} { -#@ # Ignore everything not matching our pattern for -#@ # package names. -#@ continue -#@ } -#@ try { -#@ package vcompare $pkgversion 0 -#@ } on error {} { -#@ # Ignore everything where the version part is not -#@ # acceptable to "package vcompare". -#@ continue -#@ } -#@ -#@ if {[package ifneeded $pkgname $pkgversion] ne {}} { -#@ # There's already a provide script registered for -#@ # this version of this package. Since all units of -#@ # code claiming to be the same version of the same -#@ # package ought to be identical, just stick with -#@ # the one we already have. -#@ continue -#@ } -#@ -#@ # We have found a candidate, generate a "provide script" -#@ # for it, and remember it. Note that we are using ::list -#@ # to do this; locally [list] means something else without -#@ # the namespace specifier. -#@ -#@ # NOTE. When making changes to the format of the provide -#@ # command generated below CHECK that the 'LOCATE' -#@ # procedure in core file 'platform/shell.tcl' still -#@ # understands it, or, if not, update its implementation -#@ # appropriately. -#@ # -#@ # Right now LOCATE's implementation assumes that the path -#@ # of the package file is the last element in the list. -#@ -#@ package ifneeded $pkgname $pkgversion "[::list package provide $pkgname $pkgversion];[::list source -encoding utf-8 $file]" -#@ -#@ # We abort in this unknown handler only if we got a -#@ # satisfying candidate for the requested package. -#@ # Otherwise we still have to fallback to the regular -#@ # package search to complete the processing. -#@ -#@ if {($pkgname eq $name) -#@ && [package vsatisfies $pkgversion {*}$args]} { -#@ set satisfied 1 -#@ -#@ # We do not abort the loop, and keep adding provide -#@ # scripts for every candidate in the directory, just -#@ # remember to not fall back to the regular search -#@ # anymore. -#@ } -#@ } -#@ } -#@ } -#@ -#@ if {$satisfied} { -#@ return -#@ } -#@ } -#@ -#@ # Fallback to previous command, if existing. See comment above about -#@ # ::list... -#@ -#@ if {[llength $original]} { -#@ uplevel 1 $original [::linsert $args 0 $name] -#@ } -#@ } -#@ -#@ # ::tcl::tm::Defaults -- -#@ # -#@ # Determines the default search paths. -#@ # -#@ # Arguments -#@ # None -#@ # -#@ # Results -#@ # None. -#@ # -#@ # Sideeffects -#@ # May add paths to the list of defaults. -#@ -#@ proc ::tcl::tm::Defaults {} { -#@ global env tcl_platform -#@ -#@ lassign [split [info tclversion] .] major minor -#@ set exe [file normalize [info nameofexecutable]] -#@ -#@ # Note that we're using [::list], not [list] because [list] means -#@ # something other than [::list] in this namespace. -#@ roots [::list [file dirname [info library]] [file join [file dirname [file dirname $exe]] lib] ] -#@ -#@ if {$tcl_platform(platform) eq "windows"} { -#@ set sep ";" -#@ } else { -#@ set sep ":" -#@ } -#@ for {set n $minor} {$n >= 0} {incr n -1} { -#@ foreach ev [::list TCL${major}.${n}_TM_PATH TCL${major}_${n}_TM_PATH ] { -#@ if {![info exists env($ev)]} continue -#@ foreach p [split $env($ev) $sep] { -#@ path add $p -#@ } -#@ } -#@ } -#@ return -#@ } -#@ -#@ # ::tcl::tm::roots -- -#@ # -#@ # Public API to the module path. See specification. -#@ # -#@ # Arguments -#@ # paths - List of 'root' paths to derive search paths from. -#@ # -#@ # Results -#@ # No result. -#@ # -#@ # Sideeffects -#@ # Calls 'path add' to paths to the list of module search paths. -#@ -#@ proc ::tcl::tm::roots {paths} { -#@ lassign [split [package present Tcl] .] major minor -#@ foreach pa $paths { -#@ set p [file join $pa tcl$major] -#@ for {set n $minor} {$n >= 0} {incr n -1} { -#@ set px [file join $p ${major}.${n}] -#@ if {![interp issafe]} {set px [file normalize $px]} -#@ path add $px -#@ } -#@ set px [file join $p site-tcl] -#@ if {![interp issafe]} {set px [file normalize $px]} -#@ path add $px -#@ } -#@ return -#@ } -#@ -#@ # Initialization. Set up the default paths, then insert the new handler into -#@ # the chain. -#@ -#@ if {![interp issafe]} {::tcl::tm::Defaults} -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tm.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/package.tcl - -#@ # package.tcl -- -#@ # -#@ # utility procs formerly in init.tcl which can be loaded on demand -#@ # for package management. -#@ # -#@ # Copyright (c) 1991-1993 The Regents of the University of California. -#@ # Copyright (c) 1994-1998 Sun Microsystems, Inc. -#@ # -#@ # See the file "license.terms" for information on usage and redistribution -#@ # of this file, and for a DISCLAIMER OF ALL WARRANTIES. -#@ # -#@ -#@ namespace eval tcl::Pkg {} -#@ -#@ # ::tcl::Pkg::CompareExtension -- -#@ # -#@ # Used internally by pkg_mkIndex to compare the extension of a file to a given -#@ # extension. On Windows, it uses a case-insensitive comparison because the -#@ # file system can be file insensitive. -#@ # -#@ # Arguments: -#@ # fileName name of a file whose extension is compared -#@ # ext (optional) The extension to compare against; you must -#@ # provide the starting dot. -#@ # Defaults to [info sharedlibextension] -#@ # -#@ # Results: -#@ # Returns 1 if the extension matches, 0 otherwise -#@ -#@ proc tcl::Pkg::CompareExtension {fileName {ext {}}} { -#@ global tcl_platform -#@ if {$ext eq ""} {set ext [info sharedlibextension]} -#@ if {$tcl_platform(platform) eq "windows"} { -#@ return [string equal -nocase [file extension $fileName] $ext] -#@ } else { -#@ # Some unices add trailing numbers after the .so, so -#@ # we could have something like '.so.1.2'. -#@ set root $fileName -#@ while {1} { -#@ set currExt [file extension $root] -#@ if {$currExt eq $ext} { -#@ return 1 -#@ } -#@ -#@ # The current extension does not match; if it is not a numeric -#@ # value, quit, as we are only looking to ignore version number -#@ # extensions. Otherwise we might return 1 in this case: -#@ # tcl::Pkg::CompareExtension foo.so.bar .so -#@ # which should not match. -#@ -#@ if {![string is integer -strict [string range $currExt 1 end]]} { -#@ return 0 -#@ } -#@ set root [file rootname $root] -#@ } -#@ } -#@ } -#@ -#@ # pkg_mkIndex -- -#@ # This procedure creates a package index in a given directory. The package -#@ # index consists of a "pkgIndex.tcl" file whose contents are a Tcl script that -#@ # sets up package information with "package require" commands. The commands -#@ # describe all of the packages defined by the files given as arguments. -#@ # -#@ # Arguments: -#@ # -direct (optional) If this flag is present, the generated -#@ # code in pkgMkIndex.tcl will cause the package to be -#@ # loaded when "package require" is executed, rather -#@ # than lazily when the first reference to an exported -#@ # procedure in the package is made. -#@ # -verbose (optional) Verbose output; the name of each file that -#@ # was successfully rocessed is printed out. Additionally, -#@ # if processing of a file failed a message is printed. -#@ # -load pat (optional) Preload any packages whose names match -#@ # the pattern. Used to handle DLLs that depend on -#@ # other packages during their Init procedure. -#@ # dir - Name of the directory in which to create the index. -#@ # args - Any number of additional arguments, each giving -#@ # a glob pattern that matches the names of one or -#@ # more shared libraries or Tcl script files in -#@ # dir. -#@ -#@ proc pkg_mkIndex {args} { -#@ set usage {"pkg_mkIndex ?-direct? ?-lazy? ?-load pattern? ?-verbose? ?--? dir ?pattern ...?"} -#@ -#@ set argCount [llength $args] -#@ if {$argCount < 1} { -#@ return -code error "wrong # args: should be\n$usage" -#@ } -#@ -#@ set more "" -#@ set direct 1 -#@ set doVerbose 0 -#@ set loadPat "" -#@ for {set idx 0} {$idx < $argCount} {incr idx} { -#@ set flag [lindex $args $idx] -#@ switch -glob -- $flag { -#@ -- { -#@ # done with the flags -#@ incr idx -#@ break -#@ } -#@ -verbose { -#@ set doVerbose 1 -#@ } -#@ -lazy { -#@ set direct 0 -#@ append more " -lazy" -#@ } -#@ -direct { -#@ append more " -direct" -#@ } -#@ -load { -#@ incr idx -#@ set loadPat [lindex $args $idx] -#@ append more " -load $loadPat" -#@ } -#@ -* { -#@ return -code error "unknown flag $flag: should be\n$usage" -#@ } -#@ default { -#@ # done with the flags -#@ break -#@ } -#@ } -#@ } -#@ -#@ set dir [lindex $args $idx] -#@ set patternList [lrange $args [expr {$idx + 1}] end] -#@ if {![llength $patternList]} { -#@ set patternList [list "*.tcl" "*[info sharedlibextension]"] -#@ } -#@ -#@ try { -#@ set fileList [glob -directory $dir -tails -types {r f} -- {*}$patternList] -#@ } on error {msg opt} { -#@ return -options $opt $msg -#@ } -#@ foreach file $fileList { -#@ # For each file, figure out what commands and packages it provides. -#@ # To do this, create a child interpreter, load the file into the -#@ # interpreter, and get a list of the new commands and packages that -#@ # are defined. -#@ -#@ if {$file eq "pkgIndex.tcl"} { -#@ continue -#@ } -#@ -#@ set c [interp create] -#@ -#@ # Load into the child any packages currently loaded in the parent -#@ # interpreter that match the -load pattern. -#@ -#@ if {$loadPat ne ""} { -#@ if {$doVerbose} { -#@ tclLog "currently loaded packages: '[info loaded]'" -#@ tclLog "trying to load all packages matching $loadPat" -#@ } -#@ if {![llength [info loaded]]} { -#@ tclLog "warning: no packages are currently loaded, nothing" -#@ tclLog "can possibly match '$loadPat'" -#@ } -#@ } -#@ foreach pkg [info loaded] { -#@ if {![string match -nocase $loadPat [lindex $pkg 1]]} { -#@ continue -#@ } -#@ if {$doVerbose} { -#@ tclLog "package [lindex $pkg 1] matches '$loadPat'" -#@ } -#@ try { -#@ load [lindex $pkg 0] [lindex $pkg 1] $c -#@ } on error err { -#@ if {$doVerbose} { -#@ tclLog "warning: load [lindex $pkg 0] [lindex $pkg 1]\nfailed with: $err" -#@ } -#@ } on ok {} { -#@ if {$doVerbose} { -#@ tclLog "loaded [lindex $pkg 0] [lindex $pkg 1]" -#@ } -#@ } -#@ if {[lindex $pkg 1] eq "Tk"} { -#@ # Withdraw . if Tk was loaded, to avoid showing a window. -#@ $c eval [list wm withdraw .] -#@ } -#@ } -#@ -#@ $c eval { -#@ # Stub out the package command so packages can require other -#@ # packages. -#@ -#@ rename package __package_orig -#@ proc package {what args} { -#@ switch -- $what { -#@ require { -#@ return; # Ignore transitive requires -#@ } -#@ default { -#@ __package_orig $what {*}$args -#@ } -#@ } -#@ } -#@ proc tclPkgUnknown args {} -#@ package unknown tclPkgUnknown -#@ -#@ # Stub out the unknown command so package can call into each other -#@ # during their initialilzation. -#@ -#@ proc unknown {args} {} -#@ -#@ # Stub out the auto_import mechanism -#@ -#@ proc auto_import {args} {} -#@ -#@ # reserve the ::tcl namespace for support procs and temporary -#@ # variables. This might make it awkward to generate a -#@ # pkgIndex.tcl file for the ::tcl namespace. -#@ -#@ namespace eval ::tcl { -#@ variable dir ;# Current directory being processed -#@ variable file ;# Current file being processed -#@ variable direct ;# -direct flag value -#@ variable x ;# Loop variable -#@ variable debug ;# For debugging -#@ variable type ;# "load" or "source", for -direct -#@ variable namespaces ;# Existing namespaces (e.g., ::tcl) -#@ variable packages ;# Existing packages (e.g., Tcl) -#@ variable origCmds ;# Existing commands -#@ variable newCmds ;# Newly created commands -#@ variable newPkgs {} ;# Newly created packages -#@ } -#@ } -#@ -#@ $c eval [list set ::tcl::dir $dir] -#@ $c eval [list set ::tcl::file $file] -#@ $c eval [list set ::tcl::direct $direct] -#@ -#@ # Download needed procedures into the slave because we've just deleted -#@ # the unknown procedure. This doesn't handle procedures with default -#@ # arguments. -#@ -#@ foreach p {::tcl::Pkg::CompareExtension} { -#@ $c eval [list namespace eval [namespace qualifiers $p] {}] -#@ $c eval [list proc $p [info args $p] [info body $p]] -#@ } -#@ -#@ try { -#@ $c eval { -#@ set ::tcl::debug "loading or sourcing" -#@ -#@ # we need to track command defined by each package even in the -#@ # -direct case, because they are needed internally by the -#@ # "partial pkgIndex.tcl" step above. -#@ -#@ proc ::tcl::GetAllNamespaces {{root ::}} { -#@ set list $root -#@ foreach ns [namespace children $root] { -#@ lappend list {*}[::tcl::GetAllNamespaces $ns] -#@ } -#@ return $list -#@ } -#@ -#@ # init the list of existing namespaces, packages, commands -#@ -#@ foreach ::tcl::x [::tcl::GetAllNamespaces] { -#@ set ::tcl::namespaces($::tcl::x) 1 -#@ } -#@ foreach ::tcl::x [package names] { -#@ if {[package provide $::tcl::x] ne ""} { -#@ set ::tcl::packages($::tcl::x) 1 -#@ } -#@ } -#@ set ::tcl::origCmds [info commands] -#@ -#@ # Try to load the file if it has the shared library extension, -#@ # otherwise source it. It's important not to try to load -#@ # files that aren't shared libraries, because on some systems -#@ # (like SunOS) the loader will abort the whole application -#@ # when it gets an error. -#@ -#@ if {[::tcl::Pkg::CompareExtension $::tcl::file [info sharedlibextension]]} { -#@ # The "file join ." command below is necessary. Without -#@ # it, if the file name has no \'s and we're on UNIX, the -#@ # load command will invoke the LD_LIBRARY_PATH search -#@ # mechanism, which could cause the wrong file to be used. -#@ -#@ set ::tcl::debug loading -#@ load [file join $::tcl::dir $::tcl::file] -#@ set ::tcl::type load -#@ } else { -#@ set ::tcl::debug sourcing -#@ source [file join $::tcl::dir $::tcl::file] -#@ set ::tcl::type source -#@ } -#@ -#@ # As a performance optimization, if we are creating direct -#@ # load packages, don't bother figuring out the set of commands -#@ # created by the new packages. We only need that list for -#@ # setting up the autoloading used in the non-direct case. -#@ if {!$::tcl::direct} { -#@ # See what new namespaces appeared, and import commands -#@ # from them. Only exported commands go into the index. -#@ -#@ foreach ::tcl::x [::tcl::GetAllNamespaces] { -#@ if {![info exists ::tcl::namespaces($::tcl::x)]} { -#@ namespace import -force ${::tcl::x}::* -#@ } -#@ -#@ # Figure out what commands appeared -#@ -#@ foreach ::tcl::x [info commands] { -#@ set ::tcl::newCmds($::tcl::x) 1 -#@ } -#@ foreach ::tcl::x $::tcl::origCmds { -#@ unset -nocomplain ::tcl::newCmds($::tcl::x) -#@ } -#@ foreach ::tcl::x [array names ::tcl::newCmds] { -#@ # determine which namespace a command comes from -#@ -#@ set ::tcl::abs [namespace origin $::tcl::x] -#@ -#@ # special case so that global names have no -#@ # leading ::, this is required by the unknown -#@ # command -#@ -#@ set ::tcl::abs [lindex [auto_qualify $::tcl::abs ::] 0] -#@ -#@ if {$::tcl::x ne $::tcl::abs} { -#@ # Name changed during qualification -#@ -#@ set ::tcl::newCmds($::tcl::abs) 1 -#@ unset ::tcl::newCmds($::tcl::x) -#@ } -#@ } -#@ } -#@ } -#@ -#@ # Look through the packages that appeared, and if there is a -#@ # version provided, then record it -#@ -#@ foreach ::tcl::x [package names] { -#@ if {[package provide $::tcl::x] ne "" -#@ && ![info exists ::tcl::packages($::tcl::x)]} { -#@ lappend ::tcl::newPkgs [list $::tcl::x [package provide $::tcl::x]] -#@ } -#@ } -#@ } -#@ } on error msg { -#@ set what [$c eval set ::tcl::debug] -#@ if {$doVerbose} { -#@ tclLog "warning: error while $what $file: $msg" -#@ } -#@ } on ok {} { -#@ set what [$c eval set ::tcl::debug] -#@ if {$doVerbose} { -#@ tclLog "successful $what of $file" -#@ } -#@ set type [$c eval set ::tcl::type] -#@ set cmds [lsort [$c eval array names ::tcl::newCmds]] -#@ set pkgs [$c eval set ::tcl::newPkgs] -#@ if {$doVerbose} { -#@ if {!$direct} { -#@ tclLog "commands provided were $cmds" -#@ } -#@ tclLog "packages provided were $pkgs" -#@ } -#@ if {[llength $pkgs] > 1} { -#@ tclLog "warning: \"$file\" provides more than one package ($pkgs)" -#@ } -#@ foreach pkg $pkgs { -#@ # cmds is empty/not used in the direct case -#@ lappend files($pkg) [list $file $type $cmds] -#@ } -#@ -#@ if {$doVerbose} { -#@ tclLog "processed $file" -#@ } -#@ } -#@ interp delete $c -#@ } -#@ -#@ append index "# Tcl package index file, version 1.1\n" -#@ append index "# This file is generated by the \"pkg_mkIndex$more\" command\n" -#@ append index "# and sourced either when an application starts up or\n" -#@ append index "# by a \"package unknown\" script. It invokes the\n" -#@ append index "# \"package ifneeded\" command to set up package-related\n" -#@ append index "# information so that packages will be loaded automatically\n" -#@ append index "# in response to \"package require\" commands. When this\n" -#@ append index "# script is sourced, the variable \$dir must contain the\n" -#@ append index "# full path name of this file's directory.\n" -#@ -#@ foreach pkg [lsort [array names files]] { -#@ set cmd {} -#@ lassign $pkg name version -#@ lappend cmd ::tcl::Pkg::Create -name $name -version $version -#@ foreach spec [lsort -index 0 $files($pkg)] { -#@ foreach {file type procs} $spec { -#@ if {$direct} { -#@ set procs {} -#@ } -#@ lappend cmd "-$type" [list $file $procs] -#@ } -#@ } -#@ append index "\n[eval $cmd]" -#@ } -#@ -#@ set f [open [file join $dir pkgIndex.tcl] w] -#@ puts $f $index -#@ close $f -#@ } -#@ -#@ # tclPkgSetup -- -#@ # This is a utility procedure use by pkgIndex.tcl files. It is invoked as -#@ # part of a "package ifneeded" script. It calls "package provide" to indicate -#@ # that a package is available, then sets entries in the auto_index array so -#@ # that the package's files will be auto-loaded when the commands are used. -#@ # -#@ # Arguments: -#@ # dir - Directory containing all the files for this package. -#@ # pkg - Name of the package (no version number). -#@ # version - Version number for the package, such as 2.1.3. -#@ # files - List of files that constitute the package. Each -#@ # element is a sub-list with three elements. The first -#@ # is the name of a file relative to $dir, the second is -#@ # "load" or "source", indicating whether the file is a -#@ # loadable binary or a script to source, and the third -#@ # is a list of commands defined by this file. -#@ -#@ proc tclPkgSetup {dir pkg version files} { -#@ global auto_index -#@ -#@ package provide $pkg $version -#@ foreach fileInfo $files { -#@ set f [lindex $fileInfo 0] -#@ set type [lindex $fileInfo 1] -#@ foreach cmd [lindex $fileInfo 2] { -#@ if {$type eq "load"} { -#@ set auto_index($cmd) [list load [file join $dir $f] $pkg] -#@ } else { -#@ set auto_index($cmd) [list source [file join $dir $f]] -#@ } -#@ } -#@ } -#@ } -#@ -#@ # tclPkgUnknown -- -#@ # This procedure provides the default for the "package unknown" function. It -#@ # is invoked when a package that's needed can't be found. It scans the -#@ # auto_path directories and their immediate children looking for pkgIndex.tcl -#@ # files and sources any such files that are found to setup the package -#@ # database. As it searches, it will recognize changes to the auto_path and -#@ # scan any new directories. -#@ # -#@ # Arguments: -#@ # name - Name of desired package. Not used. -#@ # version - Version of desired package. Not used. -#@ # exact - Either "-exact" or omitted. Not used. -#@ -#@ proc tclPkgUnknown {name args} { -#@ global auto_path env -#@ -#@ if {![info exists auto_path]} { -#@ return -#@ } -#@ # Cache the auto_path, because it may change while we run through the -#@ # first set of pkgIndex.tcl files -#@ set old_path [set use_path $auto_path] -#@ while {[llength $use_path]} { -#@ set dir [lindex $use_path end] -#@ -#@ # Make sure we only scan each directory one time. -#@ if {[info exists tclSeenPath($dir)]} { -#@ set use_path [lrange $use_path 0 end-1] -#@ continue -#@ } -#@ set tclSeenPath($dir) 1 -#@ -#@ # we can't use glob in safe interps, so enclose the following in a -#@ # catch statement, where we get the pkgIndex files out of the -#@ # subdirectories -#@ catch { -#@ foreach file [glob -directory $dir -join -nocomplain * pkgIndex.tcl] { -#@ set dir [file dirname $file] -#@ if {![info exists procdDirs($dir)]} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ } -#@ set dir [lindex $use_path end] -#@ if {![info exists procdDirs($dir)]} { -#@ set file [file join $dir pkgIndex.tcl] -#@ # safe interps usually don't have "file exists", -#@ if {([interp issafe] || [file exists $file])} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ -#@ set use_path [lrange $use_path 0 end-1] -#@ -#@ # Check whether any of the index scripts we [source]d above set a new -#@ # value for $::auto_path. If so, then find any new directories on the -#@ # $::auto_path, and lappend them to the $use_path we are working from. -#@ # This gives index scripts the (arguably unwise) power to expand the -#@ # index script search path while the search is in progress. -#@ set index 0 -#@ if {[llength $old_path] == [llength $auto_path]} { -#@ foreach dir $auto_path old $old_path { -#@ if {$dir ne $old} { -#@ # This entry in $::auto_path has changed. -#@ break -#@ } -#@ incr index -#@ } -#@ } -#@ -#@ # $index now points to the first element of $auto_path that has -#@ # changed, or the beginning if $auto_path has changed length Scan the -#@ # new elements of $auto_path for directories to add to $use_path. -#@ # Don't add directories we've already seen, or ones already on the -#@ # $use_path. -#@ foreach dir [lrange $auto_path $index end] { -#@ if {![info exists tclSeenPath($dir)] && ($dir ni $use_path)} { -#@ lappend use_path $dir -#@ } -#@ } -#@ set old_path $auto_path -#@ } -#@ } -#@ -#@ # tcl::MacOSXPkgUnknown -- -#@ # This procedure extends the "package unknown" function for MacOSX. It scans -#@ # the Resources/Scripts directories of the immediate children of the auto_path -#@ # directories for pkgIndex files. -#@ # -#@ # Arguments: -#@ # original - original [package unknown] procedure -#@ # name - Name of desired package. Not used. -#@ # version - Version of desired package. Not used. -#@ # exact - Either "-exact" or omitted. Not used. -#@ -#@ proc tcl::MacOSXPkgUnknown {original name args} { -#@ # First do the cross-platform default search -#@ uplevel 1 $original [linsert $args 0 $name] -#@ -#@ # Now do MacOSX specific searching -#@ global auto_path -#@ -#@ if {![info exists auto_path]} { -#@ return -#@ } -#@ # Cache the auto_path, because it may change while we run through the -#@ # first set of pkgIndex.tcl files -#@ set old_path [set use_path $auto_path] -#@ while {[llength $use_path]} { -#@ set dir [lindex $use_path end] -#@ -#@ # Make sure we only scan each directory one time. -#@ if {[info exists tclSeenPath($dir)]} { -#@ set use_path [lrange $use_path 0 end-1] -#@ continue -#@ } -#@ set tclSeenPath($dir) 1 -#@ -#@ # get the pkgIndex files out of the subdirectories -#@ foreach file [glob -directory $dir -join -nocomplain * Resources Scripts pkgIndex.tcl] { -#@ set dir [file dirname $file] -#@ if {![info exists procdDirs($dir)]} { -#@ try { -#@ source $file -#@ } trap {POSIX EACCES} {} { -#@ # $file was not readable; silently ignore -#@ continue -#@ } on error msg { -#@ tclLog "error reading package index file $file: $msg" -#@ } on ok {} { -#@ set procdDirs($dir) 1 -#@ } -#@ } -#@ } -#@ set use_path [lrange $use_path 0 end-1] -#@ -#@ # Check whether any of the index scripts we [source]d above set a new -#@ # value for $::auto_path. If so, then find any new directories on the -#@ # $::auto_path, and lappend them to the $use_path we are working from. -#@ # This gives index scripts the (arguably unwise) power to expand the -#@ # index script search path while the search is in progress. -#@ set index 0 -#@ if {[llength $old_path] == [llength $auto_path]} { -#@ foreach dir $auto_path old $old_path { -#@ if {$dir ne $old} { -#@ # This entry in $::auto_path has changed. -#@ break -#@ } -#@ incr index -#@ } -#@ } -#@ -#@ # $index now points to the first element of $auto_path that has -#@ # changed, or the beginning if $auto_path has changed length Scan the -#@ # new elements of $auto_path for directories to add to $use_path. -#@ # Don't add directories we've already seen, or ones already on the -#@ # $use_path. -#@ foreach dir [lrange $auto_path $index end] { -#@ if {![info exists tclSeenPath($dir)] && ($dir ni $use_path)} { -#@ lappend use_path $dir -#@ } -#@ } -#@ set old_path $auto_path -#@ } -#@ } -#@ -#@ # ::tcl::Pkg::Create -- -#@ # -#@ # Given a package specification generate a "package ifneeded" statement -#@ # for the package, suitable for inclusion in a pkgIndex.tcl file. -#@ # -#@ # Arguments: -#@ # args arguments used by the Create function: -#@ # -name packageName -#@ # -version packageVersion -#@ # -load {filename ?{procs}?} -#@ # ... -#@ # -source {filename ?{procs}?} -#@ # ... -#@ # -#@ # Any number of -load and -source parameters may be -#@ # specified, so long as there is at least one -load or -#@ # -source parameter. If the procs component of a module -#@ # specifier is left off, that module will be set up for -#@ # direct loading; otherwise, it will be set up for lazy -#@ # loading. If both -source and -load are specified, the -#@ # -load'ed files will be loaded first, followed by the -#@ # -source'd files. -#@ # -#@ # Results: -#@ # An appropriate "package ifneeded" statement for the package. -#@ -#@ proc ::tcl::Pkg::Create {args} { -#@ append err(usage) "[lindex [info level 0] 0] " -#@ append err(usage) "-name packageName -version packageVersion" -#@ append err(usage) "?-load {filename ?{procs}?}? ... " -#@ append err(usage) "?-source {filename ?{procs}?}? ..." -#@ -#@ set err(wrongNumArgs) "wrong # args: should be \"$err(usage)\"" -#@ set err(valueMissing) "value for \"%s\" missing: should be \"$err(usage)\"" -#@ set err(unknownOpt) "unknown option \"%s\": should be \"$err(usage)\"" -#@ set err(noLoadOrSource) "at least one of -load and -source must be given" -#@ -#@ # process arguments -#@ set len [llength $args] -#@ if {$len < 6} { -#@ error $err(wrongNumArgs) -#@ } -#@ -#@ # Initialize parameters -#@ array set opts {-name {} -version {} -source {} -load {}} -#@ -#@ # process parameters -#@ for {set i 0} {$i < $len} {incr i} { -#@ set flag [lindex $args $i] -#@ incr i -#@ switch -glob -- $flag { -#@ "-name" - -#@ "-version" { -#@ if {$i >= $len} { -#@ error [format $err(valueMissing) $flag] -#@ } -#@ set opts($flag) [lindex $args $i] -#@ } -#@ "-source" - -#@ "-load" { -#@ if {$i >= $len} { -#@ error [format $err(valueMissing) $flag] -#@ } -#@ lappend opts($flag) [lindex $args $i] -#@ } -#@ default { -#@ error [format $err(unknownOpt) [lindex $args $i]] -#@ } -#@ } -#@ } -#@ -#@ # Validate the parameters -#@ if {![llength $opts(-name)]} { -#@ error [format $err(valueMissing) "-name"] -#@ } -#@ if {![llength $opts(-version)]} { -#@ error [format $err(valueMissing) "-version"] -#@ } -#@ -#@ if {!([llength $opts(-source)] || [llength $opts(-load)])} { -#@ error $err(noLoadOrSource) -#@ } -#@ -#@ # OK, now everything is good. Generate the package ifneeded statment. -#@ set cmdline "package ifneeded $opts(-name) $opts(-version) " -#@ -#@ set cmdList {} -#@ set lazyFileList {} -#@ -#@ # Handle -load and -source specs -#@ foreach key {load source} { -#@ foreach filespec $opts(-$key) { -#@ lassign $filespec filename proclist -#@ -#@ if { [llength $proclist] == 0 } { -#@ set cmd "\[list $key \[file join \$dir [list $filename]\]\]" -#@ lappend cmdList $cmd -#@ } else { -#@ lappend lazyFileList [list $filename $key $proclist] -#@ } -#@ } -#@ } -#@ -#@ if {[llength $lazyFileList]} { -#@ lappend cmdList "\[list tclPkgSetup \$dir $opts(-name) $opts(-version) [list $lazyFileList]\]" -#@ } -#@ append cmdline [join $cmdList "\\n"] -#@ return $cmdline -#@ } -#@ -#@ interp alias {} ::pkg::create {} ::tcl::Pkg::Create -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/package.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/pkgIndex.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ package ifneeded cae 1.0 [list source [file join $dir syn.tcl]] -#@ package ifneeded cae::utils 1.0 [list source [file join $dir utils utils.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/iwidgets4.1/pkgIndex.tcl - -#@ # Tcl package index file -#@ package ifneeded iwidgets 4.1 " -#@ package require itk 4 -#@ namespace eval ::iwidgets { -#@ namespace export * -#@ variable library [file dirname [info script]] -#@ variable version 4.1 -#@ } -#@ source [file join $dir colors.itcl] -#@ source [file join $dir roman.itcl] -#@ source [file join $dir buttonbox.itk] -#@ source [file join $dir calendar.itk] -#@ source [file join $dir canvasprintbox.itk] -#@ source [file join $dir shell.itk] -#@ source [file join $dir dialogshell.itk] -#@ source [file join $dir dialog.itk] -#@ source [file join $dir canvasprintdialog.itk] -#@ source [file join $dir labeledframe.itk] -#@ source [file join $dir checkbox.itk] -#@ source [file join $dir labeledwidget.itk] -#@ source [file join $dir entryfield.itk] -#@ source [file join $dir combobox.itk] -#@ source [file join $dir datefield.itk] -#@ source [file join $dir dateentry.itk] -#@ source [file join $dir disjointlistbox.itk] -#@ source [file join $dir extbutton.itk] -#@ source [file join $dir extfileselectionbox.itk] -#@ source [file join $dir extfileselectiondialog.itk] -#@ source [file join $dir feedback.itk] -#@ source [file join $dir fileselectionbox.itk] -#@ source [file join $dir fileselectiondialog.itk] -#@ source [file join $dir finddialog.itk] -#@ source [file join $dir scrolledwidget.itk] -#@ source [file join $dir hierarchy.itk] -#@ source [file join $dir hyperhelp.itk] -#@ source [file join $dir mainwindow.itk] -#@ source [file join $dir menubar.itk] -#@ source [file join $dir messagebox.itk] -#@ source [file join $dir messagedialog.itk] -#@ source [file join $dir notebook.itk] -#@ source [file join $dir optionmenu.itk] -#@ source [file join $dir panedwindow.itk] -#@ source [file join $dir pane.itk] -#@ source [file join $dir promptdialog.itk] -#@ source [file join $dir pushbutton.itk] -#@ source [file join $dir radiobox.itk] -#@ source [file join $dir regexpfield.itk] -#@ source [file join $dir scrolledcanvas.itk] -#@ source [file join $dir scrolledframe.itk] -#@ source [file join $dir scrolledtext.itk] -#@ source [file join $dir scrolledhtml.itk] -#@ source [file join $dir scrolledlistbox.itk] -#@ source [file join $dir selectionbox.itk] -#@ source [file join $dir selectiondialog.itk] -#@ source [file join $dir spindate.itk] -#@ source [file join $dir spinner.itk] -#@ source [file join $dir spinint.itk] -#@ source [file join $dir spintime.itk] -#@ source [file join $dir tabnotebook.itk] -#@ source [file join $dir tabset.itk] -#@ source [file join $dir timefield.itk] -#@ source [file join $dir timeentry.itk] -#@ source [file join $dir toolbar.itk] -#@ source [file join $dir watch.itk] -#@ package provide iwidgets 4.1 -#@ " -#@ -#@ package ifneeded Iwidgets 4.1 " -#@ package require iwidgets 4.1 -#@ package provide Iwidgets 4.1 -#@ " -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/iwidgets4.1/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTclPro/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsTclPro 1.0 [list source [file join $dir snpsTclPro.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTclPro/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTest/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsTest 1.0 [list source [file join $dir snpsTest.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsTest/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsUtils/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded snpsUtils 1.0 [list source [file join $dir snpsUtils.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/snpsUtils/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/pkgIndex.tcl - -#@ package ifneeded Itcl 3.4 {load {} Itcl} -#@ package ifneeded tbcload 1.7 {load {} tbcload} -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/snps_tcl/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/reg/pkgIndex.tcl - -#@ if {([info commands ::tcl::pkgconfig] eq "") -#@ || ([info sharedlibextension] ne ".dll")} return -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/reg/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/dde/pkgIndex.tcl - -#@ if {([info commands ::tcl::pkgconfig] eq "") -#@ || ([info sharedlibextension] ne ".dll")} return -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/dde/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/platform/pkgIndex.tcl - -#@ package ifneeded platform 1.0.13 [list source [file join $dir platform.tcl]] -#@ package ifneeded platform::shell 1.1.4 [list source [file join $dir shell.tcl]] -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/platform/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tcltest/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ if {![package vsatisfies [package provide Tcl] 8.5]} {return} -#@ package ifneeded tcltest 2.3.8 [list source [file join $dir tcltest.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/tcltest/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http/pkgIndex.tcl - -#@ if {![package vsatisfies [package provide Tcl] 8.6]} {return} -#@ package ifneeded http 2.8.8 [list tclPkgSetup $dir http 2.8.8 {{http.tcl source {::http::config ::http::formatQuery ::http::geturl ::http::reset ::http::wait ::http::register ::http::unregister ::http::mapReply}}}] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/msgcat/pkgIndex.tcl - -#@ if {![package vsatisfies [package provide Tcl] 8.5]} {return} -#@ package ifneeded msgcat 1.5.2 [list source [file join $dir msgcat.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/msgcat/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http1.0/pkgIndex.tcl - -#@ # Tcl package index file, version 1.0 -#@ # This file is generated by the "pkg_mkIndex" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ package ifneeded http 1.0 [list tclPkgSetup $dir http 1.0 {{http.tcl source {httpCopyDone httpCopyStart httpEof httpEvent httpFinish httpMapReply httpProxyRequired http_code http_config http_data http_formatQuery http_get http_reset http_size http_status http_wait}}}] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/http1.0/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/opt/pkgIndex.tcl - -#@ # Tcl package index file, version 1.1 -#@ # This file is generated by the "pkg_mkIndex -direct" command -#@ # and sourced either when an application starts up or -#@ # by a "package unknown" script. It invokes the -#@ # "package ifneeded" command to set up package-related -#@ # information so that packages will be loaded automatically -#@ # in response to "package require" commands. When this -#@ # script is sourced, the variable $dir must contain the -#@ # full path name of this file's directory. -#@ -#@ if {![package vsatisfies [package provide Tcl] 8.2]} {return} -#@ package ifneeded opt 0.4.6 [list source [file join $dir optparse.tcl]] -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/tcllib/lib/tcl8.6/opt/pkgIndex.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/syn.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ # primary file of syn package -#@ -#@ # require all the sub-packages (if any) -#@ -#@ # name of the provided package -#@ -#@ package provide cae 1.0 -#@ -#@ # create command group after loading sub packages -#@ # because last group is listed first by "help" -#@ -#@ create_command_group "syn" -info "synthesis utilities" -#@ -#@ namespace eval ::cae { -#@ variable selfdir [file dirname [info script]] -#@ variable scripts [list auto_path_groups.tcl ] -#@ variable script -#@ } -#@ -#@ # source encrypted version if available -#@ # encrypted commands must use "define_proc_attributes -hide_body" -#@ -#@ foreach ::cae::script ${::cae::scripts} { -#@ if { [file exists ${::cae::selfdir}/${::cae::script}.e] } { -#@ source ${::cae::selfdir}/${::cae::script}.e -#@ } else { -#@ source ${::cae::selfdir}/${::cae::script} -#@ } -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/auto_path_groups.tcl - -#@ # Copyright (c) 2016-2017 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ package require cae::utils -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/utils/utils.tcl - -#@ # Copyright (c) 2016 Synopsys, Inc. This Synopsys software and all -#@ # associated documentation are proprietary to Synopsys, Inc. and may -#@ # only be used pursuant to the terms and conditions of a written -#@ # license agreement with Synopsys, Inc. All other use, reproduction, -#@ # modification, or distribution of the Synopsys software or the -#@ # associated documentation is strictly prohibited. -#@ -#@ # primary file of cae::utils package -#@ -#@ # name of the provided package -#@ -#@ package provide cae::utils 1.0 -#@ -#@ namespace eval ::cae::utils { -#@ } -#@ -#@ proc ::cae::utils::msg { type s } { -#@ switch -glob -- ${type} { -#@ i* { return "INFO: ${s}" } -#@ w* { return "WARNING: ${s}" } -#@ e* { return "ERROR: ${s}" } -#@ } -#@ return -#@ } -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/utils/utils.tcl - -#@ -#@ namespace eval ::cae { -#@ -#@ # note: check if these are all necessary -#@ variable auto_path_groups_messages {ATTR-3 OPT-806 OPT-774 UID-101 TIM-134 TIM-99 OPT-806 MWUI-203 MW-212 TIM-112} -#@ -#@ # default prefix for path groups -#@ variable auto_path_groups_prefix synopsys_pg_ -#@ # default slack for path groups -#@ variable auto_path_groups_slack 0.0 -#@ # default max for path groups -#@ variable auto_path_groups_max 0 -#@ # default verbosity -#@ variable auto_path_groups_verbose false -#@ # default priority -#@ variable auto_path_groups_priority 1 -#@ # default min_regs_per_hierarchy -#@ variable auto_path_groups_min_regs_per_hierarchy 10 -#@ # registers path group suffix -#@ variable auto_path_groups_reg_suffix to_regs_ -#@ # macro path group suffix -#@ variable auto_path_groups_to_macro_suffix to_macros_ -#@ # macro path group suffix -#@ variable auto_path_groups_from_macro_suffix from_macros_ -#@ # ICG path group suffix -#@ variable auto_path_groups_icg_suffix to_ICGs -#@ # input path group suffix -#@ variable auto_path_groups_input_suffix inputs -#@ # output path group suffix -#@ variable auto_path_groups_output_suffix outputs -#@ # feedthrough path group suffix -#@ variable auto_path_groups_feedthrough_suffix feedthrough -#@ # user path groups -#@ variable auto_path_groups_user_path_groups_file auto_path_groups.user_path_groups.tcl -#@ } -#@ -#@ proc create_auto_path_groups { args } { -#@ variable ::cae::auto_path_groups_messages -#@ variable ::cae::auto_path_groups_prefix -#@ variable ::cae::auto_path_groups_slack -#@ variable ::cae::auto_path_groups_max -#@ variable ::cae::auto_path_groups_verbose -#@ variable ::cae::auto_path_groups_priority -#@ variable ::cae::auto_path_groups_min_regs_per_hierarchy -#@ variable ::cae::auto_path_groups_reg_suffix -#@ variable ::cae::auto_path_groups_to_macro_suffix -#@ variable ::cae::auto_path_groups_from_macro_suffix -#@ variable ::cae::auto_path_groups_icg_suffix -#@ variable ::cae::auto_path_groups_input_suffix -#@ variable ::cae::auto_path_groups_output_suffix -#@ variable ::cae::auto_path_groups_feedthrough_suffix -#@ variable ::cae::auto_path_groups_user_path_groups_file -#@ -#@ set options(-slack) ${auto_path_groups_slack} -#@ set options(-max) ${auto_path_groups_max} -#@ set options(-prefix) ${auto_path_groups_prefix} -#@ set options(-verbose) ${auto_path_groups_verbose} -#@ set options(-priority) ${auto_path_groups_priority} -#@ set options(-min_regs_per_hierarchy) ${auto_path_groups_min_regs_per_hierarchy} -#@ set options(-exclude) [list] -#@ set options(-user_path_groups_file) ${auto_path_groups_user_path_groups_file} -#@ -#@ parse_proc_arguments -args ${args} options -#@ -#@ if { [info exists options(-file)] } { -#@ if { [catch {open $options(-file) w} fileId] } { -#@ return -code error [::cae::utils::msg e ${fileId}] -#@ } -#@ } -#@ -#@ # save user path groups -#@ if { ![info exists options(-skip)] } { -#@ echo [::cae::utils::msg i "Saving user path groups to $options(-user_path_groups_file)..."] -#@ if { [file exist $options(-user_path_groups_file)] } { -#@ echo [::cae::utils::msg w "File $options(-user_path_groups_file) already exists and will be overwritten..."] -#@ } -#@ if { [catch {open "| grep \"^group_path\" > $options(-user_path_groups_file)" w} channelId] } { -#@ return -code error [::cae::utils::msg e ${channelId}] -#@ } -#@ redirect -channel ${channelId} { write_script -nosplit } -#@ set r [catch {close ${channelId}} msg] -#@ switch ${r} { -#@ 0 { echo [::cae::utils::msg i "User path groups saved"] } -#@ 1 { echo [::cae::utils::msg i "No user path groups to save"] } -#@ default { return -code error [::cae::utils::msg e ${msg}] } -#@ } -#@ } -#@ -#@ set total 0 -#@ -#@ suppress_message ${auto_path_groups_messages} -#@ switch -- $options(-mode) { -#@ "rtl" { -#@ # create one path group per hierarchy -#@ -#@ echo [::cae::utils::msg i "Collecting hierarchies without optimize_registers..."] -#@ set optimize_registers_cells [get_cells -hier -filter {is_hierarchical==true && optimize_registers==true}] -#@ if { $options(-verbose) } { -#@ set optimize_registers_cells_names [lsort [get_object_name ${optimize_registers_cells}]] -#@ echo [::cae::utils::msg i "cells with optimize_registers: ${optimize_registers_cells_names}"] -#@ } -#@ set optimize_registers_sub_cells {} -#@ foreach_in_collection cell ${optimize_registers_cells} { -#@ redirect -file /dev/null {current_instance ${cell}} -#@ append_to_collection optimize_registers_sub_cells [get_cells -hier -filter {is_hierarchical==true && (optimize_registers==false || undefined(optimize_registers))}] -#@ } -#@ redirect -file /dev/null {current_instance} -#@ if { $options(-verbose) } { -#@ set optimize_registers_sub_cells_names [lsort [get_object_name ${optimize_registers_sub_cells}]] -#@ echo [::cae::utils::msg i "sub-cells of cells with optimize_registers: ${optimize_registers_sub_cells_names}"] -#@ } -#@ set path_group_cells [get_cells -hier -filter {is_hierarchical==true && is_sequential==true && (optimize_registers==false || undefined(optimize_registers))}] -#@ set path_group_cells [remove_from_collection ${path_group_cells} ${optimize_registers_sub_cells}] -#@ -#@ echo [::cae::utils::msg i "Collected [sizeof_collection ${path_group_cells}] hierarchies without optimize_registers"] -#@ -#@ set path_group_names [lsort [get_object_name ${path_group_cells}]] -#@ -#@ if { $options(-verbose) } { -#@ echo [::cae::utils::msg i "cells for which path groups will be created:"] -#@ foreach path_group_name ${path_group_names} { -#@ echo [::cae::utils::msg i " ${path_group_name}"] -#@ } -#@ } -#@ -#@ echo [::cae::utils::msg i "Creating path groups for hierarchies without optimize_registers..."] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ set number_of_registers [sizeof_collection [get_cells ${path_group_name}/* -filter "is_hierarchical==false && is_sequential==true"]] -#@ if { ${number_of_registers} > $options(-min_regs_per_hierarchy) } { -#@ echo [::cae::utils::msg i "Number of sequential cells found in ${path_group_name} hierarchy: ${number_of_registers}"] -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells ${path_group_name}/* -filter \"is_hierarchical==false && is_sequential==true\"\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } else { -#@ echo [::cae::utils::msg i "Not enough sequential cells found in ${path_group_name} hierarchy (${number_of_registers}), skipping..."] -#@ } -#@ } -#@ echo [::cae::utils::msg i "Number of reg path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } -#@ "mapped" { -#@ # create one path group per hierarchy not meeting timing -#@ -#@ array unset fail -#@ echo [::cae::utils::msg i "Collecting hierarchies with timing violations..."] -#@ foreach_in_collection pin [all_registers -data_pins] { -#@ set slack [get_attribute ${pin} max_slack] -#@ if { ${slack} < $options(-slack) && ${slack} != "" } { -#@ set cell [get_cells -of_objects ${pin}] -#@ set full_name [get_attribute ${cell} full_name] -#@ set name [get_attribute ${cell} name] -#@ if {[string length ${full_name}] > [string length ${name}]} { -#@ set length [expr [string length ${full_name}] - [string length ${name}] - 1] -#@ set hierarchy [string range ${full_name} 0 [expr ${length} - 1]] -#@ } else { -#@ set hierarchy "" -#@ } -#@ if { ![info exists fail(${hierarchy})] || -#@ ([info exists fail(${hierarchy})] && ${slack} < $fail(${hierarchy})) } { -#@ set fail(${hierarchy}) ${slack} -#@ } -#@ } -#@ } -#@ echo [::cae::utils::msg i "Collected [array size fail] hierarchies with timing violations"] -#@ -#@ if { $options(-max) > 0 } { -#@ echo [::cae::utils::msg i "Keeping only $options(-max) hierarchies with worst timing violations"] -#@ set hierarchy_slack_list [lsort -stride 2 -index 1 -real -increasing [array get fail]] -#@ set hierarchy_slack_list [lrange ${hierarchy_slack_list} 0 [expr {2 * $options(-max) - 1}]] -#@ array unset fail -#@ array set fail ${hierarchy_slack_list} -#@ } -#@ -#@ set path_group_names [lsort [array names fail]] -#@ -#@ if { $options(-verbose) } { -#@ echo [::cae::utils::msg i "hierarchies for which path groups will be created:"] -#@ foreach path_group_name ${path_group_names} { -#@ echo [::cae::utils::msg i " ${path_group_name} $fail(${path_group_name})"] -#@ } -#@ } -#@ -#@ echo [::cae::utils::msg i "Creating path groups for hierarchies with timing violations..."] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ if { ${path_group_name} == "" } { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells * -filter {is_hierarchical==false && is_sequential==true}\] -priority $options(-priority)" -#@ } else { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_reg_suffix}${counter} -to \[get_cells ${path_group_name}/* -filter {is_hierarchical==false && is_sequential==true}\] -priority $options(-priority)" -#@ } -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } -#@ echo [::cae::utils::msg i "Number of reg path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ -#@ } -#@ -#@ } -#@ -#@ # macro path groups -#@ if { [lsearch $options(-exclude) macro] == -1} { -#@ echo [::cae::utils::msg i "Creating macro path groups..."] -#@ if { [shell_is_in_topographical_mode] } { -#@ #set macro_cells [all_macro_cells] -#@ set macro_cells [remove_from_collection [all_macro_cells] [get_cells -quiet -hier -all -filter "is_physical_only==true"]] -#@ } else { -#@ set macro_cells [get_cells -hier * -filter "is_macro_cell == true"] -#@ } -#@ if { [sizeof_collection ${macro_cells}] != 0 } { -#@ set path_group_names [get_object_name ${macro_cells}] -#@ set counter 0 -#@ foreach path_group_name ${path_group_names} { -#@ set command "group_path -name $options(-prefix)${auto_path_groups_to_macro_suffix}${counter} -to \[get_cells ${path_group_name}\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_from_macro_suffix}${counter} -from \[get_cells ${path_group_name}\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ } -#@ echo [::cae::utils::msg i "Number of macro path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } else { -#@ echo [::cae::utils::msg i "No macro found, skipping..."] -#@ } -#@ } -#@ -#@ # ICG path groups -#@ if { [lsearch $options(-exclude) ICG] == -1} { -#@ echo [::cae::utils::msg i "Creating ICG path groups..."] -#@ set all_icg_cells [get_cells -hier -filter "full_name=~*latch || full_name=~*u_clkgate && defined(clock_gating_integrated_cell)"] -#@ if { [sizeof_collection ${all_icg_cells}] } { -#@ set counter 0 -#@ set command "group_path -name $options(-prefix)${auto_path_groups_icg_suffix} -to \[get_cells -hier -filter \"full_name=~*latch || full_name=~*u_clkgate && defined(clock_gating_integrated_cell)\"\] -priority $options(-priority)" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ echo [::cae::utils::msg i "Number of ICG path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } else { -#@ echo [::cae::utils::msg i "No ICG found, skipping..."] -#@ } -#@ } -#@ -#@ # IO path groups -#@ if { [lsearch $options(-exclude) IO] == -1} { -#@ echo [::cae::utils::msg i "Creating IO path groups..."] -#@ set counter 0 -#@ set command "group_path -name $options(-prefix)${auto_path_groups_input_suffix} -from \[ remove_from_collection \[all_inputs\] \[get_ports \[get_attribute \[get_clocks -filter defined(sources)\] sources\]\] \]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_output_suffix} -to \[all_outputs\]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ set command "group_path -name $options(-prefix)${auto_path_groups_feedthrough_suffix} -from \[ remove_from_collection \[all_inputs\] \[get_ports \[get_attribute \[get_clocks -filter defined(sources)\] sources\]\] \] -to \[all_outputs\]" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ incr counter -#@ echo [::cae::utils::msg i "Number of IO path groups created: ${counter}"] -#@ set total [expr {${total} + ${counter}}] -#@ } -#@ -#@ unsuppress_message ${auto_path_groups_messages} -#@ -#@ echo [::cae::utils::msg i "Total number of path groups created: ${total}"] -#@ -#@ if { [info exists options(-file)] } { -#@ close ${fileId} -#@ } -#@ -#@ return -#@ } -#@ -#@ define_proc_attributes create_auto_path_groups -command_group syn -dont_abbrev -hide_body -info "Creates path groups for current design" -define_args { -#@ { -mode "creates path groups for unmapped/mapped netlist" mode one_of_string {required value_help {values {rtl mapped}}} } -#@ { -exclude "excludes specific path groups (IO ICG macro) (default: empty list)" list list {optional} } -#@ { -slack "slack value used to select hierarchy violating timing (default: 0.0) - mapped mode only" slack float optional } -#@ { -max "maximum number of paths groups (default: 0=unlimited) - mapped mode only" max int optional } -#@ { -min_regs_per_hierarchy "minimum number of registers per hierarchy (default: 10) - rtl mode only" min_regs int optional } -#@ { -prefix "path group name prefix (default: synopsys_pg_)" prefix string optional } -#@ { -file "file name to dump group_path commands" file_name string optional } -#@ { -verbose "verbose mode" "" boolean optional } -#@ { -user_path_groups_file "save user path groups to this file" file_name string optional } -#@ { -skip "do not save user path groups" "" boolean optional } -#@ } -#@ -#@ proc remove_auto_path_groups { args } { -#@ variable ::cae::auto_path_groups_messages -#@ variable ::cae::auto_path_groups_prefix -#@ variable ::cae::auto_path_groups_verbose -#@ variable ::cae::auto_path_groups_user_path_groups_file -#@ -#@ set options(-prefix) ${auto_path_groups_prefix} -#@ set options(-verbose) ${auto_path_groups_verbose} -#@ set options(-user_path_groups_file) ${auto_path_groups_user_path_groups_file} -#@ -#@ parse_proc_arguments -args ${args} options -#@ -#@ if { [info exists options(-file)] } { -#@ if {[catch {open $options(-file) w } fileId] } { -#@ return -code error [::cae::utils::msg e ${fileId}] -#@ } -#@ } -#@ -#@ suppress_message ${auto_path_groups_messages} -#@ set path_group_names [get_object_name [get_path_group -filter "full_name =~ $options(-prefix)*"]] -#@ foreach path_group_name ${path_group_names} { -#@ set command "remove_path_group ${path_group_name}" -#@ echo [::cae::utils::msg i ${command}] -#@ if { [info exists options(-file)] } { -#@ puts ${fileId} ${command} -#@ } -#@ eval ${command} -#@ } -#@ echo [::cae::utils::msg i "Number of path groups removed: [llength ${path_group_names}]"] -#@ unsuppress_message ${auto_path_groups_messages} -#@ -#@ if { [info exists options(-file)] } { -#@ close ${fileId} -#@ } -#@ -#@ # restore user path groups -#@ if { ![info exists options(-skip)] } { -#@ echo [::cae::utils::msg i "Restoring user path groups from $options(-user_path_groups_file)..."] -#@ if { [file exist $options(-user_path_groups_file)] } { -#@ if { [file size $options(-user_path_groups_file)] != 0} { -#@ source -continue_on_error $options(-user_path_groups_file) -#@ } else { -#@ echo [::cae::utils::msg i "No user path groups to restore"] -#@ } -#@ file delete -force $options(-user_path_groups_file) -#@ } else { -#@ echo [::cae::utils::msg w "File $options(-user_path_groups_file) doesn't exist"] -#@ } -#@ } -#@ -#@ return -#@ } -#@ -#@ define_proc_attributes remove_auto_path_groups -command_group syn -dont_abbrev -hide_body -info "Removes path groups for current design" -define_args { -#@ { -prefix "path group name prefix (default: synopsys_pg)" prefix string optional } -#@ { -file "file name to dump group_path commands" file_name string optional } -#@ { -verbose "verbose mode" "" boolean optional } -#@ { -user_path_groups_file "restore user path groups from this file" file_name string optional } -#@ { -skip "do not restore user path groups" "" boolean optional } -#@ } -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/auto_path_groups.tcl - -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lib/syn.tcl - -#@ -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ set sh_enable_line_editing "true" -#@ set sh_line_editing_mode "emacs" -#@ } -#@ -#@ if {$synopsys_program_name == "icc_shell"} { -#@ if {"$sh_output_log_file" == ""} { -#@ set sh_output_log_file "icc_output.txt" -#@ } -#@ -#@ ## the variable sh_redirect_progress_messages only makes it possible -#@ ## for some commands to redirect progress messages to the log file,thereby -#@ ## bypassing the console and reducing the volume of messages on the console. -#@ set sh_redirect_progress_messages true -#@ } -#@ -#@ -#@ # Suppress new variable messages for the following variables -#@ array set auto_index {} -#@ set auto_oldpath "" -#@ -#@ # Enable customer support banner on fatal -#@ if { $sh_arch == "linux" || $sh_arch == "amd64" || $sh_arch == "linux64" || $sh_arch == "suse32" || $sh_arch == "suse64" || $sh_arch == "sparcOS5" || $sh_arch == "sparc64" || $sh_arch == "x86sol32" || $sh_arch == "x86sol64" || $sh_arch == "rs6000" || $sh_arch == "aix64" } { -#@ setenv SYNOPSYS_TRACE "" -#@ } -#@ -#@ # -#@ # Load the procedures which make up part of the user interface. -#@ # -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source $synopsys_root/auxx/syn/.dc_procs.tcl -#@ } -#@ alias list_commands help -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_common_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_common_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the PrimeTime and DC -#@ # user interface. -#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: group_variable -#@ # -#@ # ABSTRACT: Add a variable to the specified variable group. -#@ # This command is typically used by the system -#@ # administrator only. -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code if the variable does not exist. -#@ # error code of the variable is already in the group. -#@ # -#@ # SYNTAX: group_variable group_name variable_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ -#@ proc group_variable { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ set var $resarr(variable_name) -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ set _Variable_Groups($group) "" -#@ } -#@ -#@ # Verify that var exists as a global variable -#@ -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ return -code error "Variable '$var' is not defined." -#@ } -#@ -#@ # Only add it if it's not already there -#@ -#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } { -#@ lappend _Variable_Groups($group) $var -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args { -#@ {group "Variable group name" group} -#@ {variable_name "Variable name" variable_name}} -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: print_variable_group -#@ # -#@ # ABSTRACT: Shows variables and their values defined in the given group. -#@ -#@ # -#@ # Below the proc is the command which creates the command -#@ # help information and semantic data for the argument. -#@ # -#@ # RETURNS: 1 if it is successful. -#@ # error code of the variable group does not exist. -#@ # -#@ # SYNTAX: print_variable_group group_name -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc print_variable_group { args } { -#@ global _Variable_Groups -#@ -#@ parse_proc_arguments -args $args resarr -#@ set group $resarr(group) -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set cmd "uplevel #0 \{printvar\}" -#@ return [eval $cmd] -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Print out each global variable in the list. To be totally bulletproof, -#@ # test that each variable in the group is still defined. If not, remove -#@ # it from the list. -#@ -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } else { -#@ # Print it. -#@ set cmd "uplevel #0 \{set $var\}" -#@ set val [eval $cmd] -#@ echo [format "%-25s = \"%s\"" $var $val] -#@ } -#@ } -#@ -#@ return 1 -#@ } -#@ -#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Groups -#@ # -#@ # ABSTRACT: Return a list of all variable groups. This command is hidden -#@ # and is used by Design Vision. -#@ # -#@ # RETURNS: Tcl list of all variable groups including group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Groups { } { -#@ global _Variable_Groups -#@ -#@ set groups [array names _Variable_Groups] -#@ append groups " all" -#@ return $groups -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group -#@ # -#@ # ABSTRACT: Return a list of all variables of a variable group. -#@ # It also works for pseudo group all. -#@ # -#@ # RETURNS: Tcl list of all variables of a variable group including -#@ # pseudo group all -#@ # -#@ # SYNTAX: _Variable_Groups_Get_Groups -#@ ############################################################################## -#@ # -#@ -#@ proc _Variable_Groups_Get_Variables_Of_Group { group } { -#@ global _Variable_Groups -#@ -#@ if { [string compare $group "all"] == 0 } { -#@ set itr [array startsearch _Variable_Groups] -#@ for { } { [array anymore _Variable_Groups $itr]} { } { -#@ set index [array nextelement _Variable_Groups $itr] -#@ append vars $_Variable_Groups($index) -#@ } -#@ array donesearch _Variable_Groups $itr -#@ return $vars -#@ } -#@ -#@ if { ![info exists _Variable_Groups($group)] } { -#@ return -code error "Variable group '$group' does not exist." -#@ } -#@ -#@ # Test if all variables in the list of variables are still defined. -#@ # Remove not existing variables. -#@ foreach var [lsort $_Variable_Groups($group)] { -#@ set cmd "uplevel #0 \{info exists $var\}" -#@ if { ![eval $cmd] } { -#@ # Remove it -#@ set n [lsearch $_Variable_Groups($group) $var] -#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n] -#@ } -#@ } -#@ return $_Variable_Groups($group) -#@ } -#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_common_procs.tcl - -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_procs.tcl - -#@ ############################################################################## -#@ # -#@ # -#@ # FILE: auxx/syn/.dc_procs.tcl -#@ # -#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl -#@ # user interface. -#@ # They are loaded by .synopsys_dc.setup. -#@ # -#@ ############################################################################## -#@ # -#@ # -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_verilog -#@ # -#@ # ABSTRACT: Emulate PT's read_verilog command in DC: -#@ # -#@ # Usage: read_verilog # Read one or more verilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command -#@ # sees user/hidden variables from the top level. Star 92970. -#@ # -#@ # Modified: Evan Rosser, 12/5/01. Support -netlist and -rtl flags. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ if { $synopsys_program_name != "icc_shell" } { -#@ proc read_verilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format verilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Verilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_sverilog -#@ # -#@ # ABSTRACT: Emulate PT's read_sverilog command in DC: -#@ # -#@ # Usage: read_sverilog # Read one or more systemverilog files -#@ # *[-hdl_compiler] (Use HDL Compiler (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # Modified: Yong Xiao, 01/31/2003: Copied from read_verilog to support -#@ # systemverilog input. -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_sverilog { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format sverilog %s %s [list %s]} [array names ra -rtl] [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_sverilog -info " Read one or more systemverilog files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural Verilog netlist reader" "" boolean optional} -#@ {-rtl "Use RTL Systemverilog compiler (Presto or HDLC)" "" boolean optional} -#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_vhdl -#@ # -#@ # ABSTRACT: Emulate PT's read_vhdl command in DC: -#@ # -#@ # Usage: read_vhdl # Read one or more vhdl files -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_vhdl { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format vhdl %s [list %s]} [array names ra -netlist] $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist "Use structural VHDL netlist reader" "" boolean optional} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_db -#@ # -#@ # ABSTRACT: Emulate PT's read_db command in DC: -#@ # -#@ # Usage: -#@ # read_db # Read one or more db files -#@ # *[-netlist_only] (Do not read any attributes from db (ignored)) -#@ # *[-library] (File is a library DB (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_db { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}} -#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_edif -#@ # -#@ # ABSTRACT: Emulate PT's read_edif command in DC: -#@ # -#@ # Usage: -#@ # read_edif # Read one or more edif files -#@ # *[-complete_language] (Use ptxr to read the file (ignored)) -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ proc read_edif { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}} -#@ } -#@ -#@ -#@ ############################################################################## -#@ # -#@ # -#@ # PROCEDURE: read_ddc -#@ # -#@ # ABSTRACT: Shorthand for "read_file -format ddc": -#@ # -#@ # Usage: -#@ # read_ddc # Read one or more ddc files -#@ # *[-scenarios] only read constraints for specified scenarios -#@ # *[-active_scenarios] only activate the specified scenarios -#@ # file_names (Files to read) -#@ # -#@ # -#@ ############################################################################## -#@ # -#@ -#@ proc read_ddc { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "read_file -format ddc" -#@ if { [ info exists ra(-scenarios) ] } { -#@ set cmd "$cmd -scenarios { $ra(-scenarios) }" -#@ } -#@ if { [ info exists ra(-active_scenarios) ] } { -#@ set cmd "$cmd -active_scenarios { $ra(-active_scenarios) }" -#@ } -#@ set cmd "$cmd { $ra(file_names) }" -#@ return [uplevel \#0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_ddc -info "Read one or more ddc files" -permanent -define_args { -#@ {file_names "Files to read" file_names list required} -#@ {-scenarios "list of scenarios to be read from ddc file" -#@ scenario_list list optional} -#@ {-active_scenarios "list of scenarios to be made active" -#@ active_scenario_list list optional}} -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: source_tcl_file -#@ # -#@ # ABSTRACT: generic procedure to source another tcl file -#@ # -#@ # Arguments: -#@ # filename tcl filename -#@ # dir directory to check for file -#@ # msg verbose message -#@ # verbose verbose mode -#@ # -#@ # Usage: -#@ # -#@ ############################################################################## -#@ # -#@ proc source_tcl_file { filename dir msg {verbose 1} } { -#@ set __qual_pref_file [file join $dir $filename] -#@ if {[file exists $__qual_pref_file]} { -#@ if { $verbose } { -#@ echo $msg $__qual_pref_file -#@ } -#@ # use catch to recover from errors in the pref file -#@ echo_trace "Sourcing " $__qual_pref_file -#@ # to speed up sourcing use read and eval -#@ set f [open $__qual_pref_file] -#@ if {[catch {namespace eval :: [read -nonewline $f]} __msg]} { -#@ echo Error: Error during sourcing of $__qual_pref_file -#@ if {$__msg != ""} { echo $__msg } -#@ # actually, it looks like $__msg is always null after -#@ # source fails -#@ } -#@ close $f -#@ } else { -#@ echo_trace "Info: File '" $__qual_pref_file "' does not exist!" -#@ } -#@ } -#@ define_proc_attributes source_tcl_file -hidden -#@ -#@ -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: echo_trace -#@ # -#@ # ABSTRACT: echo only in trace modus -#@ # -#@ ############################################################################## -#@ # -#@ proc echo_trace { args } { -#@ if { [info exists ::env(TCL_TRACE)] } { -#@ echo TRACE\> [join $args "" ] -#@ } -#@ } -#@ define_proc_attributes echo_trace -hidden -#@ -#@ ############################################################################# -#@ # -#@ # Following procedures added for PC write_script -#@ # -#@ # -#@ # -#@ ############################################################################ -#@ -#@ proc set_cell_restriction { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_attribute %s -type integer restrictions %s } $ra(cell) $ra(value)] -#@ return [uplevel #0 $cmd] -#@ -#@ } -#@ define_proc_attributes set_cell_restriction -hidden -define_args { {cell "cell_name" cell string required} {value "value" value string required} } -#@ -#@ -#@ proc set_cell_soft_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_soft_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ proc set_cell_hard_keepout {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {set_keepout_margin -type soft -outer {%d %d %d %d} [list %s] } $ra(llx) $ra(lly) $ra(urx) $ra(ury) $ra(objects)] -#@ return [uplevel #0 $cmd] -#@ -#@ -#@ } -#@ -#@ define_proc_attributes set_cell_hard_keepout -hidden -define_args { {llx "llx" llx float required} {lly "lly" lly float required} {urx "urx" urx float required} {ury "ury" ury float required} {objects "objects" objects list required} } -#@ -#@ set mw_use_pdb_lib_format false -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_milkyway -#@ # -#@ # ABSTRACT: wrapper around save_mw_cel to support original write_milkyway -#@ # interface -#@ # if { [info commands open_mw_cel] == "open_mw_cel" } {} -#@ # -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc write_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {save_mw_cel -as %s %s %s %s %s} $ra(-output) [array names ra -overwrite] [array names ra -create] [array names ra -all] [array names ra -dps]] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes write_milkyway -hidden -info " Saves the design as milkyway CEL" -define_args {{-output fileName "Name" string {optional}} {-overwrite "Overwrite the current version" "" boolean {optional}} {-create "Create from scratch" "" boolean {hidden optional}} {-all "Save all modified cells" "" boolean {hidden optional}} {-dps "Save internal DPS design" "" boolean {hidden optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: read_milkyway -#@ # -#@ # ABSTRACT: wrapper around open_mw_cel to support original read_milkyway -#@ # interface -#@ # MODIFIED: To support DPS in Galileo we need to pass the filtering -#@ # parameters to the DPS command. (Pankaj Goswami, Mar09 2005) -#@ # -#@ ############################################################################## -#@ -#@ proc read_milkyway args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {open_mw_cel %s} $ra() ] -#@ -#@ if {[info exists ra(-library)]} { -#@ set cmd [concat [concat $cmd " -library " ] " $ra(-library) "] -#@ } -#@ -#@ if {[info exists ra(-read_only)]} { -#@ lappend cmd {-readonly} -#@ } -#@ -#@ # DPS specific stuff -#@ set dps_cmd "vh_set_current_partition " -#@ set read_mw_with_dps_filter false -#@ -#@ if {[info exists ra(-vh_module_only)]} { -#@ append dps_cmd "-vh_module_only " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_include)]} { -#@ append dps_cmd [concat " -vh_include " " \{ $ra(-vh_include) \}"] -#@ append dps_cmd " " -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if {[info exists ra(-vh_exclude)]} { -#@ append dps_cmd [concat " -vh_exclude" " \{ $ra(-vh_exclude) \}"] -#@ set read_mw_with_dps_filter true -#@ } -#@ -#@ if { $read_mw_with_dps_filter == true } { -#@ # Call the DPS command to store the DPS filtering params. -#@ uplevel #0 $dps_cmd -#@ } else { -#@ # If there is no DPS filtering params, then we need to reset the -#@ # params which might have been stored from the provious command. -#@ append dps_cmd " -vh_reset_partition" -#@ uplevel #0 $dps_cmd -#@ } -#@ # End of DPS stuff -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes read_milkyway -hidden -info " Read milkyway CEL from disk" -define_args {{-library "library name" "lib_name" string {optional}} {-read_only "open design in read only mode" "" boolean {optional}} {-version "version number of the CEL" "number" string {optional}} {-vh_module_only "open design for DPS module only partition" "" boolean {hidden optional}} {-vh_include "list of designs to be included in the DPS partition" "include_designs" list {hidden optional}} {-vh_exclude "list of designs to be excluded in the DPS partition" "exclude_designs" list {hidden optional}} {"" fileName "CEL name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_technology_file -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ # HISTORY : 2009/6/21, yunz, support ALF reader in ICC -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || -#@ ([string match -nocase {*d[ce]_shell*} $synopsys_program_name] && [shell_is_mwlib_enabled]) } { -#@ -#@ proc set_mw_technology_file args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ set alf_file "" -#@ -#@ if {[info exists ra(-technology)] && [info exists ra(-plib)]} { -#@ echo "Error: the $ra(-technology) and $ra(-plib) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-technology)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-technology) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } elseif {[info exists ra(-plib)] && [info exists ra(-alf)]} { -#@ echo "Error: the $ra(-plib) and $ra(-alf) options are mutually exclusive." -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ -#@ set cmd [format {update_mw_lib -technology %s %s} $ra(-technology) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-alf)]} { -#@ -#@ set cmd [format {update_mw_lib %s} $ra() ] -#@ -#@ set cmd [concat [concat $cmd " -alf " ] " $ra(-alf) "] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_technology_file -hide_body -info " Set technology file for the library " -define_args {{-technology "Technology file name" "tech_file" string {optional}} {-alf "alf file name" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: rebuild_mw_lib -#@ # -#@ # ABSTRACT: wrapper around update_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc rebuild_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {update_mw_lib -rebuild %s} $ra() ] -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes rebuild_mw_lib -hide_body -info " Rebuild the library " -define_args {{"" "Library name" "libName" string {required}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: set_mw_lib_reference -#@ # -#@ # ABSTRACT: Procedure to set ref lib list or ref ctrl file -#@ # -#@ ############################################################################## -#@ -#@ proc set_mw_lib_reference args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [format {set_reference_control_file -reference_libraries {%s} %s} $ra(-mw_reference_library) $ra() ] -#@ } -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [format {set_reference_control_file -file %s %s} $ra(-reference_control_file) $ra() ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes set_mw_lib_reference -hide_body -info " Set reference for the library " -define_args {{-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {"" "Library name" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: create_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI create_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc create_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ set lib_name "" -#@ set pdb_file "tech.pdb" -#@ set log_file "log_file" -#@ -#@ if {[info exists ra(-ignore_case)]} { -#@ set cmd [format {org_create_mw_lib %s} $ra() ] -#@ } else { -#@ set cmd [format {org_create_mw_lib -case_sensitive %s} $ra() ] -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ set cmd [concat [concat $cmd " -technology " ] " $ra(-technology) "] -#@ } -#@ -#@ if {[info exists ra(-ignore_tf_error)]} { -#@ set cmd [concat $cmd " -ignore_tf_error " ] -#@ } -#@ -#@ if {[info exists ra(-hier_separator)]} { -#@ set cmd [concat [concat $cmd " -hier_seperator " ] " $ra(-hier_separator) "] -#@ } -#@ -#@ if {[info exists ra(-bus_naming_style)]} { -#@ set cmd [concat [concat $cmd " -bus_naming_style " ] " {$ra(-bus_naming_style)} "] -#@ } -#@ -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ set cmd [concat [concat $cmd " -reference_control_file " ] " $ra(-reference_control_file) "] -#@ } -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ set cmd [concat [concat [concat $cmd " -mw_reference_library {" ] " $ra(-mw_reference_library) "] "}"] -#@ } -#@ -#@ if { ![uplevel #0 $cmd] } { -#@ return 0 -#@ } -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-open)]} { -#@ uplevel #0 $cmd -#@ set cmd [format {open_mw_lib %s} $ra() ] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes create_mw_lib -hide_body -info " Create a milkyway library " -define_args {{-technology "Technology file name" "file_name" string {optional}} {-ignore_tf_error "Ignore the error in technology file" "" boolean {hidden optional}} {-hier_separator "Hierarchical separator, default is backslash / " "separator" string {hidden optional}} {-bus_naming_style "Bus naming style" "bus_naming_style" string {optional}} {-ignore_case "Make case insensitive" "" boolean {hidden optional}} {-case_sensitive "Make case sensitive" "" boolean {hidden optional}} {-mw_reference_library "List of reference libraries" "lib_list" list {optional}} {-reference_control_file "Reference control file" "file_name" string {optional}} {-open "Open the library after creation" "" boolean {optional}} {"" "Library name to create" "libName" string {required}}} -#@ -#@ # -#@ ############################################################################## -#@ # -#@ # PROCEDURE: report_mw_lib -#@ # -#@ # ABSTRACT: wrapper around MWUI report_mw_lib -#@ # -#@ ############################################################################## -#@ -#@ proc report_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-mw_reference_library)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -mw_reference_library %s} $ra() ] -#@ } else { -#@ set cmd [format {org_report_mw_lib -mw_reference_library} ] -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if {[info exists ra(-unit_range)]} { -#@ if {[info exists ra()]} { -#@ set cmd [format {org_report_mw_lib -unit_range %s} $ra() ] -#@ } else { -#@ echo "Error : Library name must be specified when using this option" -#@ return 0; -#@ } -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes report_mw_lib -hide_body -info " Report information about the library " -define_args {{-unit_range "Report unit range of library" "" boolean {optional}} {-mw_reference_library "Report list of reference libraries" "" boolean {optional}} {"" "Library to be reported" "libName" string {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_lib -#@ # -#@ # ABSTRACT: Wrapper around close_mw_lib to handle -save option properly -#@ # - save_mw_cel to save current cel with dc_netlist -#@ # - close_mw_cel to close current cel -#@ # - save_open_cels to save other open cels before closing library -#@ # -#@ ############################################################################## -#@ -#@ proc close_mw_lib args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ if {$args == ""} { -#@ set cmd [format {icc_is_dc_up} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ if {[uplevel #0 $cmd]} { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } else { -#@ return 0 -#@ } -#@ } else { -#@ set cmd [format {org_close_mw_lib } ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-save)]} { -#@ -#@ set cmd [format {save_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {close_mw_cel} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ -#@ set cmd [format {save_open_cels} ] -#@ if {![uplevel #0 $cmd]} { -#@ return -#@ } -#@ } -#@ -#@ set cmd [format {org_close_mw_lib} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-save "Save open cels" "" boolean {optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } else { -#@ define_proc_attributes close_mw_lib -hide_body -info " Closes the milkyway library " -define_args {{-no_save "Don't save open cels" "" boolean {hidden optional}} {"" "libraries to be closed" "lib list" list {hidden optional}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: write_mw_lib_files -#@ # -#@ # ABSTRACT: Write technology or reference control file -#@ # History: Yun Zhang 2012/12/11, public option -stream_layer_map_file -#@ # History: Yun Zhang 2012/9/5. support new hidden option -vt_cell_placement_properties -#@ # History: Yun Zhang 2011/12/5. add new hidden option -stream_layer_map_file -#@ # -#@ ############################################################################## -#@ proc write_mw_lib_files args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd "" -#@ -#@ if {[info exists ra(-reference_control_file)]} { -#@ #Option -reference_contrl_file, -plib and -technology are exclusive. -#@ # If both of them are set at the same time, error reported. -#@ # 9000273455, by xqsun, 2009/2/4 -#@ if {[info exists ra(-technology)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-technology'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-reference_control_file' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {report_mw_lib_ref_ctrl_file -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-technology)]} { -#@ if {[info exists ra(-plib)]} { -#@ echo "Error: Cannot specify '-technology' with '-plib'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-vt_cell_placement_properties)]} { -#@ echo "Error: Cannot specify '-technology' with '-vt_cell_placement_properties'.(CMD-001)" -#@ return 0 -#@ } elseif {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-technology' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-vt_cell_placement_properties)]} { -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ echo "Error: Cannot specify '-vt_cell_placement_properties' with '-stream_layer_map_file'.(CMD-001)" -#@ return 0 -#@ } else { -#@ set cmd [format {org_report_mw_lib -vt_cell_placement_properties -output %s %s} $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ -#@ if {[info exists ra(-stream_layer_map_file)]} { -#@ set cmd [format {org_report_mw_lib -stream_layer_map_file %s -output %s %s} $ra(-stream_layer_map_file) $ra(-output) $ra() ] -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ } -#@ -#@ define_proc_attributes write_mw_lib_files -hide_body -info " Write technology or reference control file " -define_args {{-technology "Dump technology file" "" boolean {optional}} {-vt_cell_placement_properties "Dump multi-VT cells' implant layer information of library" "" boolean {optional hidden}} {-reference_control_file "Dump reference control file" "" boolean {optional}} {-stream_layer_map_file "Dump layer map file during stream in/out" "" string {optional}} {-output "Output file" "file_name" string {required}} {"" "Library to be reported" "libName" string {required}}} -#@ } -#@ ############################################################################## -#@ # -#@ # PROCEDURE: close_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around close_mw_cel to add -save option -#@ # remove_timing_design is the command to shutdown dc netlist -#@ # -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc close_mw_cel args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ global mw_is_all_views -#@ set cmd [format {icc_is_dc_up} ] -#@ set dc_is_up [uplevel #0 $cmd] -#@ -#@ set cmd_close [format {org_close_mw_cel} ] -#@ -#@ if {[info exists ra(-all_views)]} { -#@ set cmd_close [format {%s -all_views} $cmd_close] -#@ set mw_is_all_views 1 -#@ } -#@ if {[info exists ra(-all_versions)]} { -#@ set cmd_close [format {%s -all_versions} $cmd_close] -#@ } -#@ if {[info exists ra(-save)]} { -#@ set cmd_close [format {%s -save} $cmd_close] -#@ } -#@ if {[info exists ra(-verbose)]} { -#@ set cmd_close [format {%s -verbose} $cmd_close] -#@ } -#@ if {[info exists ra(-hierarchy)]} { -#@ set cmd_close [format {%s -hierarchy} $cmd_close] -#@ } -#@ -#@ ui_util_clean_saved_lib_attr $args -#@ -#@ set cmd "" -#@ set lcels "" -#@ set is_current_closed 1 -#@ -#@ if {[info exists ra()]} { -#@ set lcels $ra() -#@ } -#@ set len [string length $lcels] -#@ if {$len > 0} { -#@ set is_current_closed [is_current_mw_cel $lcels] -#@ set cmd_close [format {%s {%s}} $cmd_close $lcels] -#@ } -#@ if {[uplevel #0 $cmd_close]} { -#@ set mw_is_all_views 0 -#@ if {$dc_is_up == 1} { -#@ if {$is_current_closed == 1} { -#@ set cmd [format {remove_design -quiet -designs} ] -#@ return [uplevel #0 $cmd] -#@ } -#@ return 1 -#@ } else { -#@ return 1 -#@ } -#@ } else { -#@ set mw_is_all_views 0 -#@ return 0 -#@ } -#@ } -#@ -#@ define_proc_attributes close_mw_cel -hide_body -info " Closes the design " -define_args {{-save "Save the design" "" boolean {optional}} {-discard "Discard any changes" "" boolean {optional hidden}} {-verbose "Print out debugging messages" "" boolean {optional hidden}} {-hierarchy "Close top design and its child designs" "" boolean {optional}} {-all_views "Close all views of the design" "" boolean {optional}} {-all_versions "Close all versions of the design" "" boolean {optional}} {"" "designs to be closed" "design list" list {optional}}} -#@ -#@ ############################################################################## -#@ # -#@ # PROCEDURE: save_all_mw_cel -#@ # -#@ # ABSTRACT: Wrapper around save_mw_cel to save all the open cels. Needed for Black box flow. -#@ # -#@ ############################################################################## -#@ -#@ proc save_all_mw_cels { } { -#@ set top_cel [get_attribute [current_mw_cel] name] -#@ -#@ set cels [fp_get_open_cells] -#@ -#@ foreach cel $cels { -#@ if {$cel != $top_cel} { -#@ current_mw_cel $cel -#@ -#@ save_mw_cel -#@ } -#@ } -#@ -#@ current_mw_cel $top_cel -#@ -#@ save_mw_cel -#@ } -#@ -#@ icc_hide_cmd save_all_mw_cels -#@ -#@ ############################################################################## -#@ # PROCEDURE: execute_command_and_create_cel_from_scratch -#@ # ABSTRACT: This procedure executes the given command and creates the CEL -#@ # from scratch after executing this command. -#@ ############################################################################## -#@ proc execute_command_and_create_cel_from_scratch {org_cmd_name args} { -#@ global mw_create_cel_force -#@ global mw_enable_auto_cel -#@ global mw_force_auto_cel -#@ -#@ set lib [current_mw_lib] -#@ -#@ # If no MW lib, design is not from MW. Execute the original command -#@ # and return. -#@ if {$lib == ""} { -#@ return [eval $org_cmd_name $args] -#@ } -#@ -#@ # Get values of few variables. -#@ set incr_mode $mw_create_cel_force -#@ set mw_create_cel_force TRUE -#@ -#@ # Get auto cel mode, disable it temporarily if enabled. -#@ set auto_cel_mode $mw_enable_auto_cel -#@ set mw_enable_auto_cel FALSE -#@ -#@ # Check if the already existing CEL is auto-CEL. -#@ set auto_cel 0 -#@ if {[is_cel_auto_cel]} { -#@ set auto_cel 1 -#@ } elseif {![get_top_cel_mwid]} { -#@ set auto_cel 1 -#@ } -#@ -#@ -#@ # Run the original command, if not successful restore the incr_mode -#@ # variable and return. No CEL is created. -#@ if {![eval $org_cmd_name $args]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ return 0 -#@ } -#@ -#@ # Restore auto_cel mode -#@ set mw_enable_auto_cel $auto_cel_mode -#@ -#@ # Now create auto or real CEL depending on what the original CEL was. -#@ if {$auto_cel == "1"} { -#@ # Force creation of auto-CEL, since commands other than read_def/pdef -#@ # do not decouple CEL from DC. -#@ -#@ set mw_force_auto_cel TRUE -#@ set cmd [format {save_mw_cel -auto}] -#@ } else { -#@ if [get_top_cel_mwid] { -#@ set cmd [format {save_mw_cel -create}] -#@ echo "Information: Command not supported by incr. update or write-thru." -#@ echo " Creating new CEL from scratch, old CEL will be closed." -#@ } -#@ } -#@ -#@ # Create the Auto CEL or normal CEL from scratch. -#@ if {![uplevel #0 $cmd]} { -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 0 -#@ } -#@ -#@ set mw_create_cel_force $incr_mode -#@ set mw_force_auto_cel FALSE -#@ return 1 -#@ } -#@ -#@ define_proc_attributes execute_command_and_create_cel_from_scratch -hidden -hide_body -#@ -#@ ############################################################################## -#@ # PROCEDURE: read_def -#@ # ABSTRACT: Wrapper around read_def to handle incremental update properly -#@ # if MW based read_def is used, bypass the wrapper -#@ # enable_milkyway_def_reader_writer must be TRUE and use_pdb_lib_format must -#@ # be false for MW read_Def to be run, use wrapper if either condition fails -#@ ############################################################################## -#@ rename -force dc_read_def org_read_def -#@ icc_hide_cmd org_read_def -#@ proc dc_read_def args { -#@ parse_proc_arguments -args $args ra -#@ -#@ return [eval execute_command_and_create_cel_from_scratch "org_read_def" $args] -#@ } -#@ -#@ define_proc_attributes dc_read_def -hide_body -info " Read a def file " -define_args {{-design "name of design for which clusters are to be read" "" string {optional}} {-quiet "do not print out any warnings" "" boolean {optional}} {-verbose "print out more warnings" "" boolean {optional}} {-allow_physical_cells "allow physical cells" "" boolean {optional}} {-allow_physical_ports "allow physical ports" "" boolean {optional}} {-allow_physical_nets "allow physical nets" "" boolean {optional}} {-skip_signal_nets "skip signal nets" "" boolean {optional}} {-incremental "incremental" "" boolean {optional}} {-enforce_scaling "enforce_scaling" "" boolean {optional}} {-move_bounds "move bounds" "" boolean {optional}} {"" "input def file names" "input_def_file_name" string {required}}} -#@ -#@ -#@ ############################################################################## -#@ # PROCEDURE: group -#@ # ABSTRACT: Wrapper around group to handle incremental update properly -#@ ############################################################################## -#@ rename -force group org_group -#@ icc_hide_cmd org_group -#@ proc group args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_group" $args] -#@ } -#@ -#@ define_proc_attributes group -hide_body -info " create new hierarchy" -define_args {{-except "cells not to be included in the group" "exclude_list" list {optional}} -#@ {-design_name "name of design created for new hierarchy" "design_name" string {optional}} -#@ {-cell_name "name of cell created for new hierarchy" "cell_name" string {optional}} -#@ {-logic "group any combinational elements" "" boolean {optional}} -#@ {-pla "group any PLA elements" "" boolean {optional}} -#@ {-fsm "group all elements part of a finite state machine" "" boolean {optional}} -#@ {-hdl_block "name of hdl_block to group" "" string {optional}} -#@ {-hdl_bussed "group all bussed gates under this block" "" boolean {optional}} -#@ {-hdl_all_blocks "group all hdl blocks under this block" "" boolean {optional}} -#@ {-soft "set the group_name attribute" "" boolean {optional}} -#@ {"" "cells to be included in the group" "cell_list" list {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: copy_design -#@ # ABSTRACT: Wrapper around copy_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force copy_design org_copy_design -#@ icc_hide_cmd org_copy_design -#@ proc copy_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_copy_design" $args] -#@ } -#@ -#@ define_proc_attributes copy_design -hide_body -info " copy_design" -define_args {{"" "List of designs to be copied" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: create_design -#@ # ABSTRACT: Wrapper around create_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force create_design org_create_design -#@ icc_hide_cmd org_create_design -#@ proc create_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_create_design" $args] -#@ } -#@ -#@ define_proc_attributes create_design -hide_body -info " Creates a design in dc_shell memory" -define_args {{"" "name of the design to create" "" string {required}} -#@ {"" "name of file for design; optional" "" string {optional}}} -#@ -#@ ############################################################################## -#@ # PROCEDURE: reset_design -#@ # ABSTRACT: Wrapper around reset_design to handle incremental update properly -#@ ############################################################################## -#@ #rename -force reset_design org_reset_design -#@ #icc_hide_cmd org_reset_design -#@ #proc reset_design args { -#@ # parse_proc_arguments -args $args ra -#@ # return [eval execute_command_and_create_cel_from_scratch "org_reset_design" $args] -#@ #} -#@ -#@ ############################################################################## -#@ # PROCEDURE: rename_design -#@ # ABSTRACT: Wrapper around rename_design to handle incremental update properly -#@ ############################################################################## -#@ rename -force rename_design org_rename_design -#@ icc_hide_cmd org_rename_design -#@ proc rename_design args { -#@ parse_proc_arguments -args $args ra -#@ return [eval execute_command_and_create_cel_from_scratch "org_rename_design" $args] -#@ } -#@ -#@ define_proc_attributes rename_design -hide_body -info " rename_design" -define_args {{"" "List of designs to be renamed" "design_list" list {required}} -#@ {"" "Name of new design or target file" "target_name" string {required}}} -#@ -#@ } -#@ -#@ ############################################################################## -#@ # If we are in icc_shell (i.e. Galileo) then -#@ # load the procedures to switch between DC and Milkyway collections. -#@ # Set the default to MW collection unless otherwise specified. -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # load the procedures that switch between DC and MW collections -#@ source $synopsys_root/auxx/syn/collection_procs.tcl -#@ -#@ set CS mw -#@ -#@ # see if the user wants DC -#@ if {! [catch {getenv USE_DC_COLLECTIONS_ONLY}] && -#@ [getenv USE_DC_COLLECTIONS_ONLY] } { -#@ set CS dc -#@ } -#@ -#@ # set the collection source now -#@ redirect /dev/null { -#@ if {[catch {set_collection_mode -handle $CS}]} { -#@ catch {set_collection_option -handle $CS} -#@ } -#@ } -#@ -#@ unset CS -#@ } -#@ -#@ ############################################################################## -#@ # procedure for route command -#@ # echo the command to a temp tcl file for seperate process to pick up -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ rename -force route org_route -#@ icc_hide_cmd org_route -#@ proc route args { -#@ set route_cmd_file_name ".route_cmd.tcl" -#@ set route_cmd_temp_file_name ".route_cmd.tcl.temp" -#@ set fp [open $route_cmd_file_name "w"] -#@ set route_cmd [concat "sep_proc_route " $args " -child"] -#@ puts $fp $route_cmd -#@ close $fp -#@ -#@ uplevel #0 rename -force route route_temp_proc -#@ uplevel #0 rename -force org_route route -#@ set status [ uplevel #0 route $args ] -#@ uplevel #0 rename -force route org_route -#@ uplevel #0 rename -force route_temp_proc route -#@ -#@ if { [info exist status ] == 1 } { -#@ return $status -#@ } -#@ return -#@ } -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: set_ignore_cell -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/ideal_cell.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # Tcl Command: check_physical_design -#@ # Description: Load the command only in IC Compiler (icc_shell) -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ # Load the compiled Tcl byte-code: -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_core.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_utils.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_flows.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_reports.tbc -#@ source $synopsys_root/auxx/syn/psyn/check_physical_design_ui.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_opt.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_cmd.tbc -#@ source $synopsys_root/auxx/syn/psyn/sanity_setup_rpt.tbc -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/msgParser.tbc -#@ source $synopsys_root/auxx/syn/psyn/displacement_gui.tbc -#@ source $synopsys_root/auxx/syn/psyn/categorize_timing_gui.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ source $synopsys_root/auxx/syn/psyn/propagate_all_clocks.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*dc_shell*} $synopsys_program_name] && [shell_is_in_topographical_mode] } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] || [string match -nocase {*dc_shell*} $synopsys_program_name] || [string match -nocase {*de_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/write_timing_context.tcl.e; -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ source $synopsys_root/auxx/syn/psyn/write_scenarios.tbc; -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "de_shell" } { -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source $synopsys_root/auxx/syn/psyn/create_qor_snapshot.tbc -#@ source $synopsys_root/auxx/syn/psyn/report_qor_snapshot.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ -#@ source $synopsys_root/auxx/syn/psyn/mcmm_utils.tcl.e -#@ } -#@ -#@ ############################################################################## -#@ # ICC setup and hiding commands/procs etc -#@ ############################################################################## -#@ -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ #set save_mw_cel_lib_setup TRUE -#@ #set auto_restore_mw_cel_lib_setup FALSE -#@ -#@ alias create_wiring_keepout create_wiring_keepouts -#@ alias get_wiring_keepout get_wiring_keepouts -#@ alias get_placement_keepout get_placement_keepouts -#@ alias create_placement_keepout create_placement_keepouts -#@ -#@ icc_hide_cmd execute_command_and_create_cel_from_scratch -#@ icc_hide_cmd dc_read_def -#@ icc_hide_cmd read_edif -#@ icc_hide_cmd read_sverilog -#@ icc_hide_cmd read_vhdl -#@ icc_hide_cmd set_collection_mode -#@ icc_hide_cmd return_dc_collection -#@ icc_hide_cmd return_mw_collection -#@ set mw_use_pdb_lib_format true -#@ } -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: get_dont_touch_nets -#@ # Description: wrapper of "get_nets -filter dont_touch_reason==mv" -#@ ############################################################################## -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ -#@ proc get_dont_touch_nets args { -#@ -#@ parse_proc_arguments -args $args ra -#@ -#@ set cmd [format {get_nets}] -#@ -#@ if {[info exists ra()]} { -#@ set cmd [format {%s {%s}} $cmd $ra()] -#@ } -#@ if {[info exists ra(-type)]} { -#@ set cmd [format {%s -filter dont_touch_reasons=~*%s*} $cmd $ra(-type)] -#@ } -#@ if {[info exists ra(-hierarchical)]} { -#@ set cmd [format {%s -hierarchical} $cmd] -#@ } -#@ if {[info exists ra(-quiet)]} { -#@ set cmd [format {%s -quiet} $cmd] -#@ } -#@ if {[info exists ra(-regexp)]} { -#@ set cmd [format {%s -regexp} $cmd] -#@ } -#@ if {[info exists ra(-nocase)]} { -#@ set cmd [format {%s -nocase} $cmd] -#@ } -#@ if {[info exists ra(-exact)]} { -#@ set cmd [format {%s -exact} $cmd] -#@ } -#@ -#@ return [uplevel #0 $cmd] -#@ } -#@ -#@ define_proc_attributes get_dont_touch_nets -info " Get dont_touch nets " -permanent -define_args { {"" "Match net names against patterns" "patterns" list {optional}} {-type "Match net dont_touch reasons" "reasons" list {required}} {-hierarchical "Search level-by-level in current instance" "" boolean {optional}} {-quiet "Suppress all messages" "" boolean {optional hidden}} {-regexp "Patterns are full regular expressions" "" boolean {optional hidden}} {-nocase "With -regexp, matches are case-insensitive" "" boolean {optional hidden}} {-exact "Wildcards are considered as plain characters" "" boolean {optional hidden}} } -#@ -#@ alias get_dont_touch_net get_dont_touch_nets -#@ } -#@ -#@ -#@ ############################################################################## -#@ # return the first {index value} pair in Tcl array ary. -#@ ############################################################################## -#@ proc _snps_array_peek { level ary } { -#@ upvar #$level $ary loc_ary -#@ set ret [list] -#@ if {[catch {set token [array startsearch loc_ary]}]} { -#@ return $ret -#@ } -#@ while {[array anymore loc_ary $token]} { -#@ set k [array nextelement loc_ary $token] -#@ set v $loc_ary($k) -#@ set ret [list $k $v] -#@ break -#@ } -#@ array donesearch loc_ary $token -#@ return $ret; -#@ } -#@ define_proc_attributes _snps_array_peek -hidden -#@ -#@ -#@ ############################################################################## -#@ # Tcl Command: filter_collection -#@ # Description: DC wrapper for filter_collection with fixes of direction filter -#@ # -#@ # This is a fix for DC's filter using "direction" attribute. This -#@ # attribute is of integer type, but user wants a string format -#@ ############################################################################## -#@ if {[string match -nocase {*icc_shell*} $synopsys_program_name] == 0} { -#@ rename -force -hidden filter_collection _real_filter_collection -#@ proc filter_collection {args} { -#@ parse_proc_arguments -args $args ra -#@ -#@ set regexp "" -#@ set nocase "" -#@ if {[info exist ra(-regexp)]} { -#@ set regexp "-regexp" -#@ } -#@ if {[info exist ra(-nocase)]} { -#@ set nocase "-nocase" -#@ } -#@ set coll $ra(collection1) -#@ -#@ # _real_filter_collection silently returns in this error condition -#@ if {[catch {set coll_size [sizeof_collection $coll]}] || $coll_size <= 0} { -#@ return [list] -#@ } -#@ -#@ if {$::sh_translate_direction_attribute == true} { -#@ set filter_expr [replace_direction $coll $ra(expression)] -#@ } else { -#@ set filter_expr $ra(expression) -#@ } -#@ -#@ # if $ra(expression) is not empty but filter_expr is, collection is heterogrnous -#@ # and expression has "direction" as substring. We have to walk through all objects -#@ if {[string length $filter_expr] == 0 && [string length $ra(expression)] != 0} { -#@ set part1 [format {_real_filter_collection %s %s } $regexp $nocase] -#@ set results "" -#@ set subclxn "" -#@ set subsize [expr [sizeof_collection $coll]/80 + 10] -#@ set counter 0 -#@ foreach_in_collection obj $coll { -#@ incr counter -#@ set cmd [format {%s %s {%s}} $part1 $obj [replace_direction $obj $ra(expression)]] -#@ append_to_collection subclxn [uplevel #0 $cmd] -#@ if {[expr $counter % $subsize] == 0} { -#@ append_to_collection results $subclxn -#@ set subclxn "" -#@ } -#@ } -#@ if {[sizeof_collection $subclxn] != 0} { -#@ append_to_collection results $subclxn -#@ } -#@ return $results -#@ } else { -#@ set cmd [format {_real_filter_collection %s %s %s {%s}} $regexp $nocase $coll $filter_expr] -#@ return [uplevel #0 $cmd] -#@ } -#@ } -#@ define_proc_attributes filter_collection -info " Filter a collection, resulting in new collection " -permanent -define_args { {-regexp "Operators =~ and !~ use regular expressions" "" boolean {optional}} {-nocase "Case insensitive string match" "" boolean {optional}} {collection1 "Collection to filter" "collection1" string {required}} {expression "Filter expression" "expression" string {required}} } -#@ -#@ } -#@ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/.dc_procs.tcl - -#@ -#@ # Temporary fix for the LMC_HOME variable- set it to an empty string -#@ -#@ if { [catch {getenv LMC_HOME } __err ] != 0 } { -#@ setenv LMC_HOME "" -#@ } -#@ -#@ -#@ # -#@ # -#@ # Site-Specific Variables -#@ # -#@ # These are the variables that are most commonly changed at a -#@ # specific site, either upon installation of the Synopsys software, -#@ # or by specific engineers in their local .synopsys files. -#@ # -#@ # -#@ -#@ # from the System Variable Group -#@ set link_library { * your_library.db } -#@ -#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/minpower/syn ${synopsys_root}/dw/syn_ver ${synopsys_root}/dw/sim_ver] -#@ set target_library your_library.db -#@ set synthetic_library "" -#@ set command_log_file "./command.log" -#@ set designer "" -#@ set company "" -#@ set find_converts_name_lists "false" -#@ -#@ set symbol_library your_library.sdb -#@ -#@ # Turn on Formality SVF recording -#@ if { $synopsys_program_name == "dc_shell" || $synopsys_program_name == "de_shell" || $synopsys_program_name == "design_vision" } { -#@ set_svf -default default.svf -#@ } -#@ -#@ # from the Schematic Variable Group -#@ -#@ # from the Plot Variable Group -#@ # [froi] 07/06/2012: Remove old Design Analyzer plot_command variable -#@ #if { $sh_arch == "hp700" } { -#@ # set plot_command "lp -d" -#@ #} else { -#@ # set plot_command "lpr -Plw" -#@ #} -#@ -#@ set view_command_log_file "./view_command.log" -#@ -#@ # from the View Variable group -#@ if { $sh_arch == "hp700" } { -#@ set text_print_command "lp -d" -#@ } else { -#@ set text_print_command "lpr -Plw" -#@ } -#@ # -#@ # System Variable Group: -#@ # -#@ # These variables are system-wide variables. -#@ # -#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid -#@ set auto_link_disable "false" -#@ set auto_link_options "-all" -#@ set uniquify_naming_style "%s_%d" -#@ set verbose_messages "true" -#@ set echo_include_commands "true" -#@ set svf_file_records_change_names_changes "true" -#@ set change_names_update_inst_tree "true" -#@ set change_names_dont_change_bus_members false -#@ set default_name_rules "" -#@ #set tdrc_enable_clock_table_creation "true" -#@ -#@ # -#@ # Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the COMPILE command. -#@ # -#@ set compile_assume_fully_decoded_three_state_busses "false" -#@ set compile_no_new_cells_at_top_level "false" -#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false" -#@ set compile_update_annotated_delays_during_inplace_opt "true" -#@ set compile_instance_name_prefix "U" -#@ set compile_instance_name_suffix "" -#@ set compile_negative_logic_methodology "false" -#@ set compile_disable_hierarchical_inverter_opt "false" -#@ set compile_use_low_timing_effort "false" -#@ set compile_fix_cell_degradation "false" -#@ set compile_preserve_subdesign_interfaces "false" -#@ set compile_enable_constant_propagation_with_no_boundary_opt "true" -#@ set port_complement_naming_style "%s_BAR" -#@ set compile_implementation_selection "true" -#@ set compile_delete_unloaded_sequential_cells "true" -#@ set reoptimize_design_changed_list_file_name "" -#@ set compile_checkpoint_phases "false" -#@ set compile_cpu_limit 0.0 -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ set compile_top_all_paths "false" -#@ set compile_top_acs_partition "false" -#@ set default_port_connection_class "universal" -#@ set compile_hold_reduce_cell_count "false" -#@ set compile_retime_license_behavior "wait" -#@ set dont_touch_nets_with_size_only_cells "false" -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ set dct_prioritize_area_correlation "false" -#@ set compile_error_on_missing_physical_cells "false" -#@ } -#@ -#@ set ldd_return_val 0 -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh -#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " -#@ -#@ } -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl -#@ # 9000784997: Do not log to command.log when sourcing .tbc files -#@ set prev_sh_source_logging [get_app_var sh_source_logging] -#@ set_app_var sh_source_logging 0 -#@ source ${synopsys_root}/auxx/syn/scripts/analyze_datapath.tbc -#@ set_app_var sh_source_logging $prev_sh_source_logging -#@ } -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ ####################################################################### -#@ # -#@ # list_duplicate_designs.tcl 21 Sept. 2006 -#@ # -#@ # List designs in dc_shell memory that have the same design name -#@ # -#@ # COPYRIGHT (C) 2006, SYNOPSYS INC., ALL RIGHTS RESERVED. -#@ # -#@ ####################################################################### -#@ -#@ proc list_duplicate_designs { args } { -#@ parse_proc_arguments -args $args ra -#@ -#@ # Get the list of duplicate designs -#@ set the_pid [pid] -#@ set rand_1 [expr int(rand() * 100000)] -#@ set temp_file_1 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_1] -#@ -#@ redirect $temp_file_1 { foreach_in_collection ldd_design [find design "*"] { -#@ echo [get_object_name $ldd_design] -#@ } } -#@ -#@ set rand_2 [expr int(rand() * 100000)] -#@ set temp_file_2 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_2] -#@ -#@ sh sort $temp_file_1 | uniq -d | tee $temp_file_2 -#@ file delete $temp_file_1 -#@ -#@ # Report duplicates -#@ if { ! [file size $temp_file_2] } { -#@ echo [concat {No duplicate designs found.}] -#@ set ldd_return_val 0 -#@ } else { -#@ set rand_3 [expr int(rand() * 100000)] -#@ set temp_file_3 [format "/tmp/ldd_design_%s_%s" $the_pid $rand_3] -#@ echo {Warning: Multiple designs in memory with the same design name.} -#@ echo {} -#@ echo { Design File Path} -#@ echo { ------ ---- ----} -#@ list_designs -table > $temp_file_3 -#@ echo [sh fgrep -f $temp_file_2 $temp_file_3 | sort | grep -v 'Design.*File.*Path'] -#@ file delete $temp_file_3 -#@ set ldd_return_val 1 -#@ } -#@ -#@ # Clean up -#@ file delete $temp_file_2 -#@ -#@ set list_duplicate_designs1 $ldd_return_val -#@ } -#@ -#@ define_proc_attributes list_duplicate_designs -info " List designs of same names" -permanent -define_args { -#@ } -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/scripts/list_duplicate_designs.tcl - -#@ -#@ -#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint"; -#@ -#@ set compile_top_all_paths "false" -#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name -#@ -#@ # -#@ # These variables affects compile, report_timing and report_constraints -#@ # commands. -#@ # -#@ set enable_recovery_removal_arcs "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ -#@ # -#@ # Multibit Variable Group: -#@ # -#@ # These variables affect the multibit mapping functionality -#@ # -#@ -#@ set bus_multiple_separator_style "," -#@ set bus_multiple_name_separator_style ",," -#@ -#@ # -#@ # ILM Variable Group: -#@ # -#@ # These variables affect Interface Logic Model functionality -#@ # -#@ -#@ set ilm_ignore_percentage 25 -#@ -#@ # -#@ # Estimator Variable Group: -#@ # -#@ # These variables affect the designs created by the ESTIMATE command. -#@ # -#@ set estimate_resource_preference "fast" -#@ alias est_resource_preference estimate_resource_preference -#@ set lbo_lfo_enable_at_pin_count 3 -#@ set lbo_cells_in_regions "false" -#@ -#@ # Synthetic Library Group: -#@ # -#@ # These variable affect synthetic library processing. -#@ # -#@ set cache_dir_chmod_octal "777" -#@ set cache_file_chmod_octal "666" -#@ set cache_read "~" -#@ set cache_read_info "false" -#@ set cache_write "~" -#@ set cache_write_info "false" -#@ set synlib_dont_get_license {} -#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07} -#@ set synlib_wait_for_design_license {} -#@ set synlib_dwhomeip {} -#@ -#@ # -#@ # Insert_DFT Variable Group: -#@ # -#@ #set test_default_client_order [list] -#@ set insert_dft_clean_up "true" -#@ set insert_test_design_naming_style "%s_test_%d" -#@ # /*insert_test_scan_chain_only_one_clock = "false" -#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/ -#@ set test_clock_port_naming_style "test_c%s" -#@ set test_scan_clock_a_port_naming_style "test_sca%s" -#@ set test_scan_clock_b_port_naming_style "test_scb%s" -#@ set test_scan_clock_port_naming_style "test_sc%s" -#@ set test_scan_enable_inverted_port_naming_style "test_sei%s" -#@ set test_scan_enable_port_naming_style "test_se%s" -#@ set test_scan_in_port_naming_style "test_si%s%s" -#@ set test_scan_out_port_naming_style "test_so%s%s" -#@ set test_non_scan_clock_port_naming_style "test_nsc_%s" -#@ set test_default_min_fault_coverage 95 -#@ set test_dedicated_subdesign_scan_outs "false" -#@ set test_disable_find_best_scan_out "false" -#@ set test_dont_fix_constraint_violations "false" -#@ set test_isolate_hier_scan_out 0 -#@ set test_mode_port_naming_style "test_mode%s" -#@ set test_mode_port_inverted_naming_style "test_mode_i%s" -#@ set compile_dont_use_dedicated_scanout 1 -#@ set test_mux_constant_si "false" -#@ -#@ # -#@ # Analyze_Scan Variable Group: -#@ # -#@ # These variables affect the designs created by the PREVIEW_SCAN command. -#@ # -#@ set test_preview_scan_shows_cell_types "false" -#@ set test_scan_link_so_lockup_key "l" -#@ set test_scan_link_wire_key "w" -#@ set test_scan_segment_key "s" -#@ set test_scan_true_key "t" -#@ -#@ # -#@ # bsd Variable Group: -#@ -#@ # These variables affect the report generated by the check_bsd command -#@ # and the BSDLout generated by the write_bsdl command. -#@ # -#@ set test_user_test_data_register_naming_style "UTDR%d" -#@ -#@ set test_user_defined_instruction_naming_style "USER%d" -#@ -#@ set test_bsdl_default_suffix_name "bsdl" -#@ -#@ set test_bsdl_max_line_length 80 -#@ -#@ set test_cc_ir_masked_bits 0 -#@ -#@ set test_cc_ir_value_of_masked_bits 0 -#@ -#@ set test_bsd_allow_tolerable_violations "false" -#@ set test_bsd_optimize_control_cell "false" -#@ set test_bsd_control_cell_drive_limit 0 -#@ set test_bsd_manufacturer_id 0 -#@ set test_bsd_part_number 0 -#@ set test_bsd_version_number 0 -#@ set bsd_max_in_switching_limit 60000 -#@ set bsd_max_out_switching_limit 60000 -#@ -#@ # -#@ # TestManager Variable Group: -#@ # -#@ # These variables affect the TestManager methodology. -#@ # -#@ set multi_pass_test_generation "false" -#@ -#@ # -#@ # TestSim Variable Group: -#@ # -#@ # These variables affect the TestSim behavior. -#@ # -#@ # set testsim_print_stats_file "true" -#@ -#@ # Test DRC Variable Group: -#@ # -#@ # These variables affect the check_test command. -#@ # -#@ set test_capture_clock_skew "small_skew" -#@ set test_allow_clock_reconvergence "true" -#@ set test_check_port_changes_in_capture "true" -#@ set test_infer_slave_clock_pulse_after_capture "infer" -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affect the rtldrc, check_test, write_test_protocol -#@ # and write_test command. -#@ # -#@ set test_default_delay 0.0 -#@ set test_default_bidir_delay 0.0 -#@ set test_default_strobe 40.0 -#@ set test_default_strobe_width 0.0 -#@ set test_default_period 100.0 -#@ set test_stil_max_line_length 72 -#@ -#@ #added for B-2008.09-place_opt-004 to disable this option in ICC -#@ -#@ if { $synopsys_program_name != "icc_shell"} { -#@ set test_write_four_cycle_stil_protocol "false" -#@ set test_protocol_add_cycle "true" -#@ set test_stil_multiclock_capture_procedures "false" -#@ set write_test_new_translation_engine "false" -#@ set test_default_scan_style "multiplexed_flip_flop" -#@ set test_jump_over_bufs_invs "true" -#@ set test_point_keep_hierarchy "false" -#@ set test_mux_constant_so "false" -#@ set test_use_test_models "false" -#@ set test_stil_netlist_format "db" -#@ group_variable test "test_protocol_add_cycle" -#@ group_variable test "test_write_four_cycle_stil_protocol" -#@ group_variable test "test_stil_multiclock_capture_procedures" -#@ group_variable test "test_default_scan_style" -#@ group_variable preview_scan "test_jump_over_bufs_invs" -#@ group_variable insert_dft "test_point_keep_hierarchy" -#@ group_variable insert_dft "test_mux_constant_so" -#@ group_variable test "test_stil_netlist_format" -#@ } -#@ set test_rtldrc_latch_check_style "default" -#@ set test_enable_capture_checks "true" -#@ set ctldb_use_old_prot_flow "false" -#@ set test_bsd_default_delay 0.0 -#@ set test_bsd_default_bidir_delay 0.0 -#@ set test_bsd_default_strobe 95.0 -#@ set test_bsd_default_strobe_width 0.0 -#@ -#@ # -#@ # Test Variable Group: -#@ # -#@ # These variables affects the set_scan_state command. -#@ # -#@ -#@ set compile_seqmap_identify_shift_registers_with_synchronous_logic_ascii false -#@ -#@ # -#@ # Write_Test Variable Group: -#@ # -#@ # These variables affect output of the WRITE_TEST command. -#@ # -#@ set write_test_input_dont_care_value "X" -#@ set write_test_vector_file_naming_style "%s_%d.%s" -#@ set write_test_scan_check_file_naming_style "%s_schk.%s" -#@ set write_test_pattern_set_naming_style "TC_Syn_%d" -#@ set write_test_max_cycles 0 -#@ set write_test_max_scan_patterns 0 -#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */ -#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl} -#@ set write_test_include_scan_cell_info "true" -#@ set write_test_round_timing_values "true" -#@ -#@ -#@ # -#@ # Schematic and EDIF and Hdl Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command, define the behavior of the -#@ # DC system EDIF interface, and are for controlling hdl -#@ # reading. -#@ # -#@ set bus_dimension_separator_style {][} -#@ set bus_naming_style {%s[%d]} -#@ -#@ -#@ # -#@ # Schematic and EDIF Variable Groups: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command and define the behavior of -#@ # the DC system EDIF interface. -#@ # -#@ set bus_range_separator_style ":" -#@ -#@ -#@ # -#@ # EDIF and Io Variable Groups: -#@ # -#@ # These variables define the behavior of the DC system EDIF interface and -#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc. -#@ -#@ set bus_inference_descending_sort "true" -#@ set bus_inference_style "" -#@ set write_name_nets_same_as_ports "false" -#@ # -#@ # Schematic Variable Group: -#@ # -#@ # These variables affect the schematics created by the -#@ # create_schematic command. -#@ # -#@ set font_library "1_25.font" -#@ set generic_symbol_library "generic.sdb" -#@ -#@ # -#@ # Io Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc. -#@ # -#@ #set db2sge_output_directory "" -#@ #set db2sge_scale "2" -#@ #set db2sge_overwrite "true" -#@ #set db2sge_display_symbol_names "false" -#@ -#@ -#@ #set db2sge_display_pin_names "false" -#@ #set db2sge_display_instance_names "false" -#@ #set db2sge_use_bustaps "false" -#@ #set db2sge_use_compound_names "true" -#@ #set db2sge_bit_type "std_logic" -#@ #set db2sge_bit_vector_type "std_logic_vector" -#@ #set db2sge_one_name "'1'" -#@ #set db2sge_zero_name "'0'" -#@ #set db2sge_unknown_name "'X'" -#@ #set db2sge_target_xp "false" -#@ #set db2sge_tcf_package_file "synopsys_tcf.vhd" -#@ #set db2sge_use_lib_section "" -#@ #set db2sge_script "" -#@ #set db2sge_command "" -#@ -#@ # set equationout_and_sign "*" -#@ # set equationout_or_sign "+" -#@ # set equationout_postfix_negation "true" -#@ -#@ # # [wjchen] 2006/08/14: The following variables are obsoleted for DC simpilification. -#@ #set lsiin_net_name_prefix "NET_" -#@ #set lsiout_inverter_cell "" -#@ #set lsiout_upcase "true" -#@ -#@ #set mentor_bidirect_value "INOUT" -#@ #set mentor_do_path "" -#@ #set mentor_input_output_property_name "PINTYPE" -#@ #set mentor_input_value "IN" -#@ #set mentor_logic_one_value "1SF" -#@ #set mentor_logic_zero_one_property_name "INIT" -#@ #set mentor_logic_zero_value "0SF" -#@ #set mentor_output_value "OUT" -#@ #set mentor_primitive_property_name "PRIMITIVE" -#@ #set mentor_primitive_property_value "MODULE" -#@ #set mentor_reference_property_name "COMP" -#@ #set mentor_search_path "" -#@ #set mentor_write_symbols "true" -#@ -#@ ## [wjchen] 0606_simp -#@ #set pla_read_create_flip_flop "false" -#@ #set tdlout_upcase "true" -#@ -#@ # # [wjchen] 2006/08/14: The following4 variables are obsoleted for DC simpilification. -#@ # set xnfout_constraints_per_endpoint "50" -#@ # set xnfout_default_time_constraints true -#@ # set xnfout_clock_attribute_style "CLK_ONLY" -#@ # set xnfout_library_version "" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # set xnfin_family "4000" -#@ # set xnfin_ignore_pins "GTS GSR GR" -#@ # set xnfin_dff_reset_pin_name "RD" -#@ # set xnfin_dff_set_pin_name "SD" -#@ # set xnfin_dff_clock_enable_pin_name "CE" -#@ # set xnfin_dff_data_pin_name "D" -#@ # set xnfin_dff_clock_pin_name "C" -#@ # set xnfin_dff_q_pin_name "Q" -#@ # -#@ -#@ # -#@ # EDIF Variable Group: -#@ # -#@ # These variables define the behavior of the DC system -#@ # EDIF interface. -#@ # -#@ -#@ ##[wjchen] 2006/08/24 -#@ -#@ # set bus_extraction_style {%s[%d:%d]} -#@ -#@ ##[wjchen] 2006/08/24 -#@ #set edifin_autoconnect_offpageconnectors "false" -#@ #set edifin_autoconnect_ports "false" -#@ #set edifin_dc_script_flag "" -#@ #set edifin_delete_empty_cells "true" -#@ #set edifin_delete_ripper_cells "true" -#@ #set edifin_ground_net_name "" -#@ #set edifin_ground_net_property_name "" -#@ #set edifin_ground_net_property_value "" -#@ #set edifin_ground_port_name "" -#@ #set edifin_instance_property_name "" -#@ #set edifin_portinstance_disabled_property_name "" -#@ #set edifin_portinstance_disabled_property_value "" -#@ #set edifin_portinstance_property_name "" -#@ #set edifin_power_net_name "" -#@ #set edifin_power_net_property_name "" -#@ #set edifin_power_net_property_value "" -#@ #set edifin_power_port_name "" -#@ #set edifin_use_identifier_in_rename "false" -#@ #set edifin_view_identifier_property_name "" -#@ #set edifin_lib_logic_1_symbol "" -#@ #set edifin_lib_logic_0_symbol "" -#@ #set edifin_lib_in_port_symbol "" -#@ #set edifin_lib_out_port_symbol "" -#@ #set edifin_lib_inout_port_symbol "" -#@ #set edifin_lib_in_osc_symbol "" -#@ #set edifin_lib_out_osc_symbol "" -#@ #set edifin_lib_inout_osc_symbol "" -#@ #set edifin_lib_mentor_netcon_symbol "" -#@ #set edifin_lib_ripper_bits_property "" -#@ #set edifin_lib_ripper_bus_end "" -#@ #set edifin_lib_ripper_cell_name "" -#@ #set edifin_lib_ripper_view_name "" -#@ #set edifin_lib_route_grid 1024 -#@ #set edifin_lib_templates {} -#@ #set edifout_dc_script_flag "" -#@ #set edifout_design_name "Synopsys_edif" -#@ #set edifout_designs_library_name "DESIGNS" -#@ #set edifout_display_instance_names "false" -#@ #set edifout_display_net_names "false" -#@ #set edifout_external "true" -#@ #set edifout_external_graphic_view_name "Graphic_representation" -#@ #set edifout_external_netlist_view_name "Netlist_representation" -#@ #set edifout_external_schematic_view_name "Schematic_representation" -#@ #set edifout_ground_name "logic_0" -#@ #set edifout_ground_net_name "" -#@ #set edifout_ground_net_property_name "" -#@ #set edifout_ground_net_property_value "" -#@ #set edifout_ground_pin_name "logic_0_pin" -#@ #set edifout_ground_port_name "GND" -#@ #set edifout_instance_property_name "" -#@ #set edifout_instantiate_ports "false" -#@ #set edifout_library_graphic_view_name "Graphic_representation" -#@ #set edifout_library_netlist_view_name "Netlist_representation" -#@ #set edifout_library_schematic_view_name "Schematic_representation" -#@ #set edifout_merge_libraries "false" -#@ #set edifout_multidimension_arrays "false" -#@ #set edifout_name_oscs_different_from_ports "false" -#@ #set edifout_name_rippers_same_as_wires "false" -#@ #set edifout_netlist_only "false" -#@ #set edifout_no_array "false" -#@ #set edifout_numerical_array_members "false" -#@ #set edifout_pin_direction_in_value "" -#@ #set edifout_pin_direction_inout_value "" -#@ #set edifout_pin_direction_out_value "" -#@ #set edifout_pin_direction_property_name "" -#@ #set edifout_pin_name_property_name "" -#@ #set edifout_portinstance_disabled_property_name "" -#@ #set edifout_portinstance_disabled_property_value "" -#@ #set edifout_portinstance_property_name "" -#@ #set edifout_power_and_ground_representation "cell" -#@ #set edifout_power_name "logic_1" -#@ #set edifout_power_net_name "" -#@ #set edifout_power_net_property_name "" -#@ #set edifout_power_net_property_value "" -#@ #set edifout_power_pin_name "logic_1_pin" -#@ #set edifout_power_port_name "VDD" -#@ #set edifout_skip_port_implementations "false" -#@ #set edifout_target_system "" -#@ #set edifout_top_level_symbol "true" -#@ #set edifout_translate_origin "" -#@ #set edifout_unused_property_value "" -#@ #set edifout_write_attributes "false" -#@ #set edifout_write_constraints "false" -#@ #set edifout_write_properties_list {} -#@ #set read_name_mapping_nowarn_libraries {} -#@ #set write_name_mapping_nowarn_libraries {} -#@ -#@ # -#@ # Hdl and Vhdlio Variable Groups: -#@ # -#@ # These variables are for controlling hdl reading, writing, -#@ # and optimizing. -#@ # -#@ set hdlin_enable_upf_compatible_naming "FALSE" -#@ set hdlin_auto_save_templates "FALSE" -#@ set hdlin_generate_naming_style "%s_%d" -#@ set hdlin_enable_relative_placement "rb" -#@ set hdlin_mux_rp_limit "128x4" -#@ set hdlin_generate_separator_style "_" -#@ set hdlin_ignore_textio_constructs "TRUE" -#@ set hdlin_infer_function_local_latches "FALSE" -#@ set hdlin_keep_signal_name "all_driving" -#@ set hdlin_module_arch_name_splitting "FALSE" -#@ set hdlin_preserve_sequential "none" -#@ set hdlin_presto_net_name_prefix "N" -#@ set hdlin_presto_cell_name_prefix "C" -#@ set hdlin_strict_verilog_reader "FALSE" -#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE" -#@ if { $synopsys_program_name == "de_shell" } { -#@ set hdlin_elab_errors_deep "TRUE" -#@ } else { -#@ set hdlin_elab_errors_deep "FALSE" -#@ } -#@ set hdlin_mux_size_min 2 -#@ set hdlin_subprogram_default_values "FALSE" -#@ set hdlin_field_naming_style "" -#@ set hdlin_upcase_names "FALSE" -#@ set hdlin_sv_union_member_naming "FALSE" -#@ set hdlin_enable_hier_map "FALSE" -#@ set hdlin_sv_interface_only_modules "" -#@ set hdlin_sv_enable_rtl_attributes "FALSE" -#@ set hdlin_vhdl_std 2008 -#@ set hdlin_vhdl93_concat "TRUE" -#@ set hdlin_vhdl_syntax_extensions "FALSE" -#@ set hdlin_analyze_verbose_mode 0 -#@ set hdlin_report_sequential_pruning "FALSE" -#@ set hdlin_vrlg_std 2005 -#@ set hdlin_sverilog_std 2012 -#@ set hdlin_while_loop_iterations 4096 -#@ set hdlin_reporting_level "basic" -#@ set hdlin_autoread_verilog_extensions ".v" -#@ set hdlin_autoread_sverilog_extensions ".sv .sverilog" -#@ set hdlin_autoread_vhdl_extensions ".vhd .vhdl" -#@ set hdlin_autoread_exclude_extensions "" -#@ -#@ set bus_minus_style "-%d" -#@ set hdlin_latch_always_async_set_reset FALSE -#@ set hdlin_ff_always_sync_set_reset FALSE -#@ set hdlin_ff_always_async_set_reset TRUE -#@ set hdlin_check_input_netlist FALSE -#@ set hdlin_check_no_latch FALSE -#@ set hdlin_mux_for_array_read_sparseness_limit 90 -#@ set hdlin_infer_mux "default" -#@ set hdlin_mux_oversize_ratio 100 -#@ set hdlin_mux_size_limit 32 -#@ set hdlin_mux_size_only 1 -#@ set hdlin_infer_multibit "default_none" -#@ set hdlin_enable_rtldrc_info "false" -#@ set hdlin_interface_port_ABI 3 -#@ set hdlin_shorten_long_module_name "false" -#@ set hdlin_module_name_limit 256 -#@ set hdlin_enable_assertions "FALSE" -#@ set hdlin_enable_configurations "FALSE" -#@ set hdlin_sv_blackbox_modules "" -#@ set hdlin_sv_tokens "FALSE" -#@ set hdlin_sv_packages "enable" -#@ set hdlin_verification_priority "FALSE" -#@ set hdlin_enable_elaborate_ref_linking "FALSE" -#@ set hdlin_enable_hier_naming "FALSE" -#@ set hdlin_enable_elaborate_update "true" -#@ set hdlin_vhdl_mixed_language_instantiation "FALSE" -#@ set hdl_preferred_license "" -#@ set hdl_keep_licenses "true" -#@ set hlo_resource_allocation "constraint_driven" -#@ set sdfout_top_instance_name "" -#@ set sdfout_time_scale 1.0 -#@ set sdfout_min_rise_net_delay 0. -#@ set sdfout_min_fall_net_delay 0. -#@ set sdfout_min_rise_cell_delay 0. -#@ set sdfout_min_fall_cell_delay 0. -#@ set sdfout_write_to_output "false" -#@ set sdfout_allow_non_positive_constraints "false" -#@ set sdfin_top_instance_name "" -#@ set sdfin_min_rise_net_delay 0. -#@ set sdfin_min_fall_net_delay 0. -#@ set sdfin_min_rise_cell_delay 0. -#@ set sdfin_min_fall_cell_delay 0. -#@ set sdfin_rise_net_delay_type "maximum" -#@ set sdfin_fall_net_delay_type "maximum" -#@ set sdfin_rise_cell_delay_type "maximum" -#@ set sdfin_fall_cell_delay_type "maximum" -#@ set site_info_file ${synopsys_root}/admin/license/site_info -#@ if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ alias site_info sh cat $site_info_file -#@ } else { -#@ alias site_info "sh cat site_info_file" -#@ } -#@ set template_naming_style "%s_%p" -#@ set template_parameter_style "%s%d" -#@ set template_separator_style "_" -#@ set verilogout_equation "false" -#@ set verilogout_ignore_case "false" -#@ set verilogout_no_tri "false" -#@ set verilogout_inout_is_in "false" -#@ set verilogout_single_bit "false" -#@ set verilogout_higher_designs_first "FALSE" -#@ # set verilogout_levelize "FALSE" -#@ set verilogout_include_files {} -#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_" -#@ set verilogout_show_unconnected_pins "FALSE" -#@ set verilogout_no_negative_index "FALSE" -#@ #set enable_2003.03_verilog_reader TRUE -#@ # to have a net instead of 1'b0 and 1'b1 in inouts: -#@ set verilogout_indirect_inout_connection "FALSE" -#@ -#@ # set vhdlout_architecture_name "SYN_%a_%u" -#@ set vhdlout_bit_type "std_logic" -#@ # set vhdlout_bit_type_resolved "TRUE" -#@ set vhdlout_bit_vector_type "std_logic_vector" -#@ # set vhdlout_conversion_functions {} -#@ # set vhdlout_dont_write_types "FALSE" -#@ set vhdlout_equations "FALSE" -#@ set vhdlout_one_name "'1'" -#@ set vhdlout_package_naming_style "CONV_PACK_%d" -#@ set vhdlout_preserve_hierarchical_types "VECTOR" -#@ set vhdlout_separate_scan_in "FALSE" -#@ set vhdlout_single_bit "USER" -#@ set vhdlout_target_simulator "" -#@ set vhdlout_three_state_name "'Z'" -#@ set vhdlout_three_state_res_func "" -#@ # set vhdlout_time_scale 1.0 -#@ set vhdlout_top_configuration_arch_name "A" -#@ set vhdlout_top_configuration_entity_name "E" -#@ set vhdlout_top_configuration_name "CFG_TB_E" -#@ set vhdlout_unknown_name "'X'" -#@ set vhdlout_upcase "FALSE" -#@ set vhdlout_use_packages {IEEE.std_logic_1164} -#@ set vhdlout_wired_and_res_func "" -#@ set vhdlout_wired_or_res_func "" -#@ set vhdlout_write_architecture "TRUE" -#@ set vhdlout_write_components "TRUE" -#@ set vhdlout_write_entity "TRUE" -#@ set vhdlout_write_top_configuration "FALSE" -#@ # set vhdlout_synthesis_off "TRUE" -#@ set vhdlout_zero_name "'0'" -#@ #set vhdlout_levelize "FALSE" -#@ set vhdlout_dont_create_dummy_nets "FALSE" -#@ set vhdlout_follow_vector_direction "TRUE" -#@ -#@ -#@ # vhdl netlist reader variables -#@ set enable_vhdl_netlist_reader "FALSE" -#@ -#@ # variables pertaining to VHDL library generation -#@ set vhdllib_timing_mesg "true" -#@ set vhdllib_timing_xgen "false" -#@ set vhdllib_timing_checks "true" -#@ set vhdllib_negative_constraint "false" -#@ set vhdllib_glitch_handle "true" -#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle" -#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */ -#@ set vhdllib_architecture {VITAL} -#@ set vhdllib_tb_compare 0 -#@ set vhdllib_tb_x_eq_dontcare FALSE -#@ set vhdllib_logic_system "ieee-1164" -#@ set vhdllib_logical_name "" -#@ -#@ # variables pertaining to technology library processing -#@ set read_db_lib_warnings FALSE -#@ set read_translate_msff TRUE -#@ set libgen_max_differences -1 -#@ -#@ # -#@ # Gui Variable Group -#@ # used for design_vision and psyn_gui -#@ # -#@ set gui_auto_start 0 -#@ set gui_start_option_no_windows 0 -#@ group_variable gui_variables "gui_auto_start" -#@ group_variable gui_variables "gui_start_option_no_windows" -#@ -#@ # -#@ # If you like emacs, uncomment the next line -#@ # set text_editor_command "emacs -fn 8x13 %s &" ; -#@ -#@ # You can delete pairs from this list, but you can't add new ones -#@ # unless you also update the UIL files. So, customers can not add -#@ # dialogs to this list, only Synopsys can do that. -#@ # -#@ set view_independent_dialogs { "test_report" " Test Reports " "report_print" " Report " "report_options" " Report Options " "report_win" " Report Output " "manual_page" " Manual Page " } -#@ -#@ # if color Silicon Graphics workstation -#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} { -#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } { -#@ set x11_set_cursor_foreground "magenta" -#@ set view_use_small_cursor "true" -#@ set view_set_selecting_color "white" -#@ } -#@ } -#@ -#@ # if running on an Apollo machine -#@ set found_x11_vendor_string_apollo 0 -#@ set found_arch_apollo 0 -#@ if { [info exists x11_vendor_string]} { -#@ if { $x11_vendor_string == "Apollo "} { -#@ set found_x11_vendor_string_apollo 1 -#@ } -#@ } -#@ if { [info exists arch]} { -#@ if { $arch == "apollo"} { -#@ set found_arch_apollo 1 -#@ } -#@ } -#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} { -#@ set enable_page_mode "false" -#@ } else { -#@ set enable_page_mode "true" -#@ } -#@ -#@ # don't work around this bug on the Apollo -#@ if { $found_x11_vendor_string_apollo == 1} { -#@ set view_extend_thick_lines "false" -#@ } else { -#@ set view_extend_thick_lines "true" -#@ } -#@ -#@ # -#@ # Suffix Variable Group: -#@ # -#@ # Suffixes recognized by the Design Analyzer menu in file choices -#@ # -#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } { -#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added -#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf} -#@ } else { -#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} -#@ } -#@ -#@ set view_analyze_file_suffix {v vhd vhdl} -#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} -#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con} -#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips} -#@ -#@ # -#@ # links_to_layout Variable Group: -#@ # -#@ # These variables affect the read_timing, write_timing -#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design -#@ # commands. -#@ # -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ set auto_wire_load_selection "true" -#@ set compile_create_wire_load_table "false" -#@ } -#@ set rtl_load_resistance_factor 0.0 -#@ -#@ # power Variable Group: -#@ # -#@ # These variables affect the behavior of power optimization and analysis. -#@ # -#@ -#@ set power_keep_license_after_power_commands "false" -#@ set power_rtl_saif_file "power_rtl.saif" -#@ set power_sdpd_saif_file "power_sdpd.saif" -#@ set power_preserve_rtl_hier_names "false" -#@ set power_do_not_size_icg_cells "true" -#@ set power_hdlc_do_not_split_cg_cells "false" -#@ set power_cg_flatten "false" -#@ set power_opto_extra_high_dynamic_power_effort "false" -#@ set power_default_static_probability 0.5 -#@ set power_default_toggle_rate 0.1 -#@ set power_default_toggle_rate_type "fastest_clock" -#@ set power_model_preference "nlpm" -#@ set power_sa_propagation_effort "low" -#@ set power_sa_propagation_verbose "false" -#@ set power_fix_sdpd_annotation "true" -#@ set power_fix_sdpd_annotation_verbose "false" -#@ set power_sdpd_message_tolerance 0.00001 -#@ set do_operand_isolation "false" -#@ set power_cg_module_naming_style "" -#@ set power_cg_cell_naming_style "" -#@ set power_cg_gated_clock_net_naming_style "" -#@ set power_rclock_use_asynch_inputs "false" -#@ set power_rclock_inputs_use_clocks_fanout "true" -#@ set power_rclock_unrelated_use_fastest "true" -#@ set power_lib2saif_rise_fall_pd "false" -#@ set power_min_internal_power_threshold "" -#@ -#@ -#@ # SystemC related variables -#@ set systemcout_levelize "true" -#@ set systemcout_debug_mode "false" -#@ -#@ # ACS Variables -#@ if { [info exists acs_work_dir] } { -#@ set acs_area_report_suffix "area" -#@ set acs_autopart_max_area "0.0" -#@ set acs_autopart_max_percent "0.0" -#@ set acs_budgeted_cstr_suffix "con" -#@ set acs_compile_script_suffix "autoscr" -#@ set acs_constraint_file_suffix "con" -#@ set acs_cstr_report_suffix "cstr" -#@ set acs_db_suffix "db" -#@ set acs_dc_exec "" -#@ set acs_default_pass_name "pass" -#@ set acs_exclude_extensions {} -#@ set acs_exclude_list [list $synopsys_root] -#@ set acs_global_user_compile_strategy_script "default" -#@ set acs_hdl_verilog_define_list {} -#@ set acs_hdl_source {} -#@ set acs_lic_wait 0 -#@ set acs_log_file_suffix "log" -#@ set acs_make_args "set acs_make_args" -#@ set acs_make_exec "gmake" -#@ set acs_makefile_name "Makefile" -#@ set acs_num_parallel_jobs 1 -#@ set acs_override_report_suffix "report" -#@ set acs_override_script_suffix "scr" -#@ set acs_qor_report_suffix "qor" -#@ set acs_timing_report_suffix "tim" -#@ set acs_use_autopartition "false" -#@ set acs_use_default_delays "false" -#@ set acs_user_budgeting_script "budget.scr" -#@ set acs_user_compile_strategy_script_suffix "compile" -#@ set acs_verilog_extensions {.v} -#@ set acs_vhdl_extensions {.vhd} -#@ set acs_work_dir [pwd] -#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 ACS-193 FILE-1 FILE-2 FILE-3 FILE-4 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ] -#@ set ilm_preserve_core_constraints "false" -#@ } -#@ -#@ # -#@ # -#@ # DesignTime Variable Group -#@ # -#@ # The variables which affect the DesignTime timing engine -#@ # -#@ -#@ set case_analysis_log_file "" -#@ set case_analysis_sequential_propagate "false" -#@ set create_clock_no_input_delay "false" -#@ set disable_auto_time_borrow "false" -#@ set disable_case_analysis "false" -#@ set disable_conditional_mode_analysis "false" -#@ set disable_library_transition_degradation "false" -#@ set dont_bind_unused_pins_to_logic_constant "false" -#@ set enable_slew_degradation "true" -#@ set high_fanout_net_pin_capacitance 1.000000 -#@ set high_fanout_net_threshold 1000 -#@ set lib_thresholds_per_lib "true" -#@ set rc_adjust_rd_when_less_than_rnet "true" -#@ set rc_ceff_delay_min_diff_ps 0.250000 -#@ set rc_degrade_min_slew_when_rd_less_than_rnet "false" -#@ set rc_driver_model_max_error_pct 0.160000 -#@ set rc_filter_rd_less_than_rnet "true" -#@ set rc_input_threshold_pct_fall 50.000000 -#@ set rc_input_threshold_pct_rise 50.000000 -#@ set rc_output_threshold_pct_fall 50.000000 -#@ set rc_output_threshold_pct_rise 50.000000 -#@ set rc_rd_less_than_rnet_threshold 0.450000 -#@ set rc_slew_derate_from_library 1.000000 -#@ set rc_slew_lower_threshold_pct_fall 20.000000 -#@ set rc_slew_lower_threshold_pct_rise 20.000000 -#@ set rc_slew_upper_threshold_pct_fall 80.000000 -#@ set rc_slew_upper_threshold_pct_rise 80.000000 -#@ set timing_disable_cond_default_arcs "false" -#@ #timing_enable_multiple_clocks_per_reg is on by default -#@ #set timing_enable_multiple_clocks_per_reg "false" -#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net infeasible_paths} -#@ set timing_self_loops_no_skew "false" -#@ set when_analysis_permitted "true" -#@ set when_analysis_without_case_analysis "false" -#@ -#@ -#@ # -#@ # Variable Group Definitions: -#@ # -#@ # The group_variable() command groups variables for display -#@ # in the "File/Defaults" dialog and defines groups of variables -#@ # for the list() command. -#@ # -#@ -#@ set enable_instances_in_report_net "true" -#@ # Set report options env variables -#@ set view_report_interactive "true" -#@ set view_report_output2file "false" -#@ set view_report_append "true" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ group_variable report_variables "enable_instances_in_report_net" -#@ group_variable report_variables "view_report_interactive" -#@ group_variable report_variables "view_report_output2file" -#@ group_variable report_variables "view_report_append" -#@ -#@ # "links_to_layout" variables are used by multiple commands -#@ # auto_wire_load_selection is also in the "compile" variable group. -#@ group_variable links_to_layout "auto_wire_load_selection" -#@ -#@ # variables starting with "compile" are also in the compile variable group -#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ -#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable links_to_layout "compile_create_wire_load_table" -#@ -#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name" -#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints" -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ # -#@ # to find the XErrorDB and XKeySymDB for X11 file -#@ set motif_files ${synopsys_root}/admin/setup -#@ # set filename for logging input file -#@ set filename_log_file "filenames.log" -#@ # whether to delete the filename log after the normal exits -#@ set exit_delete_filename_log_file "true" -#@ -#@ # executable to fire off RTLA/BCV -#@ set xterm_executable "xterm" -#@ -#@ if { $synopsys_program_name != "ptxr" } { -#@ -#@ # "system" variables are used by multiple commands -#@ group_variable system auto_link_disable -#@ group_variable system auto_link_options -#@ group_variable system command_log_file -#@ group_variable system company -#@ group_variable system compatibility_version -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ group_variable system "dc_shell_status" -#@ } else { -#@ set current_design "" -#@ set current_instance "" -#@ group_variable system "current_design" -#@ group_variable system "current_instance" -#@ } -#@ -#@ group_variable system "designer" -#@ group_variable system "echo_include_commands" -#@ group_variable system "enable_page_mode" -#@ group_variable system "change_names_update_inst_tree" -#@ group_variable system "change_names_dont_change_bus_members" -#@ group_variable system "default_name_rules" -#@ group_variable system "verbose_messages" -#@ group_variable system "link_library" -#@ group_variable system "link_force_case" -#@ group_variable system "search_path" -#@ group_variable system "synthetic_library" -#@ group_variable system "target_library" -#@ group_variable system "uniquify_naming_style" -#@ group_variable system "suppress_errors" -#@ group_variable system "find_converts_name_lists" -#@ group_variable system "filename_log_file" -#@ group_variable system "exit_delete_filename_log_file" -#@ group_variable system "syntax_check_status" -#@ group_variable system "context_check_status" -#@ -#@ #/* "compile" variables are used by the compile command */ -#@ group_variable compile "compile_assume_fully_decoded_three_state_busses" -#@ group_variable compile "compile_no_new_cells_at_top_level" -#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt" -#@ group_variable compile "reoptimize_design_changed_list_file_name" -#@ group_variable compile "compile_create_wire_load_table" -#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt" -#@ group_variable compile "compile_instance_name_prefix" -#@ group_variable compile "compile_instance_name_suffix" -#@ group_variable compile "compile_negative_logic_methodology" -#@ group_variable compile "compile_disable_hierarchical_inverter_opt" -#@ -#@ group_variable compile "port_complement_naming_style" -#@ group_variable compile "auto_wire_load_selection" -#@ group_variable compile "rtl_load_resistance_factor" -#@ group_variable compile "compile_implementation_selection" -#@ group_variable compile "compile_use_low_timing_effort" -#@ group_variable compile "compile_fix_cell_degradation" -#@ group_variable compile "compile_preserve_subdesign_interfaces" -#@ group_variable compile "compile_enable_constant_propagation_with_no_boundary_opt" -#@ group_variable compile "compile_delete_unloaded_sequential_cells" -#@ group_variable compile "enable_recovery_removal_arcs" -#@ group_variable compile "compile_checkpoint_phases" -#@ group_variable compile "compile_cpu_limit" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_all_paths" -#@ group_variable compile "compile_top_acs_partition" -#@ group_variable compile "default_port_connection_class" -#@ group_variable compile "compile_retime_license_behavior" -#@ group_variable compile "dont_touch_nets_with_size_only_cells" -#@ group_variable compile "compile_seqmap_no_scan_cell" -#@ -#@ if { $synopsys_program_name == "dc_shell" && [shell_is_in_topographical_mode] } { -#@ group_variable compile "dct_prioritize_area_correlation" -#@ group_variable compile "compile_error_on_missing_physical_cells" -#@ } -#@ -#@ # "multibit" variables are used by the the multibit mapping functionality -#@ -#@ group_variable multibit "bus_multiple_separator_style" -#@ -#@ # "ilm" variables are used by Interface Logic Model functionality -#@ -#@ group_variable ilm "ilm_ignore_percentage" -#@ -#@ # "estimate" variables are used by the estimate command -#@ # The estimate command also recognizes the "compile" variables. -#@ group_variable estimate "estimate_resource_preference" -#@ -#@ # "synthetic_library" variables -#@ group_variable synlib "cache_dir_chmod_octal" -#@ group_variable synlib "cache_file_chmod_octal" -#@ group_variable synlib "cache_read" -#@ group_variable synlib "cache_read_info" -#@ group_variable synlib "cache_write" -#@ group_variable synlib "cache_write_info" -#@ group_variable synlib "synlib_dont_get_license" -#@ group_variable synlib "synlib_wait_for_design_license" -#@ group_variable synlib "synthetic_library" -#@ -#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands -#@ #group_variable insert_dft "test_default_client_order" -#@ group_variable insert_dft "insert_dft_clean_up" -#@ group_variable insert_dft "insert_test_design_naming_style" -#@ group_variable insert_dft "test_clock_port_naming_style" -#@ group_variable insert_dft "test_default_min_fault_coverage" -#@ group_variable insert_dft "test_scan_clock_a_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_b_port_naming_style" -#@ group_variable insert_dft "test_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style" -#@ group_variable insert_dft "test_scan_enable_port_naming_style" -#@ group_variable insert_dft "test_scan_in_port_naming_style" -#@ group_variable insert_dft "test_scan_out_port_naming_style" -#@ group_variable insert_dft "test_non_scan_clock_port_naming_style" -#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs" -#@ group_variable insert_dft "test_disable_find_best_scan_out" -#@ group_variable insert_dft "test_dont_fix_constraint_violations" -#@ group_variable insert_dft "test_isolate_hier_scan_out" -#@ group_variable insert_dft "test_mode_port_naming_style" -#@ group_variable insert_dft "test_mode_port_inverted_naming_style" -#@ group_variable insert_dft "compile_dont_use_dedicated_scanout" -#@ group_variable insert_dft "test_mux_constant_si" -#@ -#@ # "preview_scan" variables are used by the preview_scan command -#@ group_variable preview_scan "test_preview_scan_shows_cell_types" -#@ group_variable preview_scan "test_scan_link_so_lockup_key" -#@ group_variable preview_scan "test_scan_link_wire_key" -#@ group_variable preview_scan "test_scan_segment_key" -#@ group_variable preview_scan "test_scan_true_key" -#@ -#@ # "bsd" variables are used by the check_bsd and write_bsdl commands -#@ group_variable bsd "test_user_test_data_register_naming_style" -#@ group_variable bsd "test_user_defined_instruction_naming_style" -#@ group_variable bsd "test_bsdl_default_suffix_name" -#@ group_variable bsd "test_bsdl_max_line_length" -#@ group_variable bsd "test_cc_ir_masked_bits" -#@ group_variable bsd "test_cc_ir_value_of_masked_bits" -#@ -#@ group_variable bsd "test_bsd_allow_tolerable_violations" -#@ group_variable bsd "test_bsd_optimize_control_cell" -#@ group_variable bsd "test_bsd_control_cell_drive_limit" -#@ group_variable bsd "test_bsd_manufacturer_id" -#@ group_variable bsd "test_bsd_part_number" -#@ group_variable bsd "test_bsd_version_number" -#@ group_variable bsd "bsd_max_in_switching_limit" -#@ group_variable bsd "bsd_max_out_switching_limit" -#@ -#@ # testmanager variables -#@ group_variable testmanager "multi_pass_test_generation" -#@ -#@ # "testsim" variables -#@ # group_variable testsim "testsim_print_stats_file" -#@ -#@ # "test" variables -#@ group_variable test "test_default_bidir_delay" -#@ group_variable test "test_default_delay" -#@ group_variable test "test_default_period" -#@ group_variable test "test_default_strobe" -#@ group_variable test "test_default_strobe_width" -#@ group_variable test "test_capture_clock_skew" -#@ group_variable test "test_allow_clock_reconvergence" -#@ group_variable test "test_check_port_changes_in_capture" -#@ group_variable test "test_stil_max_line_length" -#@ group_variable test "test_infer_slave_clock_pulse_after_capture" -#@ group_variable test "test_rtldrc_latch_check_style" -#@ group_variable test "test_enable_capture_checks" -#@ -#@ # "write_test" variables are used by the write_test command -#@ group_variable write_test "write_test_formats" -#@ group_variable write_test "write_test_include_scan_cell_info" -#@ group_variable write_test "write_test_input_dont_care_value" -#@ group_variable write_test "write_test_max_cycles" -#@ group_variable write_test "write_test_max_scan_patterns" -#@ group_variable write_test "write_test_pattern_set_naming_style" -#@ group_variable write_test "write_test_scan_check_file_naming_style" -#@ group_variable write_test "write_test_vector_file_naming_style" -#@ group_variable write_test "write_test_round_timing_values" -#@ -#@ group_variable view "test_design_analyzer_uses_insert_scan" -#@ -#@ # "io" variables are used by the read, read_lib, db2sge and write commands -#@ group_variable io "bus_inference_descending_sort" -#@ group_variable io "bus_inference_style" -#@ #group_variable io "db2sge_output_directory" -#@ #group_variable io "db2sge_scale" -#@ #group_variable io "db2sge_overwrite" -#@ #group_variable io "db2sge_display_symbol_names" -#@ #group_variable io "db2sge_display_pin_names" -#@ #group_variable io "db2sge_display_instance_names" -#@ #group_variable io "db2sge_use_bustaps" -#@ #group_variable io "db2sge_use_compound_names" -#@ #group_variable io "db2sge_bit_type" -#@ #group_variable io "db2sge_bit_vector_type" -#@ #group_variable io "db2sge_one_name" -#@ #group_variable io "db2sge_zero_name" -#@ #group_variable io "db2sge_unknown_name" -#@ #group_variable io "db2sge_target_xp" -#@ #group_variable io "db2sge_tcf_package_file" -#@ #group_variable io "db2sge_use_lib_section" -#@ #group_variable io "db2sge_script" -#@ #group_variable io "db2sge_command" -#@ -#@ # group_variable io "equationout_and_sign" -#@ # group_variable io "equationout_or_sign" -#@ # group_variable io "equationout_postfix_negation" -#@ -#@ # group_variable io "lsiin_net_name_prefix" -#@ # group_variable io "lsiout_inverter_cell" -#@ # group_variable io "lsiout_upcase" -#@ -#@ #group_variable io "mentor_bidirect_value" -#@ #group_variable io "mentor_do_path" -#@ #group_variable io "mentor_input_output_property_name" -#@ #group_variable io "mentor_input_value" -#@ #group_variable io "mentor_logic_one_value" -#@ #group_variable io "mentor_logic_zero_one_property_name" -#@ #group_variable io "mentor_logic_zero_value" -#@ #group_variable io "mentor_output_value" -#@ #group_variable io "mentor_primitive_property_name" -#@ #group_variable io "mentor_primitive_property_value" -#@ #group_variable io "mentor_reference_property_name" -#@ #group_variable io "mentor_search_path" -#@ #group_variable io "mentor_write_symbols" -#@ # group_variable io "pla_read_create_flip_flop" -#@ # group_variable io "tdlout_upcase" -#@ group_variable io "write_name_nets_same_as_ports" -#@ -#@ # # [wjchen] 2006/08/14: The following 4 variables are obsoleted for DC simpilification. -#@ -#@ # group_variable io "xnfout_constraints_per_endpoint" -#@ # group_variable io "xnfout_default_time_constraints" -#@ # group_variable io "xnfout_clock_attribute_style" -#@ # group_variable io "xnfout_library_version" -#@ -#@ # # [wjchen] 2006/08/11: The following 8 variables are obsoleted for DC simpilification. -#@ # group_variable io "xnfin_family" -#@ # group_variable io "xnfin_ignore_pins" -#@ # group_variable io "xnfin_dff_reset_pin_name" -#@ # group_variable io "xnfin_dff_set_pin_name" -#@ # group_variable io "xnfin_dff_clock_enable_pin_name" -#@ # group_variable io "xnfin_dff_data_pin_name" -#@ # group_variable io "xnfin_dff_clock_pin_name" ; -#@ # group_variable io "xnfin_dff_q_pin_name"; -#@ -#@ group_variable io "sdfin_min_rise_net_delay" ; -#@ group_variable io "sdfin_min_fall_net_delay" ; -#@ group_variable io "sdfin_min_rise_cell_delay" ; -#@ group_variable io "sdfin_min_fall_cell_delay" ; -#@ group_variable io "sdfin_rise_net_delay_type" ; -#@ group_variable io "sdfin_fall_net_delay_type" ; -#@ group_variable io "sdfin_rise_cell_delay_type" ; -#@ group_variable io "sdfin_fall_cell_delay_type" ; -#@ group_variable io "sdfin_top_instance_name" ; -#@ group_variable io "sdfout_time_scale" ; -#@ group_variable io "sdfout_write_to_output" ; -#@ group_variable io "sdfout_top_instance_name" ; -#@ group_variable io "sdfout_min_rise_net_delay" ; -#@ group_variable io "sdfout_min_fall_net_delay" ; -#@ group_variable io "sdfout_min_rise_cell_delay" ; -#@ group_variable io "sdfout_min_fall_cell_delay" ; -#@ group_variable io "read_db_lib_warnings" ; -#@ group_variable io "read_translate_msff" ; -#@ group_variable io "libgen_max_differences" ; -#@ -#@ # #[wjchen] 2006/08/22: The following variables are hidden for XG mode for DC simpilification. -#@ # group_variable io "read_name_mapping_nowarn_libraries" ; -#@ # group_variable io "write_name_mapping_nowarn_libraries" ; -#@ -#@ -#@ # "edif" variables are used by the EDIF format read, read_lib, write, -#@ # and write_lib commands -#@ # group_variable edif "bus_dimension_separator_style" ; -#@ # group_variable edif "bus_extraction_style" ; -#@ group_variable edif "bus_inference_descending_sort" ; -#@ group_variable edif "bus_inference_style" ; -#@ group_variable edif "bus_naming_style" ; -#@ group_variable edif "bus_range_separator_style" ; -#@ # group_variable edif "edifin_autoconnect_offpageconnectors" ; -#@ # group_variable edif "edifin_autoconnect_ports" ; -#@ # group_variable edif "edifin_delete_empty_cells" ; -#@ # group_variable edif "edifin_delete_ripper_cells" ; -#@ # group_variable edif "edifin_ground_net_name" ; -#@ # group_variable edif "edifin_ground_net_property_name" ; -#@ # group_variable edif "edifin_ground_net_property_value" ; -#@ # group_variable edif "edifin_ground_port_name" ; -#@ # group_variable edif "edifin_instance_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifin_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifin_portinstance_property_name" ; -#@ # group_variable edif "edifin_power_net_name" ; -#@ # group_variable edif "edifin_power_net_property_name" ; -#@ # group_variable edif "edifin_power_net_property_value" ; -#@ # group_variable edif "edifin_power_port_name" ; -#@ # group_variable edif "edifin_use_identifier_in_rename" ; -#@ # group_variable edif "edifin_view_identifier_property_name" ; -#@ # group_variable edif "edifin_dc_script_flag" ; -#@ # group_variable edif "edifin_lib_logic_1_symbol" ; -#@ # group_variable edif "edifin_lib_logic_0_symbol" ; -#@ # group_variable edif "edifin_lib_in_port_symbol" ; -#@ # group_variable edif "edifin_lib_out_port_symbol" ; -#@ # group_variable edif "edifin_lib_inout_port_symbol" ; -#@ # group_variable edif "edifin_lib_in_osc_symbol" ; -#@ # group_variable edif "edifin_lib_out_osc_symbol" ; -#@ # group_variable edif "edifin_lib_inout_osc_symbol" ; -#@ # group_variable edif "edifin_lib_mentor_netcon_symbol" ; -#@ # group_variable edif "edifin_lib_ripper_bits_property" ; -#@ # group_variable edif "edifin_lib_ripper_bus_end" ; -#@ # group_variable edif "edifin_lib_ripper_cell_name" ; -#@ # group_variable edif "edifin_lib_ripper_view_name" ; -#@ # group_variable edif "edifin_lib_route_grid" ; -#@ # group_variable edif "edifin_lib_templates" ; -#@ # group_variable edif "edifout_dc_script_flag" ; -#@ # group_variable edif "edifout_design_name" ; -#@ # group_variable edif "edifout_designs_library_name" ; -#@ # group_variable edif "edifout_display_instance_names" ; -#@ # group_variable edif "edifout_display_net_names" ; -#@ # group_variable edif "edifout_external" ; -#@ # group_variable edif "edifout_external_graphic_view_name" ; -#@ # group_variable edif "edifout_external_netlist_view_name" ; -#@ # group_variable edif "edifout_external_schematic_view_name" ; -#@ # group_variable edif "edifout_ground_name" ; -#@ # group_variable edif "edifout_ground_net_name" ; -#@ # group_variable edif "edifout_ground_net_property_name" ; -#@ # group_variable edif "edifout_ground_net_property_value" ; -#@ # group_variable edif "edifout_ground_pin_name" ; -#@ # group_variable edif "edifout_ground_port_name" ; -#@ # group_variable edif "edifout_instance_property_name" ; -#@ # group_variable edif "edifout_instantiate_ports" ; -#@ # group_variable edif "edifout_library_graphic_view_name" ; -#@ # group_variable edif "edifout_library_netlist_view_name" ; -#@ # group_variable edif "edifout_library_schematic_view_name" ; -#@ # group_variable edif "edifout_merge_libraries" ; -#@ # group_variable edif "edifout_multidimension_arrays" ; -#@ # group_variable edif "edifout_name_oscs_different_from_ports" ; -#@ # group_variable edif "edifout_name_rippers_same_as_wires" ; -#@ # group_variable edif "edifout_netlist_only" ; -#@ # group_variable edif "edifout_no_array" ; -#@ # group_variable edif "edifout_numerical_array_members" ; -#@ # group_variable edif "edifout_pin_direction_property_name" ; -#@ # group_variable edif "edifout_pin_direction_in_value" ; -#@ # group_variable edif "edifout_pin_direction_inout_value" ; -#@ # group_variable edif "edifout_pin_direction_out_value" ; -#@ # group_variable edif "edifout_pin_name_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_name" ; -#@ # group_variable edif "edifout_portinstance_disabled_property_value" ; -#@ # group_variable edif "edifout_portinstance_property_name" -#@ # group_variable edif "edifout_power_and_ground_representation" -#@ # group_variable edif "edifout_power_name" -#@ # group_variable edif "edifout_power_net_name" -#@ # group_variable edif "edifout_power_net_property_name" -#@ # group_variable edif "edifout_power_net_property_value" -#@ # group_variable edif "edifout_power_pin_name" -#@ # group_variable edif "edifout_power_port_name" -#@ # group_variable edif "edifout_skip_port_implementations" -#@ # group_variable edif "edifout_target_system" -#@ # group_variable edif "edifout_top_level_symbol" -#@ # group_variable edif "edifout_translate_origin" -#@ # group_variable edif "edifout_unused_property_value" -#@ # group_variable edif "edifout_write_attributes" -#@ # group_variable edif "edifout_write_constraints" -#@ # group_variable edif "edifout_write_properties_list" -#@ # group_variable edif "write_name_nets_same_as_ports" -#@ -#@ # "hdl" variables are variables pertaining to hdl reading and optimizing -#@ group_variable hdl "bus_dimension_separator_style" -#@ group_variable hdl "bus_minus_style" -#@ group_variable hdl "bus_naming_style" -#@ group_variable hdl "hdlin_ignore_textio_constructs" -#@ group_variable hdl "hdlin_latch_always_async_set_reset" -#@ group_variable hdl "hdlin_ff_always_sync_set_reset" -#@ group_variable hdl "hdlin_ff_always_async_set_reset" -#@ group_variable hdl "hdlin_check_input_netlist" -#@ group_variable hdl "hdlin_check_no_latch" -#@ group_variable hdl "hdlin_reporting_level" -#@ group_variable hdl "hdlin_infer_mux" -#@ group_variable hdl "hdlin_mux_oversize_ratio" -#@ group_variable hdl "hdlin_mux_size_limit" -#@ group_variable hdl "hdlin_infer_multibit" -#@ group_variable hdl "hdl_preferred_license" -#@ group_variable hdl "hdl_keep_licenses" -#@ group_variable hdl "hlo_resource_allocation" -#@ group_variable hdl "template_naming_style" -#@ group_variable hdl "template_parameter_style" -#@ group_variable hdl "template_separator_style" -#@ group_variable hdl "verilogout_equation" -#@ group_variable hdl "verilogout_ignore_case" -#@ group_variable hdl "verilogout_no_tri" -#@ group_variable hdl "verilogout_inout_is_in" -#@ group_variable hdl "verilogout_single_bit" -#@ group_variable hdl "verilogout_higher_designs_first" -#@ # group_variable hdl "verilogout_levelize" -#@ group_variable hdl "verilogout_include_files" -#@ group_variable hdl "verilogout_unconnected_prefix" -#@ group_variable hdl "verilogout_show_unconnected_pins" -#@ group_variable hdl "verilogout_no_negative_index" -#@ group_variable hdl "hdlin_enable_rtldrc_info" -#@ group_variable hdl "hdlin_sv_blackbox_modules" -#@ group_variable hdl "hdlin_sv_enable_rtl_attributes" -#@ group_variable hdl "hdlin_enable_hier_map" -#@ group_variable hdl "hdlin_sv_interface_only_modules" -#@ group_variable hdl "hdlin_infer_function_local_latches" -#@ group_variable hdl "hdlin_module_arch_name_splitting" -#@ group_variable hdl "hdlin_mux_size_min" -#@ group_variable hdl "hdlin_prohibit_nontri_multiple_drivers" -#@ group_variable hdl "hdlin_subprogram_default_values" -#@ group_variable hdl "hdlin_upcase_names" -#@ group_variable hdl "hdlin_vhdl_std" -#@ group_variable hdl "hdlin_vhdl93_concat" -#@ group_variable hdl "hdlin_vhdl_syntax_extensions" -#@ group_variable hdl "hdlin_vrlg_std" -#@ group_variable hdl "hdlin_while_loop_iterations" -#@ group_variable hdl "hdlin_auto_save_templates" -#@ group_variable hdl "hdlin_elab_errors_deep" -#@ group_variable hdl "hdlin_enable_assertions" -#@ group_variable hdl "hdlin_enable_configurations" -#@ group_variable hdl "hdlin_field_naming_style" -#@ group_variable hdl "hdlin_generate_naming_style" -#@ group_variable hdl "hdlin_generate_separator_style" -#@ group_variable hdl "hdlin_enable_relative_placement" -#@ group_variable hdl "hdlin_mux_rp_limit" -#@ group_variable hdl "hdlin_keep_signal_name" -#@ group_variable hdl "hdlin_module_name_limit" -#@ group_variable hdl "hdlin_mux_size_only" -#@ group_variable hdl "hdlin_preserve_sequential" -#@ group_variable hdl "hdlin_presto_cell_name_prefix" -#@ group_variable hdl "hdlin_presto_net_name_prefix" -#@ group_variable hdl "hdlin_strict_verilog_reader" -#@ group_variable hdl "hdlin_shorten_long_module_name" -#@ group_variable hdl "hdlin_sv_packages" -#@ group_variable hdl "hdlin_sv_tokens" -#@ group_variable hdl "hdlin_enable_elaborate_ref_linking" -#@ group_variable hdl "hdlin_enable_hier_naming" -#@ group_variable hdl "hdlin_enable_elaborate_update" -#@ group_variable hdl "hdlin_autoread_verilog_extensions" -#@ group_variable hdl "hdlin_autoread_sverilog_extensions" -#@ group_variable hdl "hdlin_autoread_vhdl_extensions" -#@ group_variable hdl "hdlin_autoread_exclude_extensions" -#@ group_variable hdl "hdlin_enable_upf_compatible_naming" -#@ group_variable hdl "hdlin_report_sequential_pruning" -#@ group_variable hdl "hdlin_analyze_verbose_mode" -#@ -#@ # "vhdlio" variables are variables pertaining to VHDL generation -#@ group_variable vhdlio "vhdllib_timing_mesg" -#@ group_variable vhdlio "vhdllib_timing_xgen" -#@ group_variable vhdlio "vhdllib_timing_checks" -#@ group_variable vhdlio "vhdllib_negative_constraint" -#@ group_variable vhdlio "vhdllib_pulse_handle" -#@ group_variable vhdlio "vhdllib_glitch_handle" -#@ group_variable vhdlio "vhdllib_architecture" -#@ group_variable vhdlio "vhdllib_tb_compare" -#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare" -#@ group_variable vhdlio "vhdllib_logic_system" -#@ group_variable vhdlio "vhdllib_logical_name" -#@ -#@ # group_variable vhdlio "vhdlout_architecture_name" -#@ group_variable vhdlio "vhdlout_bit_type" -#@ # group_variable vhdlio "vhdlout_bit_type_resolved" -#@ group_variable vhdlio "vhdlout_bit_vector_type" -#@ # group_variable vhdlio "vhdlout_conversion_functions" -#@ # group_variable vhdlio "vhdlout_dont_write_types" -#@ group_variable vhdlio "vhdlout_equations" -#@ group_variable vhdlio "vhdlout_one_name" -#@ group_variable vhdlio "vhdlout_package_naming_style" -#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types" -#@ group_variable vhdlio "vhdlout_separate_scan_in" -#@ group_variable vhdlio "vhdlout_single_bit" -#@ group_variable vhdlio "vhdlout_target_simulator" -#@ group_variable vhdlio "vhdlout_top_configuration_arch_name" -#@ group_variable vhdlio "vhdlout_top_configuration_entity_name" -#@ group_variable vhdlio "vhdlout_top_configuration_name" -#@ group_variable vhdlio "vhdlout_three_state_name" -#@ group_variable vhdlio "vhdlout_three_state_res_func" -#@ # group_variable vhdlio "vhdlout_time_scale" -#@ group_variable vhdlio "vhdlout_unknown_name" -#@ group_variable vhdlio "vhdlout_use_packages" -#@ group_variable vhdlio "vhdlout_wired_and_res_func" -#@ group_variable vhdlio "vhdlout_wired_or_res_func" -#@ group_variable vhdlio "vhdlout_write_architecture" -#@ group_variable vhdlio "vhdlout_write_entity" -#@ group_variable vhdlio "vhdlout_write_top_configuration" -#@ # group_variable vhdlio "vhdlout_synthesis_off" -#@ group_variable vhdlio "vhdlout_write_components" -#@ group_variable vhdlio "vhdlout_zero_name" -#@ # group_variable vhdlio "vhdlout_levelize" -#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets" -#@ group_variable vhdlio "vhdlout_follow_vector_direction" -#@ -#@ # "suffix" variables are used to find the suffixes of different file types -#@ group_variable suffix "view_execute_script_suffix" -#@ group_variable suffix "view_read_file_suffix" -#@ group_variable suffix "view_analyze_file_suffix" -#@ group_variable suffix "view_write_file_suffix" -#@ -#@ # Meenakshi: Added new group scc (for SystemC compiler) -#@ group_variable scc {systemcout_levelize} -#@ group_variable scc {systemcout_debug_mode} -#@ -#@ # "power" variables are for power-analysis. -#@ group_variable power {power_keep_license_after_power_commands} -#@ group_variable power {power_preserve_rtl_hier_names} -#@ group_variable power {power_do_not_size_icg_cells} -#@ group_variable power {power_hdlc_do_not_split_cg_cells} -#@ group_variable power {power_rtl_saif_file} -#@ group_variable power {power_sdpd_saif_file} -#@ group_variable power {power_cg_flatten} -#@ group_variable power {power_opto_extra_high_dynamic_power_effort} -#@ group_variable power {power_default_static_probability} -#@ group_variable power {power_default_toggle_rate} -#@ group_variable power {power_default_toggle_rate_type} -#@ group_variable power {power_model_preference} -#@ group_variable power {power_sa_propagation_effort} -#@ group_variable power {power_sa_propagation_verbose} -#@ group_variable power {power_fix_sdpd_annotation} -#@ group_variable power {power_fix_sdpd_annotation_verbose} -#@ group_variable power {power_sdpd_message_tolerance} -#@ group_variable power {power_rclock_use_asynch_inputs} -#@ group_variable power {power_rclock_inputs_use_clocks_fanout} -#@ group_variable power {power_rclock_unrelated_use_fastest} -#@ group_variable power {power_lib2saif_rise_fall_pd} -#@ group_variable power {power_min_internal_power_threshold} -#@ group_variable power {power_cg_module_naming_style} -#@ group_variable power {power_cg_cell_naming_style} -#@ group_variable power {power_cg_gated_clock_net_naming_style} -#@ group_variable power {do_operand_isolation} -#@ -#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM -#@ -#@ if { [info exists dpcm_debuglevel] } { -#@ group_variable dpcm "dpcm_debuglevel" -#@ group_variable dpcm "dpcm_rulespath" -#@ group_variable dpcm "dpcm_rulepath" -#@ group_variable dpcm "dpcm_tablepath" -#@ group_variable dpcm "dpcm_libraries" -#@ group_variable dpcm "dpcm_version" -#@ group_variable dpcm "dpcm_level" -#@ group_variable dpcm "dpcm_temperaturescope" -#@ group_variable dpcm "dpcm_voltagescope" -#@ group_variable dpcm "dpcm_functionscope" -#@ group_variable dpcm "dpcm_wireloadscope" -#@ group_variable dpcm "dpcm_slewlimit" -#@ group_variable dpcm "dpcm_arc_sense_mapping" -#@ -#@ } -#@ -#@ set dpcm_slewlimit "TRUE" -#@ -#@ # executable to fire off RTLA/BCV -#@ group_variable hdl {xterm_executable} -#@ -#@ # Variable group for Chip Compiler -#@ if {[info exists acs_work_dir]} { -#@ group_variable acs acs_area_report_suffix -#@ group_variable acs acs_autopart_max_area -#@ group_variable acs acs_autopart_max_percent -#@ group_variable acs acs_budgeted_cstr_suffix -#@ group_variable acs acs_compile_script_suffix -#@ group_variable acs acs_constraint_file_suffix -#@ group_variable acs acs_cstr_report_suffix -#@ group_variable acs acs_db_suffix -#@ group_variable acs acs_dc_exec -#@ group_variable acs acs_default_pass_name -#@ group_variable acs acs_exclude_extensions -#@ group_variable acs acs_exclude_list -#@ group_variable acs acs_global_user_compile_strategy_script -#@ group_variable acs acs_hdl_verilog_define_list -#@ group_variable acs acs_hdl_source -#@ group_variable acs acs_lic_wait -#@ group_variable acs acs_log_file_suffix -#@ group_variable acs acs_make_args -#@ group_variable acs acs_make_exec -#@ group_variable acs acs_makefile_name -#@ group_variable acs acs_num_parallel_jobs -#@ group_variable acs acs_override_report_suffix -#@ group_variable acs acs_override_script_suffix -#@ group_variable acs acs_qor_report_suffix -#@ group_variable acs acs_timing_report_suffix -#@ group_variable acs acs_use_autopartition -#@ group_variable acs acs_use_default_delays -#@ group_variable acs acs_user_budgeting_script -#@ group_variable acs acs_user_compile_strategy_script_suffix -#@ group_variable acs acs_verilog_extensions -#@ group_variable acs acs_vhdl_extensions -#@ group_variable acs acs_work_dir -#@ group_variable acs check_error_list -#@ group_variable acs ilm_preserve_core_constraints -#@ -#@ } -#@ -#@ # -#@ # DesignTime Variable Group timing -#@ # -#@ -#@ group_variable timing case_analysis_log_file -#@ group_variable timing case_analysis_sequential_propagate -#@ group_variable timing case_analysis_with_logic_constants -#@ group_variable timing create_clock_no_input_delay -#@ group_variable timing disable_auto_time_borrow -#@ group_variable timing disable_case_analysis -#@ group_variable timing disable_conditional_mode_analysis -#@ group_variable timing disable_library_transition_degradation -#@ group_variable timing dont_bind_unused_pins_to_logic_constant -#@ group_variable timing enable_slew_degradation -#@ group_variable timing high_fanout_net_pin_capacitance -#@ group_variable timing high_fanout_net_threshold -#@ group_variable timing lib_thresholds_per_lib -#@ group_variable timing rc_adjust_rd_when_less_than_rnet -#@ group_variable timing rc_ceff_delay_min_diff_ps -#@ group_variable timing rc_degrade_min_slew_when_rd_less_than_rnet -#@ group_variable timing rc_driver_model_max_error_pct -#@ group_variable timing rc_filter_rd_less_than_rnet -#@ group_variable timing rc_input_threshold_pct_fall -#@ group_variable timing rc_input_threshold_pct_rise -#@ group_variable timing rc_output_threshold_pct_fall -#@ group_variable timing rc_output_threshold_pct_rise -#@ group_variable timing rc_rd_less_than_rnet_threshold -#@ group_variable timing rc_slew_derate_from_library -#@ group_variable timing rc_slew_lower_threshold_pct_fall -#@ group_variable timing rc_slew_lower_threshold_pct_rise -#@ group_variable timing rc_slew_upper_threshold_pct_fall -#@ group_variable timing rc_slew_upper_threshold_pct_rise -#@ group_variable timing timing_disable_cond_default_arcs -#@ # group_variable timing timing_enable_multiple_clocks_per_reg -#@ group_variable timing timing_report_attributes -#@ group_variable timing timing_self_loops_no_skew -#@ group_variable timing when_analysis_permitted -#@ group_variable timing when_analysis_without_case_analysis -#@ -#@ } ;# $synopsys_program_name != "ptxr" -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compile Variable Group: -#@ # -#@ # These variables affect the designs created by the route_opt command. -#@ # -#@ group_variable routeopt routeopt_checkpoint -#@ group_variable routeopt routeopt_disable_cpulimit -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # -#@ # IC Compiler Variable Group: MCMM -#@ # -#@ # These variables affect Multi-Corner/Multi-Mode. Currently, MCMM is -#@ # only supported in ICC--hence the "icc_shell" qualification, above -#@ # -#@ group_variable MCMM mcmm_enable_high_capacity_flow -#@ } -#@ -#@ # Aliases for backwards compatibility or other reasons -#@ group_variable compile {compile_log_format} -#@ alias view_cursor_number x11_set_cursor_number -#@ alias set_internal_load set_load -#@ alias set_internal_arrival set_arrival -#@ alias set_connect_delay "set_annotated_delay -net" -#@ alias create_test_vectors create_test_patterns -#@ alias compile_test insert_test -#@ alias check_clocks check_timing -#@ alias lint check_design -#@ # gen removed; alias gen create_schematic -#@ alias free remove_design -#@ alias group_bus create_bus -#@ alias ungroup_bus remove_bus -#@ alias groupvar group_variable -#@ alias report_constraints report_constraint -#@ alias report_attributes report_attribute -#@ alias fsm_reduce reduce_fsm -#@ alias fsm_minimize minimize_fsm -#@ alias disable_timing set_disable_timing -#@ alias dont_touch set_dont_touch -#@ alias dont_touch_network set_dont_touch_network -#@ alias dont_use set_dont_use -#@ alias fix_hold set_fix_hold -#@ alias prefer set_prefer -#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" -#@ alias analyze_scan preview_scan -#@ alias get_clock get_clocks -#@ alias dc_shell_is_in_incr_mode shell_is_in_xg_mode -#@ alias set_vh_module_options set_dps_module_options -#@ alias set_vh_physopt_options set_dps_options -#@ alias update_vh_design update_dps_design -#@ alias vh_start dps_start -#@ alias vh_end dps_end -#@ alias all_vh_modules all_dps_modules -#@ alias all_designs_of_vh all_designs_of_dps -#@ alias vh_use_auto_partitioning dps_auto_partitioning -#@ alias vh_write_changes dps_write_changes -#@ alias vh_read_changes dps_read_changes -#@ alias vh_write_module_clock dps_write_module_clock -#@ alias get_lib get_libs -#@ -#@ # Enable unsupported psyn commands -#@ if { $synopsys_program_name == "psyn_shell" || $synopsys_program_name == "icc_shell"} { -#@ proc enable_unsupported_commands { { arg "default" } } { -#@ global cgpi_use_new_wire_factors -#@ global cgpi_use_relative_wire_factors -#@ global cgpi_use_new_path_factors -#@ global pwlm_use_new_wire_factors -#@ global pwlm_use_relative_wire_factors -#@ global pwlm_use_new_path_factors -#@ global psyn_unsupported_commands_dir -#@ global synopsys_root -#@ if {![info exists psyn_unsupported_commands_dir]} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ } -#@ set psyn_unsupported_commands_option1 $arg -#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} { -#@ source $psyn_unsupported_commands_dir/setup.tcl -#@ } else { -#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e -#@ } -#@ } -#@ } -#@ # For Intel -#@ if { $synopsys_program_name == "icc_shell"} { -#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands -#@ source -encrypted $psyn_unsupported_commands_dir/max_dist.tcl.e -#@ } -#@ -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ # to enable CLE readline-ish terminal by default for ICC -#@ set sh_enable_line_editing true -#@ -#@ # Astro forms create an enormous number of new variables which are -#@ # very annoying for users to see, so the default of this variable -#@ # for ICC is false -#@ set sh_new_variable_message false -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell" || (($synopsys_program_name == "dc_shell") && ([shell_is_in_topographical_mode])) } { -#@ source $synopsys_root/auxx/syn/psyn/verify_ilm.tcl -#@ } -#@ -#@ # Enable vh psyn commands -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ proc enable_vh_flow { } { -#@ global VH_SCRIPT_FILE -#@ global synopsys_root -#@ global suppress_errors -#@ set suppress_errors "$suppress_errors CMD-041 UID-95 SEL-003 SEL-005" -#@ if {![info exists VH_SCRIPT_FILE]} { -#@ set VH_SCRIPT_FILE $synopsys_root/auxx/syn/psyn/vh_pc.tcl.e -#@ } -#@ if {[file readable $VH_SCRIPT_FILE]} { -#@ if {[string match *.tcl $VH_SCRIPT_FILE]} { -#@ source $VH_SCRIPT_FILE -#@ } else { -#@ source -encrypted $VH_SCRIPT_FILE -#@ } -#@ } else { -#@ puts "Error: VH script file $VH_SCRIPT_FILE not found." -#@ } -#@ } -#@ } -#@ -#@ -#@ #Turn on enable_netl_view to true by default. -#@ set enable_netl_view "TRUE" -#@ -#@ -#@ #Turn on physopt_bypass_multiple_plib_check by default -#@ if { $synopsys_program_name == "psyn_shell" } { -#@ set physopt_bypass_multiple_plib_check TRUE -#@ } -#@ -#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } { -#@ alias ls "sh ls -a " -#@ } else { -#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } { -#@ alias ls "sh ls -aC " -#@ } else { -#@ alias ls "sh ls -aC " -#@ } -#@ } -#@ } -#@ -#@ # Aliases for RouteCompiler -#@ alias run_rodeo_router route66 -#@ -#@ # Removing route_global from the code. Earlier it was hidden. --Mukesh -#@ #proc route_global {} { -#@ # global route_global_keep_tmp_data -#@ # global rt66_dont_lock_dir -#@ # -#@ # set rt66_dont_lock_dir TRUE -#@ # -#@ # for { set i 0} {1==1} {incr i} { -#@ # set wdir [file join [pwd] ".route_global.$i"] -#@ # if {[file exist $wdir] == 0} { -#@ # break; -#@ # } -#@ # } -#@ # -#@ # set_routing_options -cut_out_covered_port CORE_ONLY -#@ # set_routing_options -internal_routing FALSE -#@ # set_routing_options -stick_routing FALSE -#@ # -#@ # ###puts "wdir = $wdir" -#@ # -#@ # set success [route66 -global -dontstop -dir $wdir] -#@ # -#@ # #clean tmp data if required: -#@ # if { $success == 1 } { -#@ # if [catch {string toupper $route_global_keep_tmp_data} result] { -#@ # #variable is not defined -#@ # ###puts "result_1 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } else { -#@ # #variable is set to FALSE -#@ # if { [string compare $result "TRUE"] != 0} { -#@ # ###puts "result_2 = $result => removing dir ..." -#@ # catch { file delete -force $wdir } -#@ # } -#@ # } -#@ # } -#@ # -#@ # set rt66_dont_lock_dir FALSE -#@ # return 1 -#@ #} -#@ #define_proc_attributes route_global -hidden -#@ -#@ #/* Aliases added for report command */ -#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" -#@ alias report_clock_fanout "report_transitive_fanout -clock_tree" -#@ alias report_clocks report_clock -#@ alias report_synthetic report_cell -#@ -#@ # Alias added for Ultra backward compatibility mode -#@ alias set_ultra_mode set_ultra_optimization -#@ -#@ # alias for write_sge and menu item in DA for db2sge -#@ -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl -#@ #} else { -#@ # set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge -#@ #} -#@ -#@ #set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge -#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge" -#@ -#@ -#@ if { $synopsys_program_name != "lc_shell"} { -#@ # read schematic annotation setup file -#@ #source ${synopsys_root}/admin/setup/.dc_annotate -#@ -#@ # setup the default layer settings -#@ #source ${synopsys_root}/admin/setup/.dc_layers -#@ -#@ if {$synopsys_program_name != "dc_sms_shell"} { -#@ source ${synopsys_root}/admin/setup/.dc_name_rules -#@ } -#@ } else { -#@ #for read_lib -html -#@ source ${synopsys_root}/auxx/syn/lc/read_lib_html_msg_list.tcl -#@ } -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.dc_name_rules - -#@ # -#@ -#@ # .dc_name_rules Initialization file for -#@ -#@ # Dc_Shell and Design_Analyzer -#@ -#@ # This files defines name rules for target systems. Change_names -#@ # will use this rules to fix the object names. -#@ -#@ #*/ -#@ -#@ -#@ define_name_rules sverilog -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules sverilog -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules sverilog -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules sverilog -reserved { "always" "always_comb" "always_ff" "always_latch" "and" "assert" "assert_strobe" "assign" "automatic" "begin" "bit" "break" "buf" "bufif0" "bufif1" "byte" "case" "casex" "casez" "cell" "changed" "char" "cmos" "config" "const" "continue" "deassign" "default" "defparam" "design" "disable" "do" "edge" "else" "end" "endcase" "endconfig" "endfunction" "endgenerate" "endinterface" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "endtransition" "enum" "event" "export" "extern" "for" "force" "forever" "fork" "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" "iff" "ifnone" "import" "incdir" "include" "initial" "inout" "input" "instance" "int" "integer" "interface" "join" "large" "liblist" "library" "localparam" "logic" "longint" "longreal" "macromodule" "medium" "modport" "module" "nand" "negedge" "nmos" "nor" "noshowcancelled" "not" "notif0" "notif1" "or" "output" "packed" "parameter" "pmos" "posedge" "primitive" "process" "priority" "pull0" "pull1" "pullup" "pulldown" "pulsestyle_onevent" "pulsestyle_ondetect" "rcmos" "real" "realtime" "reg" "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "shortint" "shortreal" "showcancelled" "signed" "small" "specify" "specparam" "static" "strong0" "strong1" "struct" "supply0" "supply1" "table" "task" "time" "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "transition" "tri" "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" "unique" "use" "unsigned" "vectored" "void" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ define_name_rules verilog -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules verilog -reserved { "always" "and" "assign" "automatic" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cell" "cmos" "config" "deassign" "default" "defparam" "design" "disable" "edge" "else" "end" "endcase" "endconfig" "endfunction" "endgenerate" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "generate" "genvar" "highz0" "highz1" "if" "ifnone" "incdir" "include" "initial" "inout" "input" "instance" "integer" "join" "large" "liblist" "library" "localparam" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" "noshowcancelled" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pullup" "pulldown" "pulsestyle_onevent" "pulsestyle_ondetect" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "showcancelled" "signed" "small" "specify" "specparam" "strong0" "strong1" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "unsigned" "use" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ define_name_rules verilog_1995 -type net -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog_1995 -type port -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ -#@ define_name_rules verilog_1995 -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9" -#@ define_name_rules verilog_1995 -reserved { "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cell" "cmos" "deassign" "default" "defparam" "design" "disable" "edge" "else" "end" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "ifnone" "initial" "inout" "input" "integer" "join" "large" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pullup" "pulldown" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "small" "specify" "specparam" "strong0" "strong1" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style {%s[%d]} -flatten_multi_dimension_busses -check_internal_net_name -check_bus_indexing -#@ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ ####/* Name rule for VHDL */ -#@ -#@ define_name_rules vhdl -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" \ -#@ "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -target_bus_naming_style "%s(%d)" -replacement_char "x" -special vhdl -#@ define_name_rules vhdl -type net -allowed "A-Z a-z _ 0-9 " -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -type port -allowed "A-Z a-z _ 0-9 " -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -type cell -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_" -#@ define_name_rules vhdl -map { {{"__","_"},{"_$",""}} } -#@ -#@ ####/* Name rule for VHDL */ -#@ # -- End source /EDA/Synopsys/syn/O-2018.06-SP1/admin/setup/.dc_name_rules - -#@ -#@ if { $synopsys_program_name == "psyn_gui"} { -#@ # read RouteCompiler GUI file for timing critical pathes. -#@ source ${synopsys_root}/auxx/syn/route_gui/write_route_timing_path.tcl -#@ } -#@ -#@ # Set physopt_dw_opto to false -#@ if { [string match -nocase {*icc_shell*} $synopsys_program_name] } { -#@ set physopt_dw_opto FALSE -#@ } -#@ -#@ #/* Read budgeting setup script */ -#@ -#@ if { [string compare $dc_shell_mode "default"] == 0 } { -#@ -#@ # Need a encrypted file in Tcl format for budget.setup.et -#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } { -#@ # source -e synopsys_root + "/admin/setup/budget.setup.et" -#@ } -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ source $synopsys_root/auxx/syn/.icc_procs.tcl -#@ source -encrypted $synopsys_root/auxx/syn/cts/fast_atomic_cts.tcl.e -#@ } -#@ -#@ if { $synopsys_program_name == "icc_shell"} { -#@ alias report_scenario report_scenarios -#@ } -#@ -#@ # floorplanning preferences globals -#@ global fp_snap_type -#@ -#@ set fp_snap_type(port) wiretrack -#@ set fp_snap_type(cell) litho -#@ set fp_snap_type(pin) wiretrack -#@ set fp_snap_type(movebound) litho -#@ set fp_snap_type(port_shape) wiretrack -#@ set fp_snap_type(wiring_keepout) wiretrack -#@ set fp_snap_type(placement_keepout) litho -#@ set fp_snap_type(net_shape) wiretrack -#@ set fp_snap_type(route_shape) wiretrack -#@ set fp_snap_type(none) litho -#@ -#@ # STAR 9000615813. PWR-18 is no longer internally suppressed. -#@ # Instead call tcl suppress_message so that it can be unsuppressed by users in -#@ # command line if needed -#@ suppress_message PWR-18 -#@ -#@ # alias for write_sge is always the last line of the setup file -#@ #if { [string compare $dc_shell_mode "tcl"] == 0 } { -#@ # alias write_sge "source db2sge_script" -#@ #} else { -#@ # alias write_sge "include db2sge_script" -#@ #} -#@ -#@ if { $dc_shell_mode == "tcl" } { -#@ # Configure Execute script dialog to display .tcl files -#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl" -#@ } -#@ -#@ # -#@ # Shirley Lu 5/15/2007 -#@ # -#@ # Invoke NCX validation/correlation/fomatter from lc_shell: -#@ # -#@ # UNIX shell: -#@ # setenv SYNOPSYS_NCX_ROOT /mydisk/ncx_2007.06 -#@ # -#@ -#@ if {[info exists env(SYNOPSYS_NCX_ROOT)]} { -#@ -#@ set ncx_path $env(SYNOPSYS_NCX_ROOT)/ncx/${sh_arch}/bin -#@ -#@ # -#@ # check_ccs_lib -#@ # use libchecker under $ncx_path defined above -#@ # Disable this command since 2010.12-SP3 (should be done in 2010.12 release) -#@ #proc check_ccs_lib {args} { -#@ # global ncx_path -#@ # set cmdStr [linsert $args 0 ${ncx_path}/libchecker -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ # -#@ # format_lib -#@ # use ncx under $ncx_path defined above -#@ # Disable format_lib command in 2014.09 release -- xwwang, 7/25/2014 -#@ #proc format_lib {args} { -#@ # global ncx_path -#@ # echo "Warning: format_lib command is scheduled to become obsolete in a future production release." -#@ # set cmdStr [linsert $args 0 ${ncx_path}/ncx -lc_shell] -#@ # set cmd [open "| $cmdStr 2>@ stdout"] -#@ # catch { -#@ # while {[gets $cmd info] >= 0} { -#@ # echo $info -#@ # } -#@ # } -#@ # if {[catch {close $cmd} msg]} { -#@ # } -#@ #} -#@ -#@ } -#@ -#@ proc valias {v_orig v_alias} { -#@ uplevel 1 "upvar 0 $v_orig $v_alias" -#@ } -#@ -#@ set lc_run_from_legacy_library_compiler "true" -#@ -#@ set lc_enable_legacy_library_compiler "false" -#@ -#@ valias lc_enable_legacy_library_compiler lc_enable_common_shell_lc -#@ -#@ if {[info exists ::env(SYNOPSYS_LC_ROOT)] && [file exists $::env(SYNOPSYS_LC_ROOT)/$::sh_arch/lc/bin/lc_shell_exec]} { -#@ # make lc man pages search path override the default man page search path -#@ set man_path [linsert $man_path 0 $::env(SYNOPSYS_LC_ROOT)/doc/lc/man] -#@ } else { -#@ set lc_link "$::synopsys_root/$::sh_arch/syn/bin/lc_shell_exec" -#@ while { [file exists $lc_link] && [file type $lc_link] == "link"} { -#@ set lc_link [file readlink $lc_link] -#@ } -#@ # resolve symbol-link to get $exec_path of lc_shell_exec -#@ if { [file exists $lc_link] } { -#@ set LC_ROOT [file dirname [file dirname [file dirname [file dirname $lc_link]]]] -#@ set man_path [linsert $man_path 0 $LC_ROOT/doc/lc/man] -#@ } -#@ } -#@ -#@ source ${synopsys_root}/auxx/syn/lc_commands.tbc -#@ # -- Starting source /EDA/Synopsys/syn/O-2018.06-SP1/auxx/syn/lc_commands.tbc - -#@ ############################################################################## -#@ # Author : Liping Zhao -#@ # History: 2016/11/21 created -#@ # Description: This is the source tcl file of run_nglc.tbc. -#@ # The procs are all for run library compiler under the hood. -#@ # These procs are exracted from .synopsys_dc.setup -#@ ############################################################################## -#@ # TclPro::Compiler::Include -#@ -#@ if {[catch {package require tbcload 1.6} err] == 1} { -#@ return -code error "[info script]: The TclPro ByteCode Loader is not available or does not support the correct version -- $err" -#@ } -#@ tbcload::bceval { -#@ TclPro ByteCode 2 0 1.7 8.5 -#@ 44 0 426 61 0 0 312 0 12 44 44 -1 -1 -#@ 426 -#@ `:G,f=!CM1qv2&|=!A8#>!*BEKs!6#o9v.EW< -#@ !E;kpvJSapvQXxOwI1IOwI1IOwI1IOwI1IOwI1IOwI1IOwI1IOw -#@ 44 -#@ I%%n#;c(;v0g>a'?qwn#I%%n#I%%n#I%%n#I%%n#I%%n#I%%n#Hq^R# -#@ 61 -#@ x -#@ 4 -#@ ,CHr@ -#@ x -#@ 23 -#@ lj|Z?!aiaEw>m#H8&Z)F5mNaEt-E- -#@ x -#@ 1 -#@ A! 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---------------------------------------------------------------------------- -// SpyGlass GuideWare Goal File -// -// Goal Name : dft_scan_ready -// Version : 5.5.0 -// -// Revision History: -// Ver Date Comments -// 5.5.0 11-Jun-2015 Initial version -// Added : Clock_26 -// Added : Info_testmode_conflict_01 -// Added : Info_untestable -// Removed: Info_path -// -// Copyright Synopsys Inc, 2019. All rights reserved. -// ---------------------------------------------------------------------------- - -=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -dft_scan_ready -* -Make registers scannable -* - SpyGlass DFT may be run on RTL designs without any built-in test logic or -on designs with test mode controls and test clocks. In the first case, -SpyGlass will identify the system logic that does not comply with DFT -requirements. In the second case, SpyGlass DFT will verify that the -design-for-test logic is performing correctly as well as identify where -additional design-for-test logic may be required or useful. - - This "scan ready" step is designed to ensure that as many registers in -the RTL as possible can easily be replaced with scan equivalents either -during logic synthesis or in a post-synthesis step. SpyGlass DFT does -not do the scan insertion or scan chain stitching but rather deals with -the clocks and the asynchronous signals to ensure compliance with -scan replacement requirements. - - For more details about this goal, please refer to the -SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your -SpyGlass installation -=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//------------------------------------------------ -// Policy Registration -//------------------------------------------------ - --policies=dft - - -//------------------------------------------------ -// General Setup commands -//------------------------------------------------ - - -//------------------------------------------------ -// Policy Specific Parameter Setting -//------------------------------------------------ - - -//------------------------------------------------ -// Rule Registration -//------------------------------------------------ - --rules Coverage_audit // Analyze coverage for circuit - --rules Info_coverage // Estimate fault and test coverage - --rules Async_07 // Asynchronous set/reset sources should be inactive during shift mode --overloadrules Async_07+msgLabel=Async_07_M1+severity=Error - --rules Async_08 // Asynchronous set/reset pins of all the flops should be fully controllable during capture. - --rules Clock_11 // All clock sources must be testclock controlled in shift mode --overloadrules Clock_11+msgLabel=Clock_11_M1+severity=Error - --rules Clock_11_capture // All clock sources must be testclock controlled in capture mode - --rules Clock_26 // Testclock constraint must not be applied on sensitized fanout of another test clock in Shift or Capture mode - --rules Diagnose_testclock // Display instances that blocks testclock propagation - --rules Diagnose_testmode // Display instances that blocks testmode propagation - --rules Info_forcedScan // Displays all registers and flip-flops specified as 'scan' - --rules Info_inferredNoScan // Displays all flip-flops which have been inferred as no_scan - --rules Info_noScan // Displays all registers and flip-flops specified as 'no_scan' - --rules Info_scanwrap // Report scanwrap related information - --rules Info_testclock // Display test clock propagation - --rules Info_testmode // Display testmode simulation results - --rules Info_testmode_conflict_01 // Display conflict in user specified testmode with respect to simulation result of fanin cone - --rules Info_untestable // Display untestable faults caused by test mode - -//------------------------------------------------ -// End of Rule Registration -//------------------------------------------------ diff --git a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_debug_help.htm b/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_debug_help.htm deleted file mode 100644 index a70ceca..0000000 --- a/src/UWE_projectCode/tmp/tmp/Scripts/custom_methodology/dft/dft_scan_ready_debug_help.htm +++ /dev/null @@ -1,151 +0,0 @@ - - - - - - - - - - dft_scan_ready - - - - - - - - - - - - - -