From 6b9cf3a44830066d070614684bcdeadd6cc1b798 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=BB=84=E7=86=99=E5=93=B2?= Date: Sun, 24 May 2026 22:25:25 +0800 Subject: [PATCH] fix(backend): add x16/x17 to GP allocatable set to fix segfaults Adding x16 and x17 (IP0/IP1, caller-saved) increases GP registers from 16 to 18, reducing register pressure for large functions. Fixes segfaults: 39_fp_params (64 params), 30_many_dimensions (2MB frame). Also improves performance: crc -8, fft0 -4, huffman -12, sl -1 etc. --- src/mir/RegAlloc.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mir/RegAlloc.cpp b/src/mir/RegAlloc.cpp index 6667f033..a8c85d5f 100644 --- a/src/mir/RegAlloc.cpp +++ b/src/mir/RegAlloc.cpp @@ -47,8 +47,8 @@ namespace mir return reg >= PhysReg::S0 && reg <= PhysReg::S31; } - static const int GP_ALLOCATABLE[] = {8, 9, 10, 11, 12, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28}; - static const int GP_NUM_ALLOCATABLE = 16; + static const int GP_ALLOCATABLE[] = {8, 9, 10, 11, 12, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28}; + static const int GP_NUM_ALLOCATABLE = 18; static const int FP_ALLOCATABLE[] = {8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; static const int FP_NUM_ALLOCATABLE = 24; static const int FP_CALLER_SAVED[] = {8, 9, 10, 11, 12, 13, 14, 15};