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#include "mir/MIR.h"
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#include <iostream>
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#include <stdexcept>
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#include <string>
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#include "utils/Log.h"
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namespace mir
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{
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namespace
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{
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std::string NormalizeAsmSymbol(std::string name)
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{
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while (!name.empty() && (name.front() == '@' || name.front() == '%'))
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{
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name.erase(name.begin());
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}
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return name;
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}
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const char *OpcodeToAsm(Opcode opcode)
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{
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switch (opcode)
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{
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::LoadStackAddr:
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case Opcode::LoadGlobal:
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case Opcode::StoreGlobal:
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case Opcode::LoadGlobalAddr:
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case Opcode::LoadMem:
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case Opcode::StoreMem:
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case Opcode::Uxtw:
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case Opcode::Sxtw:
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return "";
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case Opcode::MovImm:
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return "mov";
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case Opcode::LoadStack:
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return "ldur";
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case Opcode::StoreStack:
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return "stur";
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case Opcode::AddRR:
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return "add";
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case Opcode::SubRR:
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return "sub";
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case Opcode::MulRR:
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return "mul";
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case Opcode::DivRR:
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return "sdiv";
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case Opcode::FAddRR:
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return "fadd";
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case Opcode::FSubRR:
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return "fsub";
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case Opcode::FMulRR:
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return "fmul";
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case Opcode::FDivRR:
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return "fdiv";
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case Opcode::ModRR:
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return "msub";
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case Opcode::AndRR:
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return "and";
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case Opcode::OrRR:
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return "orr";
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case Opcode::XorRR:
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return "eor";
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case Opcode::ShlRR:
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return "lsl";
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case Opcode::ShrRR:
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return "lsr";
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case Opcode::CmpRR:
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return "cmp";
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case Opcode::CmpImm:
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return "cmp";
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case Opcode::FCmpRR:
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return "fcmp";
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case Opcode::CSet:
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return "cset";
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case Opcode::Csneg:
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return "csneg";
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case Opcode::Scvtf:
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return "scvtf";
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case Opcode::FCvtzs:
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return "fcvtzs";
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case Opcode::FMovWS:
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return "fmov";
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case Opcode::Br:
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return "b";
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case Opcode::CondBr:
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return "b";
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case Opcode::Call:
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return "bl";
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case Opcode::Ret:
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return "ret";
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case Opcode::LoadAddr:
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return "adrp";
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case Opcode::MovReg:
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return "mov";
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default:
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return "";
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}
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}
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const char *CondCodeToAsm(CondCode cond)
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{
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switch (cond)
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{
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case CondCode::EQ:
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return "eq";
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case CondCode::NE:
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return "ne";
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case CondCode::LT:
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return "lt";
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case CondCode::LE:
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return "le";
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case CondCode::GT:
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return "gt";
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case CondCode::GE:
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return "ge";
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default:
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return "";
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}
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}
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bool IsXReg(PhysReg reg)
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{
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return reg >= PhysReg::X0 && reg <= PhysReg::X30;
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}
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bool IsWReg(PhysReg reg)
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{
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return reg >= PhysReg::W0 && reg <= PhysReg::W30;
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}
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bool IsSReg(PhysReg reg)
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{
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return reg >= PhysReg::S0 && reg <= PhysReg::S31;
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}
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PhysReg PickModQuotientReg(const Operand &dst,
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const Operand &lhs,
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const Operand &rhs)
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{
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const PhysReg candidates[] = {
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PhysReg::W14, PhysReg::W12, PhysReg::W15,
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PhysReg::W11, PhysReg::W10, PhysReg::W9, PhysReg::W8};
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for (PhysReg reg : candidates)
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{
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bool conflict = false;
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for (const Operand *op : {&dst, &lhs, &rhs})
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{
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if (op->GetKind() == Operand::Kind::Reg &&
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IsWReg(op->GetReg()) &&
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op->GetReg() == reg)
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{
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conflict = true;
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break;
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}
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}
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if (!conflict)
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{
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return reg;
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}
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}
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return PhysReg::W14;
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}
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std::string BlockLabel(const MachineFunction &function, int label_id)
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{
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return ".L." + NormalizeAsmSymbol(function.GetName()) + "." +
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std::to_string(label_id);
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}
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void PrintBlockLabelRef(const MachineFunction &function, int label_id,
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std::ostream &os)
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{
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os << BlockLabel(function, label_id);
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}
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void PrintOperand(const Operand &operand, std::ostream &os)
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{
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switch (operand.GetKind())
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{
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case Operand::Kind::Reg:
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os << PhysRegName(operand.GetReg());
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break;
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case Operand::Kind::VReg:
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os << "%vreg" << operand.GetVRegId();
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break;
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case Operand::Kind::Imm:
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os << "#" << operand.GetImm();
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break;
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case Operand::Kind::FrameIndex:
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os << "<fi#" << operand.GetFrameIndex() << ">";
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break;
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case Operand::Kind::Label:
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os << ".L" << operand.GetLabel();
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break;
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case Operand::Kind::Symbol:
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os << NormalizeAsmSymbol(operand.GetSymbol());
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break;
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}
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}
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void EmitLargeImmediate(PhysReg target, int value, std::ostream &os)
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{
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if (value >= -32768 && value <= 65535)
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{
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os << " mov " << PhysRegName(target) << ", #" << value << "\n";
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return;
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}
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const unsigned int uvalue = static_cast<unsigned int>(value);
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bool emitted = false;
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for (int shift = 0; shift < 32; shift += 16)
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{
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const unsigned short part = (uvalue >> shift) & 0xFFFF;
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if (part == 0 && emitted)
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{
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continue;
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}
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if (!emitted)
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{
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os << " movz " << PhysRegName(target) << ", #" << part;
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if (shift > 0)
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{
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os << ", lsl #" << shift;
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}
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os << "\n";
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emitted = true;
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}
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else if (part != 0)
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{
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os << " movk " << PhysRegName(target) << ", #" << part;
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if (shift > 0)
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{
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os << ", lsl #" << shift;
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}
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os << "\n";
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}
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}
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if (!emitted)
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{
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os << " mov " << PhysRegName(target) << ", #0\n";
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}
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}
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void EmitStackAdjust(const char *op, int amount, std::ostream &os)
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{
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while (amount > 0)
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{
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const int chunk = amount > 4095 ? 4095 : amount;
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os << " " << op << " sp, sp, #" << chunk << "\n";
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amount -= chunk;
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}
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}
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PhysReg PrinterScratchXReg()
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{
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// 汇编打印阶段展开伪指令时，需要一个全局保留的 scratch。
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// 不能再复用 x14/x15，否则会把 lowering 已经放好的数组/全局基址冲掉。
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// 当前 lowering 不使用 x13，因此固定保留 x13 给打印阶段使用。
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return PhysReg::X13;
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}
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void EmitAddressFromBase(PhysReg target_xreg, PhysReg base_reg, int offset,
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std::ostream &os)
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{
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os << " mov " << PhysRegName(target_xreg) << ", "
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<< PhysRegName(base_reg) << "\n";
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while (offset > 0)
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{
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const int chunk = offset > 4095 ? 4095 : offset;
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os << " add " << PhysRegName(target_xreg) << ", "
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<< PhysRegName(target_xreg) << ", #" << chunk << "\n";
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offset -= chunk;
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}
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while (offset < 0)
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{
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const int chunk = (-offset) > 4095 ? 4095 : (-offset);
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os << " sub " << PhysRegName(target_xreg) << ", "
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<< PhysRegName(target_xreg) << ", #" << chunk << "\n";
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offset += chunk;
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}
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}
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void PrintStackAccess(Opcode opcode, const Operand ®, int offset,
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std::ostream &os)
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{
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const char *narrow_op = (opcode == Opcode::LoadStack) ? "ldur" : "stur";
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const char *wide_op = (opcode == Opcode::LoadStack) ? "ldr" : "str";
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if (offset >= -256 && offset <= 255)
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{
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os << " " << narrow_op << " ";
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PrintOperand(reg, os);
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os << ", [x29, #" << offset << "]\n";
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return;
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}
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const PhysReg scratch_xreg = PrinterScratchXReg();
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EmitAddressFromBase(scratch_xreg, PhysReg::X29, offset, os);
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os << " " << wide_op << " ";
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PrintOperand(reg, os);
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os << ", [" << PhysRegName(scratch_xreg) << "]\n";
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}
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void PrintGlobalAddr(const Operand &dst, const std::string &symbol,
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std::ostream &os)
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{
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const std::string asm_symbol = NormalizeAsmSymbol(symbol);
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os << " adrp ";
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PrintOperand(dst, os);
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os << ", " << asm_symbol << "\n";
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os << " add ";
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PrintOperand(dst, os);
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os << ", ";
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PrintOperand(dst, os);
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os << ", :lo12:" << asm_symbol << "\n";
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}
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void PrintGlobalAccess(Opcode opcode, const Operand ®,
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const std::string &symbol, std::ostream &os)
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{
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const std::string asm_symbol = NormalizeAsmSymbol(symbol);
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const PhysReg scratch_xreg = PrinterScratchXReg();
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os << " adrp " << PhysRegName(scratch_xreg) << ", " << asm_symbol << "\n";
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os << " " << (opcode == Opcode::LoadGlobal ? "ldr " : "str ");
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PrintOperand(reg, os);
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os << ", [" << PhysRegName(scratch_xreg) << ", #:lo12:" << asm_symbol << "]\n";
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}
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void PrintMemAccess(Opcode opcode, const Operand &data_reg,
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const Operand &addr_reg, std::ostream &os)
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{
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os << " " << (opcode == Opcode::LoadMem ? "ldr " : "str ");
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PrintOperand(data_reg, os);
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os << ", [";
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PrintOperand(addr_reg, os);
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os << "]\n";
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}
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int ResolveFrameOffset(const MachineFunction &function, const Operand &operand)
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{
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if (operand.GetKind() != Operand::Kind::FrameIndex)
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{
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throw std::runtime_error(FormatError("mir", "期望 FrameIndex 操作数"));
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}
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return function.GetFrameSlot(operand.GetFrameIndex()).offset;
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}
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bool IsStackArgSlot(const MachineFunction &function, const Operand &operand)
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{
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if (operand.GetKind() != Operand::Kind::FrameIndex)
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{
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return false;
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}
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const auto &slot = function.GetFrameSlot(operand.GetFrameIndex());
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return slot.is_stack_arg && !slot.is_callee_stack_arg;
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}
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void PrintStackArgAccess(Opcode opcode, const Operand ®, int offset,
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std::ostream &os)
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{
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const char *wide_op = (opcode == Opcode::LoadStack) ? "ldr" : "str";
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bool is_32bit = IsWReg(reg.GetReg()) || IsSReg(reg.GetReg());
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int max_imm = is_32bit ? 16380 : 32760;
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if (offset >= 0 && offset <= max_imm)
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{
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os << " " << wide_op << " ";
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PrintOperand(reg, os);
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os << ", [sp, #" << offset << "]\n";
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return;
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}
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const PhysReg scratch_xreg = PrinterScratchXReg();
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EmitAddressFromBase(scratch_xreg, PhysReg::SP, offset, os);
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os << " " << wide_op << " ";
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PrintOperand(reg, os);
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os << ", [" << PhysRegName(scratch_xreg) << "]\n";
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}
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void PrintInstr(const MachineFunction &function, const MachineInstr &instr,
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std::ostream &os)
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{
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const char *asm_op = OpcodeToAsm(instr.GetOpcode());
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const auto &operands = instr.GetOperands();
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switch (instr.GetOpcode())
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{
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case Opcode::Prologue:
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{
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const auto &cs_regs = function.GetCalleeSavedRegs();
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os << " stp x29, x30, [sp, #-16]!\n";
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os << " mov x29, sp\n";
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if (function.GetFrameSize() > 0)
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{
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EmitStackAdjust("sub", function.GetFrameSize(), os);
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}
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int cs_offset = 0;
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for (auto r : cs_regs)
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{
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if (r >= PhysReg::X0 && r <= PhysReg::X30)
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{
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os << " str " << PhysRegName(r) << ", [sp, #" << cs_offset << "]\n";
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cs_offset += 8;
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}
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else if (r >= PhysReg::S0 && r <= PhysReg::S31)
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{
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os << " str " << PhysRegName(r) << ", [sp, #" << cs_offset << "]\n";
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cs_offset += 4;
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}
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}
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return;
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}
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case Opcode::Epilogue:
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{
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const auto &cs_regs = function.GetCalleeSavedRegs();
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int cs_offset = 0;
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for (auto r : cs_regs)
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{
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if (r >= PhysReg::X0 && r <= PhysReg::X30)
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{
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os << " ldr " << PhysRegName(r) << ", [sp, #" << cs_offset << "]\n";
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cs_offset += 8;
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}
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else if (r >= PhysReg::S0 && r <= PhysReg::S31)
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{
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os << " ldr " << PhysRegName(r) << ", [sp, #" << cs_offset << "]\n";
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cs_offset += 4;
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}
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}
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if (function.GetFrameSize() > 0)
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{
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EmitStackAdjust("add", function.GetFrameSize(), os);
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}
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os << " ldp x29, x30, [sp], #16\n";
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os << " ret\n";
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return;
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}
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case Opcode::Ret:
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os << " ret\n";
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|
|
return;
|
|
|
|
|
|
case Opcode::MovImm:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
EmitLargeImmediate(operands[0].GetReg(), operands[1].GetImm(), os);
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::LoadStack:
|
|
|
case Opcode::StoreStack:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Reg &&
|
|
|
operands[1].GetKind() == Operand::Kind::FrameIndex)
|
|
|
{
|
|
|
if (IsStackArgSlot(function, operands[1]))
|
|
|
{
|
|
|
PrintStackArgAccess(instr.GetOpcode(), operands[0],
|
|
|
ResolveFrameOffset(function, operands[1]), os);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
PrintStackAccess(instr.GetOpcode(), operands[0],
|
|
|
ResolveFrameOffset(function, operands[1]), os);
|
|
|
}
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::LoadStackAddr:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Reg &&
|
|
|
operands[1].GetKind() == Operand::Kind::FrameIndex)
|
|
|
{
|
|
|
EmitAddressFromBase(operands[0].GetReg(), PhysReg::X29,
|
|
|
ResolveFrameOffset(function, operands[1]), os);
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::LoadGlobal:
|
|
|
case Opcode::StoreGlobal:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Reg &&
|
|
|
operands[1].GetKind() == Operand::Kind::Symbol)
|
|
|
{
|
|
|
PrintGlobalAccess(instr.GetOpcode(), operands[0],
|
|
|
operands[1].GetSymbol(), os);
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::LoadGlobalAddr:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Reg &&
|
|
|
operands[1].GetKind() == Operand::Kind::Symbol)
|
|
|
{
|
|
|
PrintGlobalAddr(operands[0], operands[1].GetSymbol(), os);
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::LoadMem:
|
|
|
case Opcode::StoreMem:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Reg &&
|
|
|
operands[1].GetKind() == Operand::Kind::Reg &&
|
|
|
IsXReg(operands[1].GetReg()))
|
|
|
{
|
|
|
PrintMemAccess(instr.GetOpcode(), operands[0], operands[1], os);
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Uxtw:
|
|
|
case Opcode::Sxtw:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " " << (instr.GetOpcode() == Opcode::Uxtw ? "uxtw" : "sxtw") << " ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::CSet:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " cset ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", "
|
|
|
<< CondCodeToAsm(static_cast<CondCode>(operands[1].GetImm()))
|
|
|
<< "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Br:
|
|
|
if (!operands.empty() && operands[0].GetKind() == Operand::Kind::Label)
|
|
|
{
|
|
|
os << " b ";
|
|
|
PrintBlockLabelRef(function, operands[0].GetLabel(), os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::CondBr:
|
|
|
if (operands.size() >= 2 &&
|
|
|
operands[0].GetKind() == Operand::Kind::Imm &&
|
|
|
operands[1].GetKind() == Operand::Kind::Label)
|
|
|
{
|
|
|
os << " b."
|
|
|
<< CondCodeToAsm(static_cast<CondCode>(operands[0].GetImm()))
|
|
|
<< " ";
|
|
|
PrintBlockLabelRef(function, operands[1].GetLabel(), os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::ModRR:
|
|
|
if (operands.size() >= 3)
|
|
|
{
|
|
|
const PhysReg qreg = PickModQuotientReg(operands[0], operands[1], operands[2]);
|
|
|
|
|
|
os << " sdiv " << PhysRegName(qreg) << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << "\n";
|
|
|
|
|
|
os << " msub ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", " << PhysRegName(qreg) << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::ShlRR:
|
|
|
case Opcode::ShrRR:
|
|
|
case Opcode::AsrRR:
|
|
|
if (operands.size() >= 3)
|
|
|
{
|
|
|
const char *shift_op = "lsl";
|
|
|
if (instr.GetOpcode() == Opcode::ShrRR)
|
|
|
shift_op = "lsr";
|
|
|
else if (instr.GetOpcode() == Opcode::AsrRR)
|
|
|
shift_op = "asr";
|
|
|
os << " " << shift_op << " ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
if (operands[2].GetKind() == Operand::Kind::Imm)
|
|
|
{
|
|
|
os << "#" << operands[2].GetImm();
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
PrintOperand(operands[2], os);
|
|
|
}
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Asr64RR:
|
|
|
if (operands.size() >= 3)
|
|
|
{
|
|
|
os << " asr ";
|
|
|
if (operands[0].GetKind() == Operand::Kind::Reg && IsWReg(operands[0].GetReg()))
|
|
|
os << PhysRegName(static_cast<PhysReg>(static_cast<int>(operands[0].GetReg()) + 31));
|
|
|
else
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
if (operands[1].GetKind() == Operand::Kind::Reg && IsWReg(operands[1].GetReg()))
|
|
|
os << PhysRegName(static_cast<PhysReg>(static_cast<int>(operands[1].GetReg()) + 31));
|
|
|
else
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
if (operands[2].GetKind() == Operand::Kind::Imm)
|
|
|
os << "#" << operands[2].GetImm();
|
|
|
else
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::CmpImm:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " cmp ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", #" << operands[1].GetImm() << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Csel:
|
|
|
if (operands.size() >= 4)
|
|
|
{
|
|
|
os << " csel ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << ", " << CondCodeToAsm(static_cast<CondCode>(operands[3].GetImm())) << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Csneg:
|
|
|
if (operands.size() >= 4)
|
|
|
{
|
|
|
os << " csneg ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << ", " << CondCodeToAsm(static_cast<CondCode>(operands[3].GetImm())) << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Smull:
|
|
|
if (operands.size() >= 3)
|
|
|
{
|
|
|
os << " smull ";
|
|
|
if (operands[0].GetKind() == Operand::Kind::Reg && IsWReg(operands[0].GetReg()))
|
|
|
os << PhysRegName(static_cast<PhysReg>(static_cast<int>(operands[0].GetReg()) + 31));
|
|
|
else
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Msub:
|
|
|
if (operands.size() >= 4)
|
|
|
{
|
|
|
os << " msub ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[2], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[3], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::NegRR:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " neg ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::MovReg:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
bool is_float = IsSReg(operands[0].GetReg()) || IsSReg(operands[1].GetReg());
|
|
|
os << " " << (is_float ? "fmov" : "mov") << " ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::FMovWS:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " fmov ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::Scvtf:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " scvtf ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
case Opcode::FCvtzs:
|
|
|
if (operands.size() >= 2)
|
|
|
{
|
|
|
os << " fcvtzs ";
|
|
|
PrintOperand(operands[0], os);
|
|
|
os << ", ";
|
|
|
PrintOperand(operands[1], os);
|
|
|
os << "\n";
|
|
|
}
|
|
|
return;
|
|
|
|
|
|
default:
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
if (asm_op && asm_op[0] != '\0' && !operands.empty())
|
|
|
{
|
|
|
os << " " << asm_op;
|
|
|
for (size_t i = 0; i < operands.size(); ++i)
|
|
|
{
|
|
|
os << (i == 0 ? " " : ", ");
|
|
|
PrintOperand(operands[i], os);
|
|
|
}
|
|
|
os << "\n";
|
|
|
}
|
|
|
}
|
|
|
|
|
|
void PrintGlobals(const MachineModule &module, std::ostream &os)
|
|
|
{
|
|
|
if (module.GetGlobals().empty())
|
|
|
{
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
os << " .data\n";
|
|
|
for (const auto &global : module.GetGlobals())
|
|
|
{
|
|
|
const std::string asm_name = NormalizeAsmSymbol(global.name);
|
|
|
|
|
|
bool is_zero_init = false;
|
|
|
if (global.kind == MachineGlobal::Kind::I32Scalar && global.init_value == 0)
|
|
|
{
|
|
|
is_zero_init = true;
|
|
|
}
|
|
|
if (global.kind == MachineGlobal::Kind::I32Array)
|
|
|
{
|
|
|
bool all_zero = true;
|
|
|
for (auto v : global.init_values)
|
|
|
{
|
|
|
if (v != 0)
|
|
|
{
|
|
|
all_zero = false;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
if (all_zero)
|
|
|
{
|
|
|
is_zero_init = true;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (is_zero_init)
|
|
|
{
|
|
|
os << " .bss\n";
|
|
|
os << " .globl " << asm_name << "\n";
|
|
|
os << " .p2align 2\n";
|
|
|
os << asm_name << ":\n";
|
|
|
if (global.kind == MachineGlobal::Kind::I32Scalar)
|
|
|
{
|
|
|
os << " .space 4\n";
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
os << " .space " << (global.array_size * 4) << "\n";
|
|
|
}
|
|
|
os << " .data\n";
|
|
|
continue;
|
|
|
}
|
|
|
|
|
|
os << " .globl " << asm_name << "\n";
|
|
|
os << " .p2align 2\n";
|
|
|
os << asm_name << ":\n";
|
|
|
|
|
|
if (global.kind == MachineGlobal::Kind::I32Scalar)
|
|
|
{
|
|
|
os << " .word " << global.init_value << "\n";
|
|
|
continue;
|
|
|
}
|
|
|
|
|
|
const size_t init_count = global.init_values.size();
|
|
|
for (size_t i = 0; i < init_count; ++i)
|
|
|
{
|
|
|
os << " .word " << global.init_values[i] << "\n";
|
|
|
}
|
|
|
|
|
|
if (global.array_size > init_count)
|
|
|
{
|
|
|
os << " .zero " << ((global.array_size - init_count) * 4) << "\n";
|
|
|
}
|
|
|
}
|
|
|
os << "\n";
|
|
|
}
|
|
|
|
|
|
} // namespace
|
|
|
|
|
|
void PrintAsm(const MachineFunction &function, std::ostream &os)
|
|
|
{
|
|
|
const std::string asm_name = NormalizeAsmSymbol(function.GetName());
|
|
|
|
|
|
os << " .text\n";
|
|
|
os << " .globl " << asm_name << "\n";
|
|
|
os << " .p2align 2\n";
|
|
|
os << asm_name << ":\n";
|
|
|
|
|
|
for (const auto &block_ptr : function.GetBlocks())
|
|
|
{
|
|
|
if (!block_ptr)
|
|
|
{
|
|
|
continue;
|
|
|
}
|
|
|
|
|
|
const auto &block = *block_ptr;
|
|
|
PrintBlockLabelRef(function, block.GetLabelId(), os);
|
|
|
os << ":\n";
|
|
|
|
|
|
for (const auto &instr : block.GetInstructions())
|
|
|
{
|
|
|
PrintInstr(function, instr, os);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
void PrintAsm(const MachineModule &module, std::ostream &os)
|
|
|
{
|
|
|
PrintGlobals(module, os);
|
|
|
|
|
|
bool first = true;
|
|
|
for (const auto &function_ptr : module.GetFunctions())
|
|
|
{
|
|
|
if (!function_ptr)
|
|
|
{
|
|
|
continue;
|
|
|
}
|
|
|
|
|
|
if (!first)
|
|
|
{
|
|
|
os << "\n";
|
|
|
}
|
|
|
PrintAsm(*function_ptr, os);
|
|
|
first = false;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
} // namespace mir
|
