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#include "mir/MIR.h"
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#include <algorithm>
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#include <queue>
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#include <set>
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#include <unordered_map>
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#include <unordered_set>
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#include <vector>
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#include "utils/Log.h"
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namespace mir
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{
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namespace
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{
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static int PhysRegToNumber(PhysReg reg)
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{
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if (reg >= PhysReg::W0 && reg <= PhysReg::W30)
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return static_cast<int>(reg) - static_cast<int>(PhysReg::W0);
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if (reg >= PhysReg::X0 && reg <= PhysReg::X30)
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return static_cast<int>(reg) - static_cast<int>(PhysReg::X0);
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if (reg >= PhysReg::S0 && reg <= PhysReg::S31)
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return static_cast<int>(reg) - static_cast<int>(PhysReg::S0) + 100;
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return -1;
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}
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static PhysReg NumberToPhysReg(int num, VRegClass vc)
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{
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if (vc == VRegClass::Float)
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return static_cast<PhysReg>(static_cast<int>(PhysReg::S0) + num);
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if (vc == VRegClass::Ptr)
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return static_cast<PhysReg>(static_cast<int>(PhysReg::X0) + num);
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return static_cast<PhysReg>(static_cast<int>(PhysReg::W0) + num);
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}
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static bool IsGPReg(PhysReg reg)
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{
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return (reg >= PhysReg::W0 && reg <= PhysReg::W30) ||
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(reg >= PhysReg::X0 && reg <= PhysReg::X30);
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}
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static bool IsFPReg(PhysReg reg)
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{
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return reg >= PhysReg::S0 && reg <= PhysReg::S31;
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}
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static const int GP_ALLOCATABLE[] = {8, 9, 10, 11, 12, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28};
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static const int GP_NUM_ALLOCATABLE = 16;
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static const int FP_ALLOCATABLE[] = {8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
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static const int FP_NUM_ALLOCATABLE = 24;
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static const int FP_CALLER_SAVED[] = {8, 9, 10, 11, 12, 13, 14, 15};
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static const int FP_NUM_CALLER_SAVED = 8;
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static const int GP_CALLER_SAVED[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17};
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static const int GP_NUM_CALLER_SAVED = 18;
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struct InstDefUse
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{
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std::vector<int> defs;
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std::vector<int> uses;
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bool is_call = false;
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bool is_terminator = false;
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};
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static InstDefUse GetInstDefUse(const MachineInstr &inst, MachineFunction & /*function*/)
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{
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InstDefUse result;
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const auto opcode = inst.GetOpcode();
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const auto &ops = inst.GetOperands();
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switch (opcode)
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{
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::Br:
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break;
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case Opcode::MovImm:
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if (ops.size() >= 1 && ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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break;
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case Opcode::LoadStack:
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case Opcode::LoadGlobal:
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case Opcode::LoadGlobalAddr:
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case Opcode::LoadStackAddr:
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if (ops.size() >= 1 && ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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break;
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case Opcode::StoreStack:
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case Opcode::StoreGlobal:
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if (ops.size() >= 1 && ops[0].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[0].GetVRegId());
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break;
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case Opcode::LoadMem:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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// 缩放寻址第三操作数：index register
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if (ops.size() >= 3 && ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::StoreMem:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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// 缩放寻址第三操作数：index register
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if (ops.size() >= 3 && ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::AddRR:
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case Opcode::SubRR:
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case Opcode::MulRR:
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case Opcode::DivRR:
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case Opcode::ModRR:
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case Opcode::AndRR:
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case Opcode::OrRR:
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case Opcode::XorRR:
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case Opcode::FAddRR:
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case Opcode::FSubRR:
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case Opcode::FMulRR:
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case Opcode::FDivRR:
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if (ops.size() >= 3)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::ShlRR:
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case Opcode::ShrRR:
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case Opcode::AsrRR:
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case Opcode::Asr64RR:
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if (ops.size() >= 3)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::Uxtw:
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case Opcode::Sxtw:
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case Opcode::Scvtf:
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case Opcode::FCvtzs:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::FMovWS:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::CmpRR:
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case Opcode::CmpImm:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::FCmpRR:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::CSet:
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if (ops.size() >= 1 && ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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break;
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case Opcode::Csel:
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if (ops.size() >= 3)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::Csneg:
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if (ops.size() >= 3)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::Smull:
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if (ops.size() >= 3)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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}
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break;
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case Opcode::Msub:
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if (ops.size() >= 4)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[2].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[2].GetVRegId());
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if (ops[3].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[3].GetVRegId());
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}
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break;
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case Opcode::NegRR:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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}
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break;
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case Opcode::CondBr:
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result.is_terminator = true;
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break;
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case Opcode::Call:
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result.is_call = true;
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for (size_t i = 0; i < ops.size(); ++i)
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{
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if (ops[i].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[i].GetVRegId());
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}
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break;
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case Opcode::Ret:
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for (size_t i = 0; i < ops.size(); ++i)
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{
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if (ops[i].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[i].GetVRegId());
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}
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result.is_terminator = true;
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break;
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case Opcode::MovReg:
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if (ops.size() >= 2)
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{
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if (ops[0].GetKind() == Operand::Kind::VReg)
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result.defs.push_back(ops[0].GetVRegId());
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if (ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[0].GetKind() == Operand::Kind::Reg && ops[1].GetKind() == Operand::Kind::VReg)
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result.uses.push_back(ops[1].GetVRegId());
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if (ops[0].GetKind() == Operand::Kind::VReg && ops[1].GetKind() == Operand::Kind::Reg)
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result.defs.push_back(ops[0].GetVRegId());
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}
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break;
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default:
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for (const auto &op : ops)
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{
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if (op.GetKind() == Operand::Kind::VReg)
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result.uses.push_back(op.GetVRegId());
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}
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break;
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}
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auto remove_dups = [](std::vector<int> &v)
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{
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std::sort(v.begin(), v.end());
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v.erase(std::unique(v.begin(), v.end()), v.end());
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};
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remove_dups(result.defs);
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remove_dups(result.uses);
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return result;
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}
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struct BlockLiveness
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{
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std::unordered_set<int> live_in;
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std::unordered_set<int> live_out;
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std::unordered_set<int> def;
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std::unordered_set<int> use;
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};
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static std::vector<BlockLiveness> ComputeBlockLiveness(MachineFunction &function)
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{
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auto &blocks = function.GetBlocks();
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const size_t num_blocks = blocks.size();
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std::vector<BlockLiveness> bl(num_blocks);
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std::unordered_map<int, size_t> label_to_block;
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for (size_t i = 0; i < num_blocks; ++i)
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{
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label_to_block[blocks[i]->GetLabelId()] = i;
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}
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for (size_t i = 0; i < num_blocks; ++i)
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{
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for (const auto &inst : blocks[i]->GetInstructions())
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{
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auto du = GetInstDefUse(inst, function);
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for (int u : du.uses)
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{
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if (bl[i].def.find(u) == bl[i].def.end())
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bl[i].use.insert(u);
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}
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for (int d : du.defs)
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bl[i].def.insert(d);
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}
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}
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bool changed = true;
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while (changed)
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{
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changed = false;
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for (size_t i = 0; i < num_blocks; ++i)
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{
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std::unordered_set<int> new_out;
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for (const auto &inst : blocks[i]->GetInstructions())
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{
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if (inst.GetOpcode() == Opcode::Br && inst.GetOperands().size() >= 1 &&
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inst.GetOperands()[0].GetKind() == Operand::Kind::Label)
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{
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auto it = label_to_block.find(inst.GetOperands()[0].GetLabel());
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if (it != label_to_block.end())
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for (int v : bl[it->second].live_in)
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new_out.insert(v);
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}
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if (inst.GetOpcode() == Opcode::CondBr && inst.GetOperands().size() >= 2 &&
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inst.GetOperands()[1].GetKind() == Operand::Kind::Label)
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{
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auto it = label_to_block.find(inst.GetOperands()[1].GetLabel());
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if (it != label_to_block.end())
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for (int v : bl[it->second].live_in)
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new_out.insert(v);
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}
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}
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if (new_out != bl[i].live_out)
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{
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bl[i].live_out = new_out;
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changed = true;
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}
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std::unordered_set<int> new_in = bl[i].use;
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for (int v : bl[i].live_out)
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{
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if (bl[i].def.find(v) == bl[i].def.end())
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new_in.insert(v);
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}
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if (new_in != bl[i].live_in)
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{
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bl[i].live_in = new_in;
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changed = true;
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}
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}
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}
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return bl;
|
|
|
}
|
|
|
|
|
|
struct InterferenceGraph
|
|
|
{
|
|
|
std::unordered_set<int> nodes;
|
|
|
std::unordered_set<long long> edges;
|
|
|
std::unordered_map<int, int> degree;
|
|
|
|
|
|
static long long MakeEdgeKey(int u, int v)
|
|
|
{
|
|
|
if (u > v) std::swap(u, v);
|
|
|
return (static_cast<long long>(static_cast<unsigned long long>(static_cast<unsigned int>(u)) << 32)) | static_cast<unsigned int>(v);
|
|
|
}
|
|
|
|
|
|
void AddNode(int v) { nodes.insert(v); }
|
|
|
|
|
|
void AddEdge(int u, int v)
|
|
|
{
|
|
|
if (u == v)
|
|
|
return;
|
|
|
auto key = MakeEdgeKey(u, v);
|
|
|
if (edges.find(key) == edges.end())
|
|
|
{
|
|
|
edges.insert(key);
|
|
|
degree[u]++;
|
|
|
degree[v]++;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
int GetDegree(int v) const
|
|
|
{
|
|
|
auto it = degree.find(v);
|
|
|
return it != degree.end() ? it->second : 0;
|
|
|
}
|
|
|
};
|
|
|
|
|
|
static bool IsGPClass(VRegClass vc)
|
|
|
{
|
|
|
return vc == VRegClass::Int || vc == VRegClass::Ptr;
|
|
|
}
|
|
|
|
|
|
static void BuildInterferenceForGP(
|
|
|
MachineFunction &function,
|
|
|
const std::vector<BlockLiveness> &block_liveness,
|
|
|
const std::vector<int> &allocatable_regs,
|
|
|
InterferenceGraph &graph)
|
|
|
{
|
|
|
auto &blocks = function.GetBlocks();
|
|
|
|
|
|
for (int vreg = 0; vreg < function.GetNumVRegs(); ++vreg)
|
|
|
{
|
|
|
if (IsGPClass(function.GetVRegClass(vreg)))
|
|
|
graph.AddNode(vreg);
|
|
|
}
|
|
|
|
|
|
for (size_t bi = 0; bi < blocks.size(); ++bi)
|
|
|
{
|
|
|
auto &block = blocks[bi];
|
|
|
std::unordered_set<int> live = block_liveness[bi].live_out;
|
|
|
|
|
|
std::vector<int> gp_live;
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (IsGPClass(function.GetVRegClass(v)))
|
|
|
gp_live.push_back(v);
|
|
|
}
|
|
|
for (size_t i = 0; i < gp_live.size(); ++i)
|
|
|
{
|
|
|
for (size_t j = i + 1; j < gp_live.size(); ++j)
|
|
|
{
|
|
|
graph.AddEdge(gp_live[i], gp_live[j]);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
const auto &insts = block->GetInstructions();
|
|
|
for (auto it = insts.rbegin(); it != insts.rend(); ++it)
|
|
|
{
|
|
|
auto du = GetInstDefUse(*it, function);
|
|
|
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (!IsGPClass(function.GetVRegClass(d)))
|
|
|
continue;
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (v != d && IsGPClass(function.GetVRegClass(v)))
|
|
|
graph.AddEdge(d, v);
|
|
|
}
|
|
|
live.erase(d);
|
|
|
}
|
|
|
for (int u : du.uses)
|
|
|
{
|
|
|
if (IsGPClass(function.GetVRegClass(u)))
|
|
|
live.insert(u);
|
|
|
}
|
|
|
|
|
|
if (du.is_call)
|
|
|
{
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (IsGPClass(function.GetVRegClass(v)))
|
|
|
{
|
|
|
for (int c : allocatable_regs)
|
|
|
{
|
|
|
bool is_caller_saved = false;
|
|
|
for (int j = 0; j < GP_NUM_CALLER_SAVED; ++j)
|
|
|
{
|
|
|
if (GP_CALLER_SAVED[j] == c)
|
|
|
{
|
|
|
is_caller_saved = true;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
if (!is_caller_saved)
|
|
|
continue;
|
|
|
|
|
|
int call_clobber_node = -1000 - c;
|
|
|
graph.AddNode(call_clobber_node);
|
|
|
graph.AddEdge(v, call_clobber_node);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
static void BuildInterferenceForFP(
|
|
|
MachineFunction &function,
|
|
|
const std::vector<BlockLiveness> &block_liveness,
|
|
|
const std::vector<int> &allocatable_regs,
|
|
|
InterferenceGraph &graph)
|
|
|
{
|
|
|
auto &blocks = function.GetBlocks();
|
|
|
|
|
|
for (int vreg = 0; vreg < function.GetNumVRegs(); ++vreg)
|
|
|
{
|
|
|
if (function.GetVRegClass(vreg) == VRegClass::Float)
|
|
|
graph.AddNode(vreg);
|
|
|
}
|
|
|
|
|
|
for (size_t bi = 0; bi < blocks.size(); ++bi)
|
|
|
{
|
|
|
auto &block = blocks[bi];
|
|
|
std::unordered_set<int> live = block_liveness[bi].live_out;
|
|
|
|
|
|
std::vector<int> fp_live;
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (function.GetVRegClass(v) == VRegClass::Float)
|
|
|
fp_live.push_back(v);
|
|
|
}
|
|
|
for (size_t i = 0; i < fp_live.size(); ++i)
|
|
|
{
|
|
|
for (size_t j = i + 1; j < fp_live.size(); ++j)
|
|
|
{
|
|
|
graph.AddEdge(fp_live[i], fp_live[j]);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
const auto &insts = block->GetInstructions();
|
|
|
for (auto it = insts.rbegin(); it != insts.rend(); ++it)
|
|
|
{
|
|
|
auto du = GetInstDefUse(*it, function);
|
|
|
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (function.GetVRegClass(d) != VRegClass::Float)
|
|
|
continue;
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (v != d && function.GetVRegClass(v) == VRegClass::Float)
|
|
|
graph.AddEdge(d, v);
|
|
|
}
|
|
|
live.erase(d);
|
|
|
}
|
|
|
for (int u : du.uses)
|
|
|
{
|
|
|
if (function.GetVRegClass(u) == VRegClass::Float)
|
|
|
live.insert(u);
|
|
|
}
|
|
|
|
|
|
if (du.is_call)
|
|
|
{
|
|
|
for (int v : live)
|
|
|
{
|
|
|
if (function.GetVRegClass(v) == VRegClass::Float)
|
|
|
{
|
|
|
for (int j = 0; j < FP_NUM_CALLER_SAVED; ++j)
|
|
|
{
|
|
|
int c = FP_CALLER_SAVED[j];
|
|
|
int call_clobber_node = -2000 - c;
|
|
|
graph.AddNode(call_clobber_node);
|
|
|
graph.AddEdge(v, call_clobber_node);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
struct GraphColoringResult
|
|
|
{
|
|
|
std::unordered_map<int, int> assignment;
|
|
|
std::set<int> spilled;
|
|
|
};
|
|
|
|
|
|
static GraphColoringResult ColorGraph(
|
|
|
InterferenceGraph &graph,
|
|
|
const std::vector<int> &allocatable_regs,
|
|
|
MachineFunction & /*function*/,
|
|
|
const std::unordered_map<int, std::vector<int>> ©_edges = {})
|
|
|
{
|
|
|
const int K = static_cast<int>(allocatable_regs.size());
|
|
|
GraphColoringResult result;
|
|
|
|
|
|
std::unordered_map<int, std::unordered_set<int>> adj;
|
|
|
for (auto key : graph.edges)
|
|
|
{
|
|
|
int u = static_cast<int>(key >> 32);
|
|
|
int v = static_cast<int>(key & 0xFFFFFFFF);
|
|
|
adj[u].insert(v);
|
|
|
adj[v].insert(u);
|
|
|
}
|
|
|
|
|
|
std::unordered_map<int, int> precolored;
|
|
|
for (int v : graph.nodes)
|
|
|
{
|
|
|
if (v < 0)
|
|
|
{
|
|
|
if (v >= -1999 && v < -1000)
|
|
|
{
|
|
|
int reg_num = -(v + 1000);
|
|
|
precolored[v] = reg_num;
|
|
|
}
|
|
|
else if (v >= -2999 && v < -2000)
|
|
|
{
|
|
|
int reg_num = -(v + 2000);
|
|
|
precolored[v] = reg_num;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
std::unordered_set<int> remaining;
|
|
|
std::unordered_map<int, int> degree;
|
|
|
for (int v : graph.nodes)
|
|
|
{
|
|
|
if (v >= 0)
|
|
|
{
|
|
|
remaining.insert(v);
|
|
|
int deg = 0;
|
|
|
for (int n : adj[v])
|
|
|
{
|
|
|
if (graph.nodes.count(n))
|
|
|
deg++;
|
|
|
}
|
|
|
degree[v] = deg;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
std::vector<int> simplify_worklist;
|
|
|
for (int v : remaining)
|
|
|
{
|
|
|
if (degree[v] < K)
|
|
|
simplify_worklist.push_back(v);
|
|
|
}
|
|
|
|
|
|
std::vector<int> stack;
|
|
|
|
|
|
while (!remaining.empty())
|
|
|
{
|
|
|
while (!simplify_worklist.empty())
|
|
|
{
|
|
|
int v = simplify_worklist.back();
|
|
|
simplify_worklist.pop_back();
|
|
|
if (!remaining.count(v))
|
|
|
continue;
|
|
|
stack.push_back(v);
|
|
|
remaining.erase(v);
|
|
|
for (int n : adj[v])
|
|
|
{
|
|
|
if (remaining.count(n))
|
|
|
{
|
|
|
degree[n]--;
|
|
|
if (degree[n] == K - 1)
|
|
|
simplify_worklist.push_back(n);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (!remaining.empty())
|
|
|
{
|
|
|
int spill_candidate = -1;
|
|
|
int max_degree = -1;
|
|
|
for (int v : remaining)
|
|
|
{
|
|
|
if (degree[v] > max_degree)
|
|
|
{
|
|
|
max_degree = degree[v];
|
|
|
spill_candidate = v;
|
|
|
}
|
|
|
}
|
|
|
if (spill_candidate >= 0)
|
|
|
{
|
|
|
result.spilled.insert(spill_candidate);
|
|
|
remaining.erase(spill_candidate);
|
|
|
for (int n : adj[spill_candidate])
|
|
|
{
|
|
|
if (remaining.count(n))
|
|
|
{
|
|
|
degree[n]--;
|
|
|
if (degree[n] == K - 1)
|
|
|
simplify_worklist.push_back(n);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
std::unordered_map<int, int> colored = precolored;
|
|
|
while (!stack.empty())
|
|
|
{
|
|
|
int v = stack.back();
|
|
|
stack.pop_back();
|
|
|
|
|
|
std::unordered_set<int> used_colors;
|
|
|
for (int n : adj[v])
|
|
|
{
|
|
|
auto it = colored.find(n);
|
|
|
if (it != colored.end())
|
|
|
used_colors.insert(it->second);
|
|
|
}
|
|
|
|
|
|
int assigned_color = -1;
|
|
|
|
|
|
// 偏置着色：优先使用 copy edge 源操作数的颜色
|
|
|
auto copy_it = copy_edges.find(v);
|
|
|
if (copy_it != copy_edges.end())
|
|
|
{
|
|
|
for (int neighbor : copy_it->second)
|
|
|
{
|
|
|
auto nit = colored.find(neighbor);
|
|
|
if (nit != colored.end())
|
|
|
{
|
|
|
int pref = nit->second;
|
|
|
if (used_colors.find(pref) == used_colors.end())
|
|
|
{
|
|
|
assigned_color = pref;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (assigned_color < 0)
|
|
|
{
|
|
|
for (int c : allocatable_regs)
|
|
|
{
|
|
|
if (used_colors.find(c) == used_colors.end())
|
|
|
{
|
|
|
assigned_color = c;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (assigned_color >= 0)
|
|
|
{
|
|
|
colored[v] = assigned_color;
|
|
|
result.assignment[v] = assigned_color;
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
result.spilled.insert(v);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return result;
|
|
|
}
|
|
|
|
|
|
static int PickGPScratchReg(
|
|
|
const std::set<int> &used_scratch,
|
|
|
const InstDefUse &du,
|
|
|
const std::unordered_map<int, int> &gp_assignment,
|
|
|
int skip_vreg = -1)
|
|
|
{
|
|
|
if (!used_scratch.count(14))
|
|
|
{
|
|
|
bool x14_used = false;
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (d == skip_vreg) continue;
|
|
|
auto it = gp_assignment.find(d);
|
|
|
if (it != gp_assignment.end() && it->second == 14)
|
|
|
{ x14_used = true; break; }
|
|
|
}
|
|
|
if (!x14_used)
|
|
|
{
|
|
|
for (int u2 : du.uses)
|
|
|
{
|
|
|
auto it = gp_assignment.find(u2);
|
|
|
if (it != gp_assignment.end() && it->second == 14)
|
|
|
{ x14_used = true; break; }
|
|
|
}
|
|
|
}
|
|
|
if (!x14_used)
|
|
|
return 14;
|
|
|
}
|
|
|
|
|
|
for (int r : GP_ALLOCATABLE)
|
|
|
{
|
|
|
if (used_scratch.count(r)) continue;
|
|
|
bool used = false;
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (d == skip_vreg) continue;
|
|
|
auto it = gp_assignment.find(d);
|
|
|
if (it != gp_assignment.end() && it->second == r)
|
|
|
{ used = true; break; }
|
|
|
}
|
|
|
if (!used)
|
|
|
{
|
|
|
for (int u2 : du.uses)
|
|
|
{
|
|
|
auto it = gp_assignment.find(u2);
|
|
|
if (it != gp_assignment.end() && it->second == r)
|
|
|
{ used = true; break; }
|
|
|
}
|
|
|
}
|
|
|
if (!used) return r;
|
|
|
}
|
|
|
return GP_ALLOCATABLE[0];
|
|
|
}
|
|
|
|
|
|
static int PickFPScratchReg(
|
|
|
const std::set<int> &used_scratch,
|
|
|
const InstDefUse &du,
|
|
|
const std::unordered_map<int, int> &fp_assignment,
|
|
|
int skip_vreg = -1)
|
|
|
{
|
|
|
for (int r : FP_ALLOCATABLE)
|
|
|
{
|
|
|
if (used_scratch.count(r)) continue;
|
|
|
bool used = false;
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (d == skip_vreg) continue;
|
|
|
auto it = fp_assignment.find(d);
|
|
|
if (it != fp_assignment.end() && it->second == r)
|
|
|
{ used = true; break; }
|
|
|
}
|
|
|
if (!used)
|
|
|
{
|
|
|
for (int u2 : du.uses)
|
|
|
{
|
|
|
auto it = fp_assignment.find(u2);
|
|
|
if (it != fp_assignment.end() && it->second == r)
|
|
|
{ used = true; break; }
|
|
|
}
|
|
|
}
|
|
|
if (!used) return r;
|
|
|
}
|
|
|
return FP_ALLOCATABLE[0];
|
|
|
}
|
|
|
|
|
|
static void RewriteWithAllocation(
|
|
|
MachineFunction &function,
|
|
|
const std::unordered_map<int, int> &gp_assignment,
|
|
|
const std::unordered_map<int, int> &fp_assignment,
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const std::set<int> &spilled)
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{
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std::unordered_map<int, int> spill_slots;
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for (int v : spilled)
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{
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int size = (function.GetVRegClass(v) == VRegClass::Ptr) ? 8 : 4;
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spill_slots[v] = function.CreateFrameIndex(size);
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}
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for (auto &block : function.GetBlocks())
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{
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std::vector<MachineInstr> new_insts;
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for (auto &inst : block->GetInstructions())
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{
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auto du = GetInstDefUse(inst, function);
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std::set<int> used_scratch_gp;
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std::set<int> used_scratch_fp;
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for (int u : du.uses)
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{
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if (spilled.count(u))
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{
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VRegClass vc = function.GetVRegClass(u);
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int slot = spill_slots[u];
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int reload_reg_num = -1;
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if (vc == VRegClass::Float)
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{
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reload_reg_num = PickFPScratchReg(used_scratch_fp, du, fp_assignment);
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used_scratch_fp.insert(reload_reg_num);
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}
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else
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{
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reload_reg_num = PickGPScratchReg(used_scratch_gp, du, gp_assignment);
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used_scratch_gp.insert(reload_reg_num);
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}
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PhysReg reload_reg = NumberToPhysReg(reload_reg_num, vc);
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new_insts.push_back(
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MachineInstr(Opcode::LoadStack,
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{Operand::Reg(reload_reg), Operand::FrameIndex(slot)}));
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for (auto &op : inst.GetOperands())
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{
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if (op.GetKind() == Operand::Kind::VReg && op.GetVRegId() == u)
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{
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const_cast<Operand &>(op) = Operand::Reg(reload_reg);
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}
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}
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}
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}
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for (auto &op : inst.GetOperands())
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{
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if (op.GetKind() == Operand::Kind::VReg)
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|
{
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int vreg_id = op.GetVRegId();
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VRegClass op_vc = op.GetVRegClass();
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VRegClass actual_vc = function.GetVRegClass(vreg_id);
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int reg_num = -1;
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if (actual_vc == VRegClass::Float)
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{
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auto it = fp_assignment.find(vreg_id);
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if (it != fp_assignment.end())
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reg_num = it->second;
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}
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else
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{
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auto it = gp_assignment.find(vreg_id);
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if (it != gp_assignment.end())
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reg_num = it->second;
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}
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if (reg_num >= 0)
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{
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const_cast<Operand &>(op) = Operand::Reg(NumberToPhysReg(reg_num, actual_vc));
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}
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else if (spilled.count(vreg_id))
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{
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int spill_reg_num = -1;
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if (actual_vc == VRegClass::Float)
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{
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spill_reg_num = PickFPScratchReg(used_scratch_fp, du, fp_assignment, vreg_id);
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used_scratch_fp.insert(spill_reg_num);
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}
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else
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{
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spill_reg_num = PickGPScratchReg(used_scratch_gp, du, gp_assignment, vreg_id);
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used_scratch_gp.insert(spill_reg_num);
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}
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const_cast<Operand &>(op) = Operand::Reg(NumberToPhysReg(spill_reg_num, actual_vc));
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}
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}
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}
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new_insts.push_back(std::move(const_cast<MachineInstr &>(inst)));
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for (int d : du.defs)
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{
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if (spilled.count(d))
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{
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VRegClass vc = function.GetVRegClass(d);
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int slot = spill_slots[d];
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const auto &last_inst = new_insts.back();
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PhysReg spill_reg = PhysReg::W0;
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for (const auto &op : last_inst.GetOperands())
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|
{
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if (op.GetKind() == Operand::Kind::Reg)
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|
{
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PhysReg r = op.GetReg();
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if (vc == VRegClass::Float && IsFPReg(r))
|
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{ spill_reg = r; break; }
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else if (vc != VRegClass::Float && IsGPReg(r))
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{ spill_reg = r; break; }
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}
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}
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new_insts.push_back(
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MachineInstr(Opcode::StoreStack,
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{Operand::Reg(spill_reg), Operand::FrameIndex(slot)}));
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|
}
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}
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}
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|
block->GetInstructions() = std::move(new_insts);
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|
}
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|
}
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|
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static void AllocateRegistersForFunction(MachineFunction &function)
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|
|
{
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|
if (function.GetNumVRegs() == 0)
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|
return;
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|
const int MAX_SPILL_ROUNDS = 10;
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|
for (int round = 0; round < MAX_SPILL_ROUNDS; ++round)
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|
|
{
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|
auto block_liveness = ComputeBlockLiveness(function);
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// 收集 copy edges (MovReg 连接的 vreg 对)
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|
std::unordered_map<int, std::vector<int>> gp_copy_edges;
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|
std::unordered_map<int, std::vector<int>> fp_copy_edges;
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|
for (auto &block : function.GetBlocks())
|
|
|
{
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|
for (auto &inst : block->GetInstructions())
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|
|
{
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|
|
if (inst.GetOpcode() == Opcode::MovReg)
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|
|
{
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|
const auto &ops = inst.GetOperands();
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|
if (ops.size() >= 2 &&
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ops[0].GetKind() == Operand::Kind::VReg &&
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|
ops[1].GetKind() == Operand::Kind::VReg)
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|
|
{
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|
int dst = ops[0].GetVRegId();
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|
int src = ops[1].GetVRegId();
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if (function.GetVRegClass(dst) == function.GetVRegClass(src))
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|
{
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|
auto &edges = IsGPClass(function.GetVRegClass(dst))
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|
? gp_copy_edges : fp_copy_edges;
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|
edges[dst].push_back(src);
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|
edges[src].push_back(dst);
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|
}
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|
}
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|
}
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|
|
}
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|
|
}
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|
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|
|
|
std::vector<int> gp_alloc(GP_ALLOCATABLE, GP_ALLOCATABLE + GP_NUM_ALLOCATABLE);
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|
|
std::vector<int> fp_alloc(FP_ALLOCATABLE, FP_ALLOCATABLE + FP_NUM_ALLOCATABLE);
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|
|
|
|
|
InterferenceGraph gp_graph, fp_graph;
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|
|
BuildInterferenceForGP(function, block_liveness, gp_alloc, gp_graph);
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|
|
BuildInterferenceForFP(function, block_liveness, fp_alloc, fp_graph);
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|
|
|
|
|
auto gp_result = ColorGraph(gp_graph, gp_alloc, function, gp_copy_edges);
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|
|
auto fp_result = ColorGraph(fp_graph, fp_alloc, function, fp_copy_edges);
|
|
|
|
|
|
if (gp_result.spilled.empty() && fp_result.spilled.empty())
|
|
|
{
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|
|
std::unordered_map<int, int> gp_assign = gp_result.assignment;
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|
|
std::unordered_map<int, int> fp_assign = fp_result.assignment;
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|
|
|
|
|
for (const auto &pair : gp_assign)
|
|
|
{
|
|
|
if (pair.second >= 19 && pair.second <= 28)
|
|
|
{
|
|
|
function.AddCalleeSavedReg(NumberToPhysReg(pair.second, VRegClass::Ptr));
|
|
|
}
|
|
|
}
|
|
|
|
|
|
for (const auto &pair : fp_assign)
|
|
|
{
|
|
|
if (pair.second >= 16 && pair.second <= 31)
|
|
|
{
|
|
|
function.AddCalleeSavedReg(NumberToPhysReg(pair.second, VRegClass::Float));
|
|
|
}
|
|
|
}
|
|
|
|
|
|
RewriteWithAllocation(function, gp_assign, fp_assign, {});
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
std::set<int> all_spilled = gp_result.spilled;
|
|
|
for (int v : fp_result.spilled)
|
|
|
all_spilled.insert(v);
|
|
|
|
|
|
std::unordered_map<int, int> spill_slots;
|
|
|
for (int v : all_spilled)
|
|
|
{
|
|
|
int size = (function.GetVRegClass(v) == VRegClass::Ptr) ? 8 : 4;
|
|
|
spill_slots[v] = function.CreateFrameIndex(size);
|
|
|
}
|
|
|
|
|
|
for (auto &block : function.GetBlocks())
|
|
|
{
|
|
|
std::vector<MachineInstr> new_insts;
|
|
|
for (auto &inst : block->GetInstructions())
|
|
|
{
|
|
|
auto du = GetInstDefUse(inst, function);
|
|
|
|
|
|
for (int u : du.uses)
|
|
|
{
|
|
|
if (all_spilled.count(u))
|
|
|
{
|
|
|
VRegClass vc = function.GetVRegClass(u);
|
|
|
int new_vreg = function.CreateVReg(vc);
|
|
|
new_insts.push_back(
|
|
|
MachineInstr(Opcode::LoadStack,
|
|
|
{Operand::VReg(new_vreg, vc), Operand::FrameIndex(spill_slots[u])}));
|
|
|
for (auto &op : inst.GetOperands())
|
|
|
{
|
|
|
if (op.GetKind() == Operand::Kind::VReg && op.GetVRegId() == u)
|
|
|
{
|
|
|
const_cast<Operand &>(op) = Operand::VReg(new_vreg, vc);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
new_insts.push_back(std::move(const_cast<MachineInstr &>(inst)));
|
|
|
|
|
|
for (int d : du.defs)
|
|
|
{
|
|
|
if (all_spilled.count(d))
|
|
|
{
|
|
|
VRegClass vc = function.GetVRegClass(d);
|
|
|
int new_vreg = function.CreateVReg(vc);
|
|
|
auto &last = new_insts.back();
|
|
|
for (auto &op : last.GetOperands())
|
|
|
{
|
|
|
if (op.GetKind() == Operand::Kind::VReg && op.GetVRegId() == d)
|
|
|
{
|
|
|
const_cast<Operand &>(op) = Operand::VReg(new_vreg, vc);
|
|
|
}
|
|
|
}
|
|
|
new_insts.push_back(
|
|
|
MachineInstr(Opcode::StoreStack,
|
|
|
{Operand::VReg(new_vreg, vc), Operand::FrameIndex(spill_slots[d])}));
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
block->GetInstructions() = std::move(new_insts);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
auto block_liveness = ComputeBlockLiveness(function);
|
|
|
|
|
|
// 收集 copy edges
|
|
|
std::unordered_map<int, std::vector<int>> fp_copy_edges_fb;
|
|
|
std::unordered_map<int, std::vector<int>> gp_copy_edges_fb;
|
|
|
for (auto &block : function.GetBlocks())
|
|
|
for (auto &inst : block->GetInstructions())
|
|
|
if (inst.GetOpcode() == Opcode::MovReg)
|
|
|
{
|
|
|
const auto &ops = inst.GetOperands();
|
|
|
if (ops.size() >= 2 && ops[0].GetKind() == Operand::Kind::VReg &&
|
|
|
ops[1].GetKind() == Operand::Kind::VReg)
|
|
|
{
|
|
|
int dst = ops[0].GetVRegId(), src = ops[1].GetVRegId();
|
|
|
if (function.GetVRegClass(dst) == function.GetVRegClass(src))
|
|
|
{
|
|
|
auto &e = IsGPClass(function.GetVRegClass(dst)) ? gp_copy_edges_fb : fp_copy_edges_fb;
|
|
|
e[dst].push_back(src);
|
|
|
e[src].push_back(dst);
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
std::vector<int> gp_alloc(GP_ALLOCATABLE, GP_ALLOCATABLE + GP_NUM_ALLOCATABLE);
|
|
|
std::vector<int> fp_alloc(FP_ALLOCATABLE, FP_ALLOCATABLE + FP_NUM_ALLOCATABLE);
|
|
|
InterferenceGraph gp_graph, fp_graph;
|
|
|
BuildInterferenceForGP(function, block_liveness, gp_alloc, gp_graph);
|
|
|
BuildInterferenceForFP(function, block_liveness, fp_alloc, fp_graph);
|
|
|
auto gp_result = ColorGraph(gp_graph, gp_alloc, function, gp_copy_edges_fb);
|
|
|
auto fp_result = ColorGraph(fp_graph, fp_alloc, function, fp_copy_edges_fb);
|
|
|
std::set<int> all_spilled = gp_result.spilled;
|
|
|
for (int v : fp_result.spilled)
|
|
|
all_spilled.insert(v);
|
|
|
std::unordered_map<int, int> gp_assign = gp_result.assignment;
|
|
|
std::unordered_map<int, int> fp_assign = fp_result.assignment;
|
|
|
for (const auto &pair : gp_assign)
|
|
|
{
|
|
|
if (pair.second >= 19 && pair.second <= 28)
|
|
|
{
|
|
|
function.AddCalleeSavedReg(NumberToPhysReg(pair.second, VRegClass::Ptr));
|
|
|
}
|
|
|
}
|
|
|
for (const auto &pair : fp_assign)
|
|
|
{
|
|
|
if (pair.second >= 16 && pair.second <= 31)
|
|
|
{
|
|
|
function.AddCalleeSavedReg(NumberToPhysReg(pair.second, VRegClass::Float));
|
|
|
}
|
|
|
}
|
|
|
RewriteWithAllocation(function, gp_assign, fp_assign, all_spilled);
|
|
|
}
|
|
|
|
|
|
} // namespace
|
|
|
|
|
|
void RunRegAlloc(MachineFunction &function)
|
|
|
{
|
|
|
AllocateRegistersForFunction(function);
|
|
|
}
|
|
|
|
|
|
void RunRegAlloc(MachineModule &module)
|
|
|
{
|
|
|
for (auto &function : module.GetFunctions())
|
|
|
{
|
|
|
if (function)
|
|
|
RunRegAlloc(*function);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
} // namespace mir
|
