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139 Commits
2022spring
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@ -0,0 +1,66 @@
|
||||
name: Build Rust Doc And Run tests
|
||||
|
||||
on: [push]
|
||||
|
||||
env:
|
||||
CARGO_TERM_COLOR: always
|
||||
|
||||
jobs:
|
||||
build-doc:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: actions/checkout@v3
|
||||
- uses: actions-rs/toolchain@v1
|
||||
with:
|
||||
profile: minimal
|
||||
toolchain: nightly-2022-04-11
|
||||
components: rust-src, llvm-tools-preview
|
||||
target: riscv64gc-unknown-none-elf
|
||||
- name: Build doc
|
||||
run: cd os && cargo doc --no-deps --verbose
|
||||
- name: Deploy to Github Pages
|
||||
uses: peaceiris/actions-gh-pages@v3
|
||||
with:
|
||||
github_token: ${{ secrets.GITHUB_TOKEN }}
|
||||
publish_dir: ./os/target/riscv64gc-unknown-none-elf/doc
|
||||
destination_dir: ${{ github.ref_name }}
|
||||
|
||||
run-tests:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: actions/checkout@v3
|
||||
- uses: actions-rs/toolchain@v1
|
||||
with:
|
||||
profile: minimal
|
||||
toolchain: nightly-2022-04-11
|
||||
components: rust-src, llvm-tools-preview
|
||||
target: riscv64gc-unknown-none-elf
|
||||
- uses: actions-rs/install@v0.1
|
||||
with:
|
||||
crate: cargo-binutils
|
||||
version: latest
|
||||
use-tool-cache: true
|
||||
- name: Cache QEMU
|
||||
uses: actions/cache@v3
|
||||
with:
|
||||
path: qemu-7.0.0
|
||||
key: qemu-7.0.0-x86_64-riscv64
|
||||
- name: Install QEMU
|
||||
run: |
|
||||
sudo apt-get update
|
||||
sudo apt-get install ninja-build -y
|
||||
if [ ! -d qemu-7.0.0 ]; then
|
||||
wget https://download.qemu.org/qemu-7.0.0.tar.xz
|
||||
tar -xf qemu-7.0.0.tar.xz
|
||||
cd qemu-7.0.0
|
||||
./configure --target-list=riscv64-softmmu
|
||||
make -j
|
||||
else
|
||||
cd qemu-7.0.0
|
||||
fi
|
||||
sudo make install
|
||||
qemu-system-riscv64 --version
|
||||
|
||||
- name: Run usertests
|
||||
run: cd os && make run TEST=1
|
||||
timeout-minutes: 10
|
@ -1,16 +1,13 @@
|
||||
.idea/*
|
||||
os/target/*
|
||||
os/.idea/*
|
||||
.*/*
|
||||
!.github/*
|
||||
!.vscode/settings.json
|
||||
|
||||
**/target/
|
||||
**/Cargo.lock
|
||||
|
||||
os/src/link_app.S
|
||||
os/src/linker.ld
|
||||
os/last-*
|
||||
os/Cargo.lock
|
||||
user/target/*
|
||||
user/.idea/*
|
||||
user/Cargo.lock
|
||||
easy-fs/Cargo.lock
|
||||
easy-fs/target/*
|
||||
easy-fs-fuse/Cargo.lock
|
||||
easy-fs-fuse/target/*
|
||||
os/.gdb_history
|
||||
tools/
|
||||
pushall.sh
|
||||
|
@ -0,0 +1,10 @@
|
||||
{
|
||||
// Prevent "can't find crate for `test`" error on no_std
|
||||
// Ref: https://github.com/rust-lang/vscode-rust/issues/729
|
||||
// For vscode-rust plugin users:
|
||||
"rust.target": "riscv64gc-unknown-none-elf",
|
||||
"rust.all_targets": false,
|
||||
// For Rust Analyzer plugin users:
|
||||
"rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
|
||||
"rust-analyzer.checkOnSave.allTargets": false
|
||||
}
|
Binary file not shown.
@ -1,43 +1,126 @@
|
||||
pub const CLOCK_FREQ: usize = 12500000;
|
||||
|
||||
pub const MMIO: &[(usize, usize)] = &[
|
||||
(0x10001000, 0x1000),
|
||||
(0xC00_0000, 0x40_0000),
|
||||
(0x1000_0000, 0x1000), // VIRT_UART0 in virt machine
|
||||
(0x1000_1000, 0x1000), // VIRT_VIRTIO in virt machine
|
||||
(0x0C00_0000, 0x40_0000), // VIRT_PLIC in virt machine
|
||||
(0x0010_0000, 0x00_2000), // VIRT_TEST/RTC in virt machine
|
||||
];
|
||||
|
||||
pub type BlockDeviceImpl = crate::drivers::block::VirtIOBlock;
|
||||
pub type CharDeviceImpl = crate::drivers::chardev::NS16550a<VIRT_UART>;
|
||||
|
||||
pub const VIRT_PLIC: usize = 0xC00_0000;
|
||||
pub const VIRT_UART: usize = 0x1000_0000;
|
||||
|
||||
use crate::drivers::plic::{PLIC, IntrTargetPriority};
|
||||
use crate::drivers::block::BLOCK_DEVICE;
|
||||
use crate::drivers::chardev::{CharDevice, UART};
|
||||
use crate::drivers::plic::{IntrTargetPriority, PLIC};
|
||||
|
||||
pub fn device_init() {
|
||||
use riscv::register::sie;
|
||||
let mut plic = unsafe { PLIC::new(VIRT_PLIC) };
|
||||
let hart_id: usize = 0;
|
||||
let supervisor = IntrTargetPriority::Supervisor;
|
||||
let machine = IntrTargetPriority::Machine;
|
||||
let machine = IntrTargetPriority::Machine;
|
||||
plic.set_threshold(hart_id, supervisor, 0);
|
||||
plic.set_threshold(hart_id, machine, 1);
|
||||
for intr_src_id in [1usize, 10] {
|
||||
plic.enable(hart_id, supervisor, intr_src_id);
|
||||
plic.enable(hart_id, supervisor, intr_src_id);
|
||||
plic.set_priority(intr_src_id, 1);
|
||||
}
|
||||
crate::println!("Hart0M threshold = {}", plic.get_threshold(hart_id, IntrTargetPriority::Machine));
|
||||
crate::println!("Hart0S threshold = {}", plic.get_threshold(hart_id, IntrTargetPriority::Supervisor));
|
||||
crate::println!("1 prio = {}", plic.get_priority(1));
|
||||
crate::println!("10 prio = {}", plic.get_priority(10));
|
||||
unsafe { sie::set_sext(); }
|
||||
unsafe {
|
||||
sie::set_sext();
|
||||
}
|
||||
}
|
||||
|
||||
use crate::drivers::block::BLOCK_DEVICE;
|
||||
|
||||
pub fn irq_handler() {
|
||||
let mut plic = unsafe { PLIC::new(VIRT_PLIC) };
|
||||
let intr_src_id = plic.claim(0, IntrTargetPriority::Supervisor);
|
||||
match intr_src_id {
|
||||
1 => BLOCK_DEVICE.handle_irq(),
|
||||
10 => UART.handle_irq(),
|
||||
_ => panic!("unsupported IRQ {}", intr_src_id),
|
||||
}
|
||||
plic.complete(0, IntrTargetPriority::Supervisor, intr_src_id);
|
||||
}
|
||||
|
||||
//ref:: https://github.com/andre-richter/qemu-exit
|
||||
use core::arch::asm;
|
||||
|
||||
const EXIT_SUCCESS: u32 = 0x5555; // Equals `exit(0)`. qemu successful exit
|
||||
|
||||
const EXIT_FAILURE_FLAG: u32 = 0x3333;
|
||||
const EXIT_FAILURE: u32 = exit_code_encode(1); // Equals `exit(1)`. qemu failed exit
|
||||
const EXIT_RESET: u32 = 0x7777; // qemu reset
|
||||
|
||||
pub trait QEMUExit {
|
||||
/// Exit with specified return code.
|
||||
///
|
||||
/// Note: For `X86`, code is binary-OR'ed with `0x1` inside QEMU.
|
||||
fn exit(&self, code: u32) -> !;
|
||||
|
||||
/// Exit QEMU using `EXIT_SUCCESS`, aka `0`, if possible.
|
||||
///
|
||||
/// Note: Not possible for `X86`.
|
||||
fn exit_success(&self) -> !;
|
||||
|
||||
/// Exit QEMU using `EXIT_FAILURE`, aka `1`.
|
||||
fn exit_failure(&self) -> !;
|
||||
}
|
||||
|
||||
/// RISCV64 configuration
|
||||
pub struct RISCV64 {
|
||||
/// Address of the sifive_test mapped device.
|
||||
addr: u64,
|
||||
}
|
||||
|
||||
/// Encode the exit code using EXIT_FAILURE_FLAG.
|
||||
const fn exit_code_encode(code: u32) -> u32 {
|
||||
(code << 16) | EXIT_FAILURE_FLAG
|
||||
}
|
||||
|
||||
impl RISCV64 {
|
||||
/// Create an instance.
|
||||
pub const fn new(addr: u64) -> Self {
|
||||
RISCV64 { addr }
|
||||
}
|
||||
}
|
||||
|
||||
impl QEMUExit for RISCV64 {
|
||||
/// Exit qemu with specified exit code.
|
||||
fn exit(&self, code: u32) -> ! {
|
||||
// If code is not a special value, we need to encode it with EXIT_FAILURE_FLAG.
|
||||
let code_new = match code {
|
||||
EXIT_SUCCESS | EXIT_FAILURE | EXIT_RESET => code,
|
||||
_ => exit_code_encode(code),
|
||||
};
|
||||
|
||||
unsafe {
|
||||
asm!(
|
||||
"sw {0}, 0({1})",
|
||||
in(reg)code_new, in(reg)self.addr
|
||||
);
|
||||
|
||||
// For the case that the QEMU exit attempt did not work, transition into an infinite
|
||||
// loop. Calling `panic!()` here is unfeasible, since there is a good chance
|
||||
// this function here is the last expression in the `panic!()` handler
|
||||
// itself. This prevents a possible infinite loop.
|
||||
loop {
|
||||
asm!("wfi", options(nomem, nostack));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn exit_success(&self) -> ! {
|
||||
self.exit(EXIT_SUCCESS);
|
||||
}
|
||||
|
||||
fn exit_failure(&self) -> ! {
|
||||
self.exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
|
||||
const VIRT_TEST: u64 = 0x100000;
|
||||
|
||||
pub const QEMU_EXIT_HANDLE: RISCV64 = RISCV64::new(VIRT_TEST);
|
||||
|
@ -0,0 +1,17 @@
|
||||
mod ns16550a;
|
||||
|
||||
pub use ns16550a::NS16550a;
|
||||
|
||||
use crate::board::CharDeviceImpl;
|
||||
use alloc::sync::Arc;
|
||||
use lazy_static::*;
|
||||
|
||||
pub trait CharDevice {
|
||||
fn read(&self) -> u8;
|
||||
fn write(&self, ch: u8);
|
||||
fn handle_irq(&self);
|
||||
}
|
||||
|
||||
lazy_static! {
|
||||
pub static ref UART: Arc<CharDeviceImpl> = Arc::new(CharDeviceImpl::new());
|
||||
}
|
@ -0,0 +1,175 @@
|
||||
///! Ref: https://www.lammertbies.nl/comm/info/serial-uart
|
||||
///! Ref: ns16550a datasheet: https://datasheetspdf.com/pdf-file/605590/NationalSemiconductor/NS16550A/1
|
||||
///! Ref: ns16450 datasheet: https://datasheetspdf.com/pdf-file/1311818/NationalSemiconductor/NS16450/1
|
||||
use super::CharDevice;
|
||||
use crate::sync::{Condvar, UPIntrFreeCell};
|
||||
use crate::task::schedule;
|
||||
use alloc::collections::VecDeque;
|
||||
use bitflags::*;
|
||||
use volatile::{ReadOnly, Volatile, WriteOnly};
|
||||
|
||||
bitflags! {
|
||||
/// InterruptEnableRegister
|
||||
pub struct IER: u8 {
|
||||
const RX_AVAILABLE = 1 << 0;
|
||||
const TX_EMPTY = 1 << 1;
|
||||
}
|
||||
|
||||
/// LineStatusRegister
|
||||
pub struct LSR: u8 {
|
||||
const DATA_AVAILABLE = 1 << 0;
|
||||
const THR_EMPTY = 1 << 5;
|
||||
}
|
||||
|
||||
/// Model Control Register
|
||||
pub struct MCR: u8 {
|
||||
const DATA_TERMINAL_READY = 1 << 0;
|
||||
const REQUEST_TO_SEND = 1 << 1;
|
||||
const AUX_OUTPUT1 = 1 << 2;
|
||||
const AUX_OUTPUT2 = 1 << 3;
|
||||
}
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[allow(dead_code)]
|
||||
struct ReadWithoutDLAB {
|
||||
/// receiver buffer register
|
||||
pub rbr: ReadOnly<u8>,
|
||||
/// interrupt enable register
|
||||
pub ier: Volatile<IER>,
|
||||
/// interrupt identification register
|
||||
pub iir: ReadOnly<u8>,
|
||||
/// line control register
|
||||
pub lcr: Volatile<u8>,
|
||||
/// model control register
|
||||
pub mcr: Volatile<MCR>,
|
||||
/// line status register
|
||||
pub lsr: ReadOnly<LSR>,
|
||||
/// ignore MSR
|
||||
_padding1: ReadOnly<u8>,
|
||||
/// ignore SCR
|
||||
_padding2: ReadOnly<u8>,
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[allow(dead_code)]
|
||||
struct WriteWithoutDLAB {
|
||||
/// transmitter holding register
|
||||
pub thr: WriteOnly<u8>,
|
||||
/// interrupt enable register
|
||||
pub ier: Volatile<IER>,
|
||||
/// ignore FCR
|
||||
_padding0: ReadOnly<u8>,
|
||||
/// line control register
|
||||
pub lcr: Volatile<u8>,
|
||||
/// modem control register
|
||||
pub mcr: Volatile<MCR>,
|
||||
/// line status register
|
||||
pub lsr: ReadOnly<LSR>,
|
||||
/// ignore other registers
|
||||
_padding1: ReadOnly<u16>,
|
||||
}
|
||||
|
||||
pub struct NS16550aRaw {
|
||||
base_addr: usize,
|
||||
}
|
||||
|
||||
impl NS16550aRaw {
|
||||
fn read_end(&mut self) -> &mut ReadWithoutDLAB {
|
||||
unsafe { &mut *(self.base_addr as *mut ReadWithoutDLAB) }
|
||||
}
|
||||
|
||||
fn write_end(&mut self) -> &mut WriteWithoutDLAB {
|
||||
unsafe { &mut *(self.base_addr as *mut WriteWithoutDLAB) }
|
||||
}
|
||||
|
||||
pub fn new(base_addr: usize) -> Self {
|
||||
Self { base_addr }
|
||||
}
|
||||
|
||||
pub fn init(&mut self) {
|
||||
let read_end = self.read_end();
|
||||
let mut mcr = MCR::empty();
|
||||
mcr |= MCR::DATA_TERMINAL_READY;
|
||||
mcr |= MCR::REQUEST_TO_SEND;
|
||||
mcr |= MCR::AUX_OUTPUT2;
|
||||
read_end.mcr.write(mcr);
|
||||
let ier = IER::RX_AVAILABLE;
|
||||
read_end.ier.write(ier);
|
||||
}
|
||||
|
||||
pub fn read(&mut self) -> Option<u8> {
|
||||
let read_end = self.read_end();
|
||||
let lsr = read_end.lsr.read();
|
||||
if lsr.contains(LSR::DATA_AVAILABLE) {
|
||||
Some(read_end.rbr.read())
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
|
||||
pub fn write(&mut self, ch: u8) {
|
||||
let write_end = self.write_end();
|
||||
loop {
|
||||
if write_end.lsr.read().contains(LSR::THR_EMPTY) {
|
||||
write_end.thr.write(ch);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct NS16550aInner {
|
||||
ns16550a: NS16550aRaw,
|
||||
read_buffer: VecDeque<u8>,
|
||||
}
|
||||
|
||||
pub struct NS16550a<const BASE_ADDR: usize> {
|
||||
inner: UPIntrFreeCell<NS16550aInner>,
|
||||
condvar: Condvar,
|
||||
}
|
||||
|
||||
impl<const BASE_ADDR: usize> NS16550a<BASE_ADDR> {
|
||||
pub fn new() -> Self {
|
||||
let mut inner = NS16550aInner {
|
||||
ns16550a: NS16550aRaw::new(BASE_ADDR),
|
||||
read_buffer: VecDeque::new(),
|
||||
};
|
||||
inner.ns16550a.init();
|
||||
Self {
|
||||
inner: unsafe { UPIntrFreeCell::new(inner) },
|
||||
condvar: Condvar::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<const BASE_ADDR: usize> CharDevice for NS16550a<BASE_ADDR> {
|
||||
fn read(&self) -> u8 {
|
||||
loop {
|
||||
let mut inner = self.inner.exclusive_access();
|
||||
if let Some(ch) = inner.read_buffer.pop_front() {
|
||||
return ch;
|
||||
} else {
|
||||
let task_cx_ptr = self.condvar.wait_no_sched();
|
||||
drop(inner);
|
||||
schedule(task_cx_ptr);
|
||||
}
|
||||
}
|
||||
}
|
||||
fn write(&self, ch: u8) {
|
||||
let mut inner = self.inner.exclusive_access();
|
||||
inner.ns16550a.write(ch);
|
||||
}
|
||||
fn handle_irq(&self) {
|
||||
let mut count = 0;
|
||||
self.inner.exclusive_session(|inner| {
|
||||
while let Some(ch) = inner.ns16550a.read() {
|
||||
count += 1;
|
||||
inner.read_buffer.push_back(ch);
|
||||
}
|
||||
});
|
||||
if count > 0 {
|
||||
self.condvar.signal();
|
||||
}
|
||||
}
|
||||
}
|
@ -1,4 +1,6 @@
|
||||
pub mod block;
|
||||
pub mod chardev;
|
||||
pub mod plic;
|
||||
|
||||
pub use block::BLOCK_DEVICE;
|
||||
pub use chardev::UART;
|
||||
|
@ -1 +1 @@
|
||||
nightly-2022-01-19
|
||||
nightly-2022-04-11
|
||||
|
@ -0,0 +1,2 @@
|
||||
export PATH=$(rustc --print sysroot)/bin:$PATH
|
||||
export RUST_SRC_PATH=$(rustc --print sysroot)/lib/rustlib/src/rust/library/
|
@ -0,0 +1,138 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(core_intrinsics)]
|
||||
|
||||
#[macro_use]
|
||||
extern crate user_lib;
|
||||
extern crate alloc;
|
||||
extern crate core;
|
||||
|
||||
use alloc::vec::Vec;
|
||||
use core::sync::atomic::{AtomicUsize, Ordering};
|
||||
use user_lib::{exit, sleep, thread_create, waittid};
|
||||
|
||||
const N: usize = 2;
|
||||
const THREAD_NUM: usize = 10;
|
||||
|
||||
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
|
||||
enum FlagState {
|
||||
Out,
|
||||
Want,
|
||||
In,
|
||||
}
|
||||
|
||||
static mut TURN: usize = 0;
|
||||
static mut FLAG: [FlagState; THREAD_NUM] = [FlagState::Out; THREAD_NUM];
|
||||
|
||||
static GUARD: AtomicUsize = AtomicUsize::new(0);
|
||||
|
||||
fn critical_test_enter() {
|
||||
assert_eq!(GUARD.fetch_add(1, Ordering::SeqCst), 0);
|
||||
}
|
||||
|
||||
fn critical_test_claim() {
|
||||
assert_eq!(GUARD.load(Ordering::SeqCst), 1);
|
||||
}
|
||||
|
||||
fn critical_test_exit() {
|
||||
assert_eq!(GUARD.fetch_sub(1, Ordering::SeqCst), 1);
|
||||
}
|
||||
|
||||
fn eisenberg_enter_critical(id: usize) {
|
||||
/* announce that we want to enter */
|
||||
loop {
|
||||
println!("Thread[{}] try enter", id);
|
||||
vstore!(&FLAG[id], FlagState::Want);
|
||||
loop {
|
||||
/* check if any with higher priority is `Want` or `In` */
|
||||
let mut prior_thread: Option<usize> = None;
|
||||
let turn = vload!(&TURN);
|
||||
let ring_id = if id < turn { id + THREAD_NUM } else { id };
|
||||
// FLAG.iter() may lead to some errors, use for-loop instead
|
||||
for i in turn..ring_id {
|
||||
if vload!(&FLAG[i % THREAD_NUM]) != FlagState::Out {
|
||||
prior_thread = Some(i % THREAD_NUM);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if prior_thread.is_none() {
|
||||
break;
|
||||
}
|
||||
println!(
|
||||
"Thread[{}]: prior thread {} exist, sleep and retry",
|
||||
id,
|
||||
prior_thread.unwrap()
|
||||
);
|
||||
sleep(1);
|
||||
}
|
||||
/* now tentatively claim the resource */
|
||||
vstore!(&FLAG[id], FlagState::In);
|
||||
/* enforce the order of `claim` and `conflict check`*/
|
||||
memory_fence!();
|
||||
/* check if anthor thread is also `In`, which imply a conflict*/
|
||||
let mut conflict = false;
|
||||
for i in 0..THREAD_NUM {
|
||||
if i != id && vload!(&FLAG[i]) == FlagState::In {
|
||||
conflict = true;
|
||||
}
|
||||
}
|
||||
if !conflict {
|
||||
break;
|
||||
}
|
||||
println!("Thread[{}]: CONFLECT!", id);
|
||||
/* no need to sleep */
|
||||
}
|
||||
/* clain the trun */
|
||||
vstore!(&TURN, id);
|
||||
println!("Thread[{}] enter", id);
|
||||
}
|
||||
|
||||
fn eisenberg_exit_critical(id: usize) {
|
||||
/* find next one who wants to enter and give the turn to it*/
|
||||
let mut next = id;
|
||||
let ring_id = id + THREAD_NUM;
|
||||
for i in (id + 1)..ring_id {
|
||||
let idx = i % THREAD_NUM;
|
||||
if vload!(&FLAG[idx]) == FlagState::Want {
|
||||
next = idx;
|
||||
break;
|
||||
}
|
||||
}
|
||||
vstore!(&TURN, next);
|
||||
/* All done */
|
||||
vstore!(&FLAG[id], FlagState::Out);
|
||||
println!("Thread[{}] exit, give turn to {}", id, next);
|
||||
}
|
||||
|
||||
pub fn thread_fn(id: usize) -> ! {
|
||||
println!("Thread[{}] init.", id);
|
||||
for _ in 0..N {
|
||||
eisenberg_enter_critical(id);
|
||||
critical_test_enter();
|
||||
for _ in 0..3 {
|
||||
critical_test_claim();
|
||||
sleep(2);
|
||||
}
|
||||
critical_test_exit();
|
||||
eisenberg_exit_critical(id);
|
||||
}
|
||||
exit(0)
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
pub fn main() -> i32 {
|
||||
let mut v = Vec::new();
|
||||
// TODO: really shuffle
|
||||
assert_eq!(THREAD_NUM, 10);
|
||||
let shuffle: [usize; 10] = [0, 7, 4, 6, 2, 9, 8, 1, 3, 5];
|
||||
for i in 0..THREAD_NUM {
|
||||
v.push(thread_create(thread_fn as usize, shuffle[i]));
|
||||
}
|
||||
for tid in v.iter() {
|
||||
let exit_code = waittid(*tid as usize);
|
||||
assert_eq!(exit_code, 0, "thread conflict happened!");
|
||||
println!("thread#{} exited with code {}", tid, exit_code);
|
||||
}
|
||||
println!("main thread exited.");
|
||||
0
|
||||
}
|
@ -0,0 +1,78 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(core_intrinsics)]
|
||||
#![feature(asm)]
|
||||
|
||||
#[macro_use]
|
||||
extern crate user_lib;
|
||||
extern crate alloc;
|
||||
extern crate core;
|
||||
|
||||
use alloc::vec::Vec;
|
||||
use core::sync::atomic::{AtomicUsize, Ordering};
|
||||
use user_lib::{exit, sleep, thread_create, waittid};
|
||||
const N: usize = 3;
|
||||
|
||||
static mut TURN: usize = 0;
|
||||
static mut FLAG: [bool; 2] = [false; 2];
|
||||
static GUARD: AtomicUsize = AtomicUsize::new(0);
|
||||
|
||||
fn critical_test_enter() {
|
||||
assert_eq!(GUARD.fetch_add(1, Ordering::SeqCst), 0);
|
||||
}
|
||||
|
||||
fn critical_test_claim() {
|
||||
assert_eq!(GUARD.load(Ordering::SeqCst), 1);
|
||||
}
|
||||
|
||||
fn critical_test_exit() {
|
||||
assert_eq!(GUARD.fetch_sub(1, Ordering::SeqCst), 1);
|
||||
}
|
||||
|
||||
fn peterson_enter_critical(id: usize, peer_id: usize) {
|
||||
println!("Thread[{}] try enter", id);
|
||||
vstore!(&FLAG[id], true);
|
||||
vstore!(&TURN, peer_id);
|
||||
memory_fence!();
|
||||
while vload!(&FLAG[peer_id]) && vload!(&TURN) == peer_id {
|
||||
println!("Thread[{}] enter fail", id);
|
||||
sleep(1);
|
||||
println!("Thread[{}] retry enter", id);
|
||||
}
|
||||
println!("Thread[{}] enter", id);
|
||||
}
|
||||
|
||||
fn peterson_exit_critical(id: usize) {
|
||||
vstore!(&FLAG[id], false);
|
||||
println!("Thread[{}] exit", id);
|
||||
}
|
||||
|
||||
pub fn thread_fn(id: usize) -> ! {
|
||||
println!("Thread[{}] init.", id);
|
||||
let peer_id: usize = id ^ 1;
|
||||
for _ in 0..N {
|
||||
peterson_enter_critical(id, peer_id);
|
||||
critical_test_enter();
|
||||
for _ in 0..3 {
|
||||
critical_test_claim();
|
||||
sleep(2);
|
||||
}
|
||||
critical_test_exit();
|
||||
peterson_exit_critical(id);
|
||||
}
|
||||
exit(0)
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
pub fn main() -> i32 {
|
||||
let mut v = Vec::new();
|
||||
v.push(thread_create(thread_fn as usize, 0));
|
||||
// v.push(thread_create(thread_fn as usize, 1));
|
||||
for tid in v.iter() {
|
||||
let exit_code = waittid(*tid as usize);
|
||||
assert_eq!(exit_code, 0, "thread conflict happened!");
|
||||
println!("thread#{} exited with code {}", tid, exit_code);
|
||||
}
|
||||
println!("main thread exited.");
|
||||
0
|
||||
}
|
Loading…
Reference in new issue