Implement fixup for mipsel and small fixes

crate/memory/src/memory_set/mod.rs

@@ -128,7 +128,8 @@ impl MemoryAttr {
 
 /// A set of memory space with multiple memory areas with associated page table
 /// NOTE: Don't remove align(64), or you will fail to run MIPS.
-#[repr(align(64))]
+/// Temporary solution for rv64
+#[cfg_attr(not(target_arch = "riscv64"), repr(align(64)))]
 pub struct MemorySet<T: PageTableExt> {
     areas: Vec<MemoryArea>,
     page_table: T,

kernel/src/arch/mipsel/board/malta/consts.rs

@@ -1,3 +1,3 @@
 /// board specific constants
-pub const MEMORY_END: usize = 0x8080_0000;
+pub const MEMORY_END: usize = 0x8800_0000;
 pub const KERNEL_HEAP_SIZE: usize = 0x0044_0000;

kernel/src/arch/mipsel/boot/linker.ld

@@ -17,6 +17,9 @@ SECTIONS
         *(.text.entry)
         . = ALIGN(4K);
         *(.text.ebase)
+        _copy_user_start = .;
+        *(.text.copy_user)
+        _copy_user_end = .;
         *(.text .text.*)
         . = ALIGN(4K);
         etext = .;

kernel/src/arch/mipsel/interrupt.rs

@@ -266,6 +266,15 @@ fn page_fault(tf: &mut TrapFrame) {
 
             if !tlb_valid {
                 if !crate::memory::handle_page_fault(addr) {
+                    extern "C" {
+                        fn _copy_user_start();
+                        fn _copy_user_end();
+                    }
+                    if tf.epc >= _copy_user_start as usize && tf.epc < _copy_user_end as usize {
+                        debug!("fixup for addr {:x?}", addr);
+                        tf.epc = crate::memory::read_user_fixup as usize;
+                        return;
+                    }
                     crate::trap::error(tf);
                 }
             }