Merge branch 'dev' of github.com:rcore-os/rCore into dev

README.md

@@ -8,7 +8,7 @@ Going to be the next generation teaching operating system.
 
 Supported architectures: x86_64, RISCV32/64, AArch64, MIPS32
 
-Tested boards: QEMU, HiFive Unleashed, x86_64 PC (i5/i7), Raspberry Pi 3B+
+Tested boards: QEMU, HiFive Unleashed, x86_64 PC (i5/i7), Raspberry Pi 3B+, Kendryte K210 and FPGA running Rocket Chip
 
 ![demo](./docs/2_OSLab/os2atc/demo.png)
 

crate/memory/src/memory_set/mod.rs

@@ -58,7 +58,8 @@ impl MemoryArea {
     fn check_read_array<S>(&self, ptr: *const S, count: usize) -> bool {
         // page align
         ptr as usize >= Page::of_addr(self.start_addr).start_address()
-            && unsafe { ptr.add(count) as usize } < Page::of_addr(self.end_addr + PAGE_SIZE - 1).start_address()
+            && unsafe { ptr.add(count) as usize }
+                < Page::of_addr(self.end_addr + PAGE_SIZE - 1).start_address()
     }
     /// Check the array is within the writable memory
     fn check_write_array<S>(&self, ptr: *mut S, count: usize) -> bool {

kernel/Cargo.toml

@@ -24,6 +24,7 @@ default = ["sv39"]
 sv39 = []
 board_u540 = ["sv39", "link_user"]
 board_k210 = ["sv39", "link_user"]
+board_rocket_chip = ["sv39", "link_user"]
 # (for aarch64 RaspberryPi3)
 nographic = []
 board_raspi3 = ["bcm2837", "link_user"]

kernel/Makefile

@@ -26,6 +26,7 @@
 #         | pc                   Only available on x86_64, run on real pc
 #         | u540                 Only available on riscv64, run on HiFive U540, use Sv39
 #         | k210                 Only available on riscv64, run on K210, use Sv39
+#         | rocket_chip          Only available on riscv64, run on Rocket Chip, use Sv39
 #         | raspi3               Only available on aarch64, run on Raspberry Pi 3 Model B/B+
 #   pci_passthru = 0000:00:00.1  Only available on x86_64, passthrough the specified PCI device
 #   init = /bin/ls               Only available on riscv64, run specified program instead of user shell
@@ -60,7 +61,7 @@ ifeq ($(arch), $(filter $(arch), aarch64 mipsel))
 export SFSIMG = $(user_dir)/build/$(arch).img
 else
 # board is pc or qemu?
-ifeq ($(board), $(filter $(board), pc u540 k210))
+ifeq ($(board), $(filter $(board), pc u540 k210 rocket_chip))
 #link user img, so use original image
 export SFSIMG = $(user_dir)/build/$(arch).img
 else

kernel/src/arch/riscv32/boot/linker64.ld

@@ -0,0 +1,49 @@
+/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore      */
+
+/* Simple linker script for the ucore kernel.
+   See the GNU ld 'info' manual ("info ld") to learn the syntax. */
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+BASE_ADDRESS = 0xffffffffc0200000;
+
+SECTIONS
+{
+    /* Load the kernel at this address: "." means the current address */
+    . = BASE_ADDRESS;
+    start = .;
+
+    .text : {
+        stext = .;
+        *(.text.entry)
+        *(.text .text.*)
+        . = ALIGN(4K);
+        etext = .;
+    }
+
+    .rodata : {
+        srodata = .;
+        *(.rodata .rodata.*)
+        . = ALIGN(4K);
+        erodata = .;
+    }
+
+    .data : {
+        sdata = .;
+        *(.data .data.*)
+        edata = .;
+    }
+
+    .stack : {
+        *(.bss.stack)
+    }
+
+    .bss : {
+        sbss = .;
+        *(.bss .bss.*)
+        ebss = .;
+    }
+
+    PROVIDE(end = .);
+}

kernel/src/arch/riscv32/memory.rs

@@ -92,6 +92,8 @@ fn remap_the_kernel(dtb: usize) {
         Linear::new(offset),
         "bss",
     );
+    // TODO: dtb on rocket chip
+    #[cfg(not(feature = "board_rocket_chip"))]
     ms.push(
         dtb,
         dtb + super::consts::MAX_DTB_SIZE,

kernel/src/arch/riscv32/mod.rs

@@ -53,10 +53,11 @@ pub extern "C" fn rust_main(hartid: usize, device_tree_paddr: usize) -> ! {
     memory::init(device_tree_vaddr);
     timer::init();
     // FIXME: init driver on u540
-    #[cfg(not(feature = "board_u540"))]
+    #[cfg(not(any(feature = "board_u540", feature = "board_rocket_chip")))]
     crate::drivers::init(device_tree_vaddr);
     #[cfg(not(feature = "board_k210"))]
     unsafe {
+        #[cfg(not(feature = "board_rocket_chip"))]
         board::enable_serial_interrupt();
         board::init_external_interrupt();
     }

tools/opensbi/README.md

@@ -2,14 +2,12 @@
 
 These are binary release of OpenSBI on this [commit](https://github.com/riscv/opensbi/tree/194dbbe5a13dff2255411c26d249f3ad4ef42c0b) at 2019.04.15.
 
-- fu540.elf: opensbi-0.3-rv64-bin/platform/sifive/fu540/firmware/fw_jump.elf
 - virt_rv32.elf: opensbi-0.3-rv32-bin/platform/qemu/virt/firmware/fw_jump.elf
 - virt_rv64.elf: opensbi-0.3-rv64-bin/platform/qemu/virt/firmware/fw_jump.elf
 
-NOTE: The [official v0.3 release](https://github.com/riscv/opensbi/releases/tag/v0.3) has bug on serial interrupt.
+NOTE: The [official v0.3 release](https://github.com/riscv/opensbi/releases/tag/v0.3) has bug on serial interrupt. Also, Rocket-Chip based CPUs (including SiFive Unleashed) seem to have unintended behavior on
 
+For K210 & SiFive Unleashed: It needs some modification. The binary is from this [commit](https://github.com/rcore-os/opensbi/commit/a9638d092756975ceb50073d736a17cef439c7b6).
 
-
-For K210: It needs some modification. The binary is from this [commit](https://github.com/rcore-os/opensbi/commit/4400a1a7d40b5399b3e07b4bad9fd303885c8c16).
-
-* k210.elf: build/platform/kendryte/k210/firmware/fw_payload.elf
+* k210.elf: build/platform/kendryte/k210/firmware/fw_payload.elf
+* fu540.elf: build/platform/sifive/fu540/firmware/fw_jump.elf