Support 32bit MSI Addr

kernel/Cargo.lock

@@ -208,6 +208,7 @@ source = "git+https://github.com/rcore-os/isomorphic_drivers#fe4af36d5f7bf3ac32b
 dependencies = [
  "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
+ "log 0.4.6 (registry+https://github.com/rust-lang/crates.io-index)",
  "spin 0.5.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "volatile 0.2.6 (registry+https://github.com/rust-lang/crates.io-index)",
 ]

kernel/Cargo.toml

@@ -59,7 +59,7 @@ console-traits = "0.3"
 buddy_system_allocator = "0.3"
 pci = { git = "https://github.com/rcore-os/pci-rs" }
 device_tree = { git = "https://github.com/rcore-os/device_tree-rs" }
-isomorphic_drivers = { git = "https://github.com/rcore-os/isomorphic_drivers" }
+isomorphic_drivers = { git = "https://github.com/rcore-os/isomorphic_drivers", features = ["log"] }
 lazy_static = { version = "1.3", features = ["spin_no_std"] }
 smoltcp = { git = "https://github.com/rcore-os/smoltcp", default-features = false, features = ["alloc", "log", "proto-ipv4", "proto-igmp", "socket-icmp", "socket-udp", "socket-tcp", "socket-raw"] }
 bitmap-allocator = { git = "https://github.com/rcore-os/bitmap-allocator" }

kernel/src/drivers/bus/pci.rs

@@ -16,7 +16,8 @@ const PCI_INTERRUPT_PIN: u16 = 0x3d;
 const PCI_MSI_CTRL_CAP: u16 = 0x00;
 const PCI_MSI_ADDR: u16 = 0x04;
 const PCI_MSI_UPPER_ADDR: u16 = 0x08;
-const PCI_MSI_DATA: u16 = 0x0C;
+const PCI_MSI_DATA_32: u16 = 0x08;
+const PCI_MSI_DATA_64: u16 = 0x0C;
 
 const PCI_CAP_ID_MSI: u8 = 0x05;
 
@@ -94,6 +95,7 @@ unsafe fn enable(loc: Location) -> Option<u32> {
     while cap_ptr > 0 {
         let cap_id = am.read8(ops, loc, cap_ptr);
         if cap_id == PCI_CAP_ID_MSI {
+            let orig_ctrl = am.read32(ops, loc, cap_ptr + PCI_MSI_CTRL_CAP);
             // The manual Volume 3 Chapter 10.11 Message Signalled Interrupts
             // 0 is (usually) the apic id of the bsp.
             am.write32(ops, loc, cap_ptr + PCI_MSI_ADDR, 0xfee00000 | (0 << 12));
@@ -101,10 +103,15 @@ unsafe fn enable(loc: Location) -> Option<u32> {
             let irq = MSI_IRQ;
             assigned_irq = Some(irq);
             // we offset all our irq numbers by 32
-            am.write32(ops, loc, cap_ptr + PCI_MSI_DATA, irq + 32);
+            if (orig_ctrl >> 16) & (1 << 7) != 0 {
+                // 64bit
+                am.write32(ops, loc, cap_ptr + PCI_MSI_DATA_64, irq + 32);
+            } else {
+                // 32bit
+                am.write32(ops, loc, cap_ptr + PCI_MSI_DATA_32, irq + 32);
+            }
 
             // enable MSI interrupt, assuming 64bit for now
-            let orig_ctrl = am.read32(ops, loc, cap_ptr + PCI_MSI_CTRL_CAP);
             am.write32(ops, loc, cap_ptr + PCI_MSI_CTRL_CAP, orig_ctrl | 0x10000);
             debug!(
                 "MSI control {:#b}, enabling MSI interrupt {}",
@@ -112,7 +119,6 @@ unsafe fn enable(loc: Location) -> Option<u32> {
                 irq
             );
             msi_found = true;
-            break;
         }
         debug!("PCI device has cap id {} at {:#X}", cap_id, cap_ptr);
         cap_ptr = am.read8(ops, loc, cap_ptr + 1) as u16;
@@ -125,6 +131,8 @@ unsafe fn enable(loc: Location) -> Option<u32> {
         debug!("MSI not found, using PCI interrupt");
     }
 
+    info!("pci device enable done");
+
     assigned_irq
 }
 
@@ -162,6 +170,7 @@ pub fn init_driver(dev: &PCIDevice) {
             // 200 Series PCH SATA controller [AHCI mode]
             // C610/X99 series chipset 6-Port SATA Controller [AHCI mode]
             if let Some(BAR::Memory(addr, len, _, _)) = dev.bars[5] {
+                info!("Found AHCI dev {:?} BAR5 {:x?}", dev, addr);
                 let irq = unsafe { enable(dev.loc) };
                 assert!(len as usize <= PAGE_SIZE);
                 let vaddr = phys_to_virt(addr as usize);