equation314
6 years ago
parent
8bb1e65ba7
commit
0e38439fb8
@ -1,24 +1,130 @@
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use core::slice;
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use aarch64::addr::{VirtAddr, PhysAddr};
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use aarch64::paging::{memory_attribute::*, Page, PageTable, PageTableFlags as EF, PhysFrame};
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use aarch64::paging::{Size4KiB, Size2MiB, Size1GiB};
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use aarch64::{asm::*, barrier, regs::*};
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use core::ptr;
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use fixedvec::FixedVec;
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use xmas_elf::program::{ProgramHeader64, Type};
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const PAGE_SIZE: usize = 4096;
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const ALIGN_2MB: u64 = 0x200000;
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const IO_REMAP_BASE: u64 = 0x3F00_0000;
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const MEMORY_END: u64 = 0x4000_0000;
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const RECURSIVE_INDEX: usize = 0o777;
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const KERNEL_OFFSET: u64 = 0x0000_0000_0000_0000;
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global_asm!(include_str!("boot.S"));
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pub fn map_kernel(kernel_start: u64, segments: &FixedVec<ProgramHeader64>) {
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fn setup_temp_page_table(start_vaddr: VirtAddr, end_vaddr: VirtAddr, offset: u64) {
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#[repr(align(4096))]
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struct PageData([u8; PAGE_SIZE]);
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static mut PAGE_TABLE_LVL4: PageData = PageData([0; PAGE_SIZE]);
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static mut PAGE_TABLE_LVL3: PageData = PageData([0; PAGE_SIZE]);
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static mut PAGE_TABLE_LVL2: PageData = PageData([0; PAGE_SIZE]);
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let frame_lvl4 = unsafe { PhysFrame::<Size4KiB>::containing_address(PhysAddr::new(&PAGE_TABLE_LVL4 as *const _ as u64)) };
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let frame_lvl3 = unsafe { PhysFrame::<Size4KiB>::containing_address(PhysAddr::new(&PAGE_TABLE_LVL3 as *const _ as u64)) };
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let frame_lvl2 = unsafe { PhysFrame::<Size4KiB>::containing_address(PhysAddr::new(&PAGE_TABLE_LVL2 as *const _ as u64)) };
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let p4 = unsafe { &mut *(frame_lvl4.start_address().as_u64() as *mut PageTable) };
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let p3 = unsafe { &mut *(frame_lvl3.start_address().as_u64() as *mut PageTable) };
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let p2 = unsafe { &mut *(frame_lvl2.start_address().as_u64() as *mut PageTable) };
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p4.zero();
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p3.zero();
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p2.zero();
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let block_flags = EF::VALID | EF::AF | EF::WRITE | EF::UXN;
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// normal memory
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for page in Page::<Size2MiB>::range_of(start_vaddr.as_u64(), end_vaddr.as_u64()) {
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let paddr = PhysAddr::new(page.start_address().as_u64().wrapping_add(offset));
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p2[page.p2_index()].set_block::<Size2MiB>(paddr, block_flags, MairNormal::attr_value());
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}
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// device memory
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for page in Page::<Size2MiB>::range_of(IO_REMAP_BASE, MEMORY_END) {
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let paddr = PhysAddr::new(page.start_address().as_u64());
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p2[page.p2_index()].set_block::<Size2MiB>(paddr, block_flags | EF::PXN, MairDevice::attr_value());
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}
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p3[0].set_frame(frame_lvl2, EF::default(), MairNormal::attr_value());
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p3[1].set_block::<Size1GiB>(PhysAddr::new(MEMORY_END), block_flags | EF::PXN, MairDevice::attr_value());
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p4[0].set_frame(frame_lvl3, EF::default(), MairNormal::attr_value());
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p4[RECURSIVE_INDEX].set_frame(frame_lvl4, EF::default(), MairNormal::attr_value());
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ttbr_el1_write(VirtAddr::new(KERNEL_OFFSET).va_range().unwrap() as u8, frame_lvl4);
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tlb_invalidate_all();
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}
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fn enable_mmu() {
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MAIR_EL1.write(
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MAIR_EL1::Attr0.val(MairNormal::config_value()) +
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MAIR_EL1::Attr1.val(MairDevice::config_value()) +
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MAIR_EL1::Attr2.val(MairNormalNonCacheable::config_value()),
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);
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// Configure various settings of stage 1 of the EL1 translation regime.
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let ips = ID_AA64MMFR0_EL1.read(ID_AA64MMFR0_EL1::PARange);
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TCR_EL1.write(
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TCR_EL1::TBI1::Ignored +
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TCR_EL1::TBI0::Ignored +
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TCR_EL1::AS::Bits_16 +
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TCR_EL1::IPS.val(ips) +
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TCR_EL1::TG1::KiB_4 +
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TCR_EL1::SH1::Inner +
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TCR_EL1::ORGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable +
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TCR_EL1::IRGN1::WriteBack_ReadAlloc_WriteAlloc_Cacheable +
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TCR_EL1::EPD1::EnableTTBR1Walks +
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TCR_EL1::A1::UseTTBR1ASID +
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TCR_EL1::T1SZ.val(16) +
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TCR_EL1::TG0::KiB_4 +
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TCR_EL1::SH0::Inner +
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TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable +
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TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable +
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TCR_EL1::EPD0::EnableTTBR0Walks +
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TCR_EL1::T0SZ.val(16),
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);
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// Switch the MMU on.
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//
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// First, force all previous changes to be seen before the MMU is enabled.
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unsafe { barrier::isb(barrier::SY) }
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// Enable the MMU and turn on data and instruction caching.
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SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
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// Force MMU init to complete before next instruction
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unsafe { barrier::isb(barrier::SY) }
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}
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pub fn map_kernel(kernel_start: usize, segments: &FixedVec<ProgramHeader64>) {
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let (mut start_vaddr, mut end_vaddr) = (VirtAddr::new(core::u64::MAX), VirtAddr::zero());
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for segment in segments {
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if segment.get_type() != Ok(Type::Load) {
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continue;
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}
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let virt_addr = segment.virtual_addr;
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let offset = segment.offset;
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let file_size = segment.file_size as usize;
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let mem_size = segment.mem_size as usize;
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let file_size = segment.file_size;
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let mem_size = segment.mem_size;
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unsafe {
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let target = slice::from_raw_parts_mut(virt_addr as *mut u8, mem_size);
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let source = slice::from_raw_parts((kernel_start + offset) as *const u8, file_size);
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target.copy_from_slice(source);
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target[file_size..].iter_mut().for_each(|x| *x = 0);
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let src = (kernel_start as u64 + offset) as *const u8;
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let dst = virt_addr as *mut u8;
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ptr::copy(src, dst, file_size as usize);
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ptr::write_bytes((virt_addr + file_size) as *mut u8, 0, (mem_size - file_size) as usize);
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}
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if virt_addr < start_vaddr.as_u64() {
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start_vaddr = VirtAddr::new(virt_addr).align_down(ALIGN_2MB);
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}
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if virt_addr + mem_size > end_vaddr.as_u64() {
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end_vaddr = VirtAddr::new(virt_addr + mem_size).align_up(ALIGN_2MB);
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}
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}
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setup_temp_page_table(start_vaddr, end_vaddr, KERNEL_OFFSET.wrapping_neg());
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enable_mmu();
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}
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