fix compile on riscv

master
WangRunji 6 years ago
parent b304764fb5
commit 0f339fcbf8

@ -2,31 +2,34 @@
use rcore_memory::memory_set::handler::Linear; use rcore_memory::memory_set::handler::Linear;
use rcore_memory::memory_set::MemoryAttr; use rcore_memory::memory_set::MemoryAttr;
use super::*; use super::*;
use crate::drivers::bus::pci;
#[cfg(target_arch = "x86_64")]
pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult { pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult {
use crate::drivers::bus::pci;
info!( info!(
"map_pci_device: vendor: {}, product: {}", "map_pci_device: vendor: {}, product: {}",
vendor, product vendor, product
); );
if let Some(tag) = pci::find_device(vendor as u32, product as u32) { let tag = pci::find_device(vendor as u32, product as u32)
// Get BAR0 memory .ok_or(SysError::ENOENT)?;
if let Some((base, len)) = unsafe { tag.get_bar_mem(0) } { // Get BAR0 memory
let mut proc = process(); let (base, len) = unsafe { tag.get_bar_mem(0) }
let virt_addr = proc.memory_set.find_free_area(0, len); .ok_or(SysError::ENOENT)?;
let attr = MemoryAttr::default().user();
proc.memory_set.push( let mut proc = process();
virt_addr, let virt_addr = proc.memory_set.find_free_area(0, len);
virt_addr + len, let attr = MemoryAttr::default().user();
attr, proc.memory_set.push(
Linear::new(base as isize - virt_addr as isize), virt_addr,
"pci", virt_addr + len,
); attr,
Ok(virt_addr) Linear::new(base as isize - virt_addr as isize),
} else { "pci",
Err(SysError::ENOENT) );
} Ok(virt_addr)
} else { }
Err(SysError::ENOENT)
} #[cfg(not(target_arch = "x86_64"))]
pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult {
Err(SysError::ENOSYS)
} }
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