fix compile on riscv

master
WangRunji 6 years ago
parent b304764fb5
commit 0f339fcbf8

@ -2,16 +2,20 @@
use rcore_memory::memory_set::handler::Linear;
use rcore_memory::memory_set::MemoryAttr;
use super::*;
use crate::drivers::bus::pci;
#[cfg(target_arch = "x86_64")]
pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult {
use crate::drivers::bus::pci;
info!(
"map_pci_device: vendor: {}, product: {}",
vendor, product
);
if let Some(tag) = pci::find_device(vendor as u32, product as u32) {
let tag = pci::find_device(vendor as u32, product as u32)
.ok_or(SysError::ENOENT)?;
// Get BAR0 memory
if let Some((base, len)) = unsafe { tag.get_bar_mem(0) } {
let (base, len) = unsafe { tag.get_bar_mem(0) }
.ok_or(SysError::ENOENT)?;
let mut proc = process();
let virt_addr = proc.memory_set.find_free_area(0, len);
let attr = MemoryAttr::default().user();
@ -23,10 +27,9 @@ pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult {
"pci",
);
Ok(virt_addr)
} else {
Err(SysError::ENOENT)
}
} else {
Err(SysError::ENOENT)
}
}
#[cfg(not(target_arch = "x86_64"))]
pub fn sys_map_pci_device(vendor: usize, product: usize) -> SysResult {
Err(SysError::ENOSYS)
}
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