WangRunji
7 years ago
parent
296b6196f4
commit
10e3cea340
@ -1,103 +0,0 @@
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--- atomic_backup.rs 2018-07-10 00:29:48.000000000 +0800
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+++ atomic.rs 2018-07-12 18:32:26.000000000 +0800
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@@ -1556,15 +1556,9 @@
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}
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#[inline]
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-unsafe fn atomic_store<T>(dst: *mut T, val: T, order: Ordering) {
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- match order {
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- Release => intrinsics::atomic_store_rel(dst, val),
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- Relaxed => intrinsics::atomic_store_relaxed(dst, val),
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- SeqCst => intrinsics::atomic_store(dst, val),
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- Acquire => panic!("there is no such thing as an acquire store"),
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- AcqRel => panic!("there is no such thing as an acquire/release store"),
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- __Nonexhaustive => panic!("invalid memory ordering"),
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- }
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+unsafe fn atomic_store<T>(dst: *mut T, val: T, _order: Ordering) {
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+ use ptr::write;
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+ write(dst, val);
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}
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#[inline]
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@@ -1580,15 +1574,22 @@
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}
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#[inline]
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-unsafe fn atomic_swap<T>(dst: *mut T, val: T, order: Ordering) -> T {
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- match order {
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- Acquire => intrinsics::atomic_xchg_acq(dst, val),
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- Release => intrinsics::atomic_xchg_rel(dst, val),
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- AcqRel => intrinsics::atomic_xchg_acqrel(dst, val),
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- Relaxed => intrinsics::atomic_xchg_relaxed(dst, val),
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- SeqCst => intrinsics::atomic_xchg(dst, val),
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- __Nonexhaustive => panic!("invalid memory ordering"),
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+unsafe fn atomic_swap<T>(dst: *mut T, val: T, _order: Ordering) -> T {
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+ let sstatus: usize;
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+ asm!("csrrs $0, 0x100, x0" : "=r"(sstatus) ::: "volatile");
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+ // Disable interrupt: sstatus::clear_sie()
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+ asm!("csrrc x0, 0x100, $0" :: "r"(1) :: "volatile");
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+
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+ use ptr::{read, write};
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+ let ret = read(dst);
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+ write(dst, val);
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+
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+ let sie = sstatus & 1 != 0;
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+ if sie {
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+ // Enable interrupt: sstatus::set_sie()
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+ asm!("csrrs x0, 0x100, $0" :: "r"(1) :: "volatile");
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}
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+ ret
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}
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/// Returns the previous value (like __sync_fetch_and_add).
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@@ -1618,29 +1619,30 @@
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}
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#[inline]
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-unsafe fn atomic_compare_exchange<T>(dst: *mut T,
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+#[cfg(target_arch = "riscv32")]
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+unsafe fn atomic_compare_exchange<T: PartialEq>(dst: *mut T,
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old: T,
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new: T,
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- success: Ordering,
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- failure: Ordering)
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+ _success: Ordering,
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+ _failure: Ordering)
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-> Result<T, T> {
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- let (val, ok) = match (success, failure) {
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- (Acquire, Acquire) => intrinsics::atomic_cxchg_acq(dst, old, new),
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- (Release, Relaxed) => intrinsics::atomic_cxchg_rel(dst, old, new),
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- (AcqRel, Acquire) => intrinsics::atomic_cxchg_acqrel(dst, old, new),
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- (Relaxed, Relaxed) => intrinsics::atomic_cxchg_relaxed(dst, old, new),
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- (SeqCst, SeqCst) => intrinsics::atomic_cxchg(dst, old, new),
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- (Acquire, Relaxed) => intrinsics::atomic_cxchg_acq_failrelaxed(dst, old, new),
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- (AcqRel, Relaxed) => intrinsics::atomic_cxchg_acqrel_failrelaxed(dst, old, new),
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- (SeqCst, Relaxed) => intrinsics::atomic_cxchg_failrelaxed(dst, old, new),
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- (SeqCst, Acquire) => intrinsics::atomic_cxchg_failacq(dst, old, new),
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- (__Nonexhaustive, _) => panic!("invalid memory ordering"),
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- (_, __Nonexhaustive) => panic!("invalid memory ordering"),
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- (_, AcqRel) => panic!("there is no such thing as an acquire/release failure ordering"),
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- (_, Release) => panic!("there is no such thing as a release failure ordering"),
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- _ => panic!("a failure ordering can't be stronger than a success ordering"),
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- };
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- if ok { Ok(val) } else { Err(val) }
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+ let sstatus: usize;
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+ asm!("csrrs $0, 0x100, x0" : "=r"(sstatus) ::: "volatile");
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+ // Disable interrupt: sstatus::clear_sie()
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+ asm!("csrrc x0, 0x100, $0" :: "r"(1) :: "volatile");
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+
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+ use ptr::{read, write};
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+ let ret = read(dst);
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+ if ret == old {
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+ write(dst, new);
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+ }
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+
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+ let sie = sstatus & 1 != 0;
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+ if sie {
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+ // Enable interrupt: sstatus::set_sie()
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+ asm!("csrrs x0, 0x100, $0" :: "r"(1) :: "volatile");
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+ }
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+ Ok(ret)
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}
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#[inline]
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@ -0,0 +1,73 @@
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//! Workaround for missing compiler-builtin symbols
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//!
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//! [atomic](http://llvm.org/docs/Atomics.html#libcalls-atomic)
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/// Copy from:
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/// https://github.com/rust-lang-nursery/compiler-builtins/blob/master/src/riscv32.rs
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#[no_mangle]
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pub extern fn __mulsi3(mut a: u32, mut b: u32) -> u32 {
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let mut r: u32 = 0;
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while a > 0 {
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if a & 1 > 0 {
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r += b;
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}
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a >>= 1;
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b <<= 1;
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}
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r
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}
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#[no_mangle]
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pub extern fn abort() {
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loop {}
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}
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use core::ptr::{read, write};
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#[no_mangle]
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pub unsafe extern fn __atomic_load_1(src: *const u8) -> u8 {
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read(src)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_load_2(src: *const u16) -> u16 {
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read(src)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_load_4(src: *const u32) -> u32 {
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read(src)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_store_1(dst: *mut u8, val: u8) {
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write(dst, val)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_store_4(dst: *mut u32, val: u32) {
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write(dst, val)
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}
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unsafe fn __atomic_compare_exchange<T: PartialEq>(dst: *mut T, old: T, new: T) -> (T, bool) {
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use super::interrupt;
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let flags = interrupt::disable_and_store();
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let ret = read(dst);
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if ret == old {
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write(dst, new);
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}
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interrupt::restore(flags);
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(ret, true)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_compare_exchange_1(dst: *mut u8, old: u8, src: u8) -> (u8, bool) {
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__atomic_compare_exchange(dst, old, src)
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}
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#[no_mangle]
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pub unsafe extern fn __atomic_compare_exchange_4(dst: *mut u32, old: u32, src: u32) -> (u32, bool) {
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__atomic_compare_exchange(dst, old, src)
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}
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@ -0,0 +1,6 @@
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#![no_std] // don't link the Rust standard library
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#![cfg_attr(not(test), no_main)] // disable all Rust-level entry points
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#![cfg_attr(test, allow(dead_code, unused_macros, unused_imports))]
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#[macro_use]
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extern crate ucore;
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