Fix rcore router for linear mapping

kernel/src/arch/riscv32/memory.rs

@@ -1,4 +1,4 @@
-use crate::consts::{KERNEL_OFFSET, MEMORY_END, MEMORY_OFFSET};
+use crate::consts::{KERNEL_OFFSET, MEMORY_END, MEMORY_OFFSET, PHYSICAL_MEMORY_OFFSET};
 use crate::memory::{init_heap, Linear, MemoryAttr, MemorySet, FRAME_ALLOCATOR};
 use core::mem;
 use log::*;

kernel/src/arch/riscv32/paging.rs

@@ -157,7 +157,7 @@ impl PageTableImpl {
         PageTableImpl {
             page_table: TopLevelPageTable::new(table, PHYSICAL_MEMORY_OFFSET),
             root_frame: frame,
-            entry: unsafe { core::mem::uninitialized() },
+            entry: unsafe { core::mem::MaybeUninit::uninitialized().into_initialized() },
         }
     }
 }
@@ -173,7 +173,7 @@ impl PageTableExt for PageTableImpl {
         PageTableImpl {
             page_table: TopLevelPageTable::new(table, PHYSICAL_MEMORY_OFFSET),
             root_frame: frame,
-            entry: unsafe { core::mem::uninitialized() },
+            entry: unsafe { core::mem::MaybeUninit::uninitialized().into_initialized() },
         }
     }
 
@@ -191,6 +191,10 @@ impl PageTableExt for PageTableImpl {
         }
         #[cfg(target_arch = "riscv64")]
         for i in 509..512 {
+            if (i == 510) {
+                // MMIO range 0x60000000 - 0x7FFFFFFF does not work as a large page, dunno why
+                continue;
+            }
             let flags =
                 EF::VALID | EF::READABLE | EF::WRITABLE | EF::EXECUTABLE | EF::ACCESSED | EF::DIRTY;
             let frame = Frame::of_addr(PhysAddr::new(
@@ -198,6 +202,42 @@ impl PageTableExt for PageTableImpl {
             ));
             table[i].set(frame, flags);
         }
+
+        // MMIO range 0x60000000 - 0x7FFFFFFF does not work as a large page, dunno why
+        let flags = EF::VALID | EF::READABLE | EF::WRITABLE;
+        // map Uartlite for Rocket Chip
+        #[cfg(feature = "board_rocket_chip")]
+        self.page_table
+            .map_to(
+                Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x6000_0000)),
+                Frame::of_addr(PhysAddr::new(0x6000_0000)),
+                flags,
+                &mut FrameAllocatorForRiscv,
+            )
+            .unwrap()
+            .flush();
+        // map AXI INTC for Rocket Chip
+        #[cfg(feature = "board_rocket_chip")]
+        self.page_table
+            .map_to(
+                Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x6120_0000)),
+                Frame::of_addr(PhysAddr::new(0x6120_0000)),
+                flags,
+                &mut FrameAllocatorForRiscv,
+            )
+            .unwrap()
+            .flush();
+        // map AXI4-Stream Data FIFO for Rocket Chip
+        #[cfg(feature = "board_rocket_chip")]
+        self.page_table
+            .map_to(
+                Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x64A0_0000)),
+                Frame::of_addr(PhysAddr::new(0x64A0_0000)),
+                flags,
+                &mut FrameAllocatorForRiscv,
+            )
+            .unwrap()
+            .flush();
     }
 
     fn token(&self) -> usize {

kernel/src/drivers/net/router.rs

@@ -20,17 +20,17 @@ use crate::sync::SpinNoIrqLock as Mutex;
 use super::super::{DeviceType, Driver, DRIVERS, NET_DRIVERS, SOCKET_ACTIVITY};
 use crate::memory::phys_to_virt;
 
-const AXI_STREAM_FIFO_ISR: *mut u32 = phys_to_virt(0x1820_0000) as *mut u32;
+const AXI_STREAM_FIFO_ISR: *mut u32 = phys_to_virt(0x64A0_0000) as *mut u32;
-const AXI_STREAM_FIFO_IER: *mut u32 = phys_to_virt(0x1820_0004) as *mut u32;
+const AXI_STREAM_FIFO_IER: *mut u32 = phys_to_virt(0x64A0_0004) as *mut u32;
-const AXI_STREAM_FIFO_TDFR: *mut u32 = phys_to_virt(0x1820_0008) as *mut u32;
+const AXI_STREAM_FIFO_TDFR: *mut u32 = phys_to_virt(0x64A0_0008) as *mut u32;
-const AXI_STREAM_FIFO_TDFD: *mut u32 = phys_to_virt(0x1820_0010) as *mut u32;
+const AXI_STREAM_FIFO_TDFD: *mut u32 = phys_to_virt(0x64A0_0010) as *mut u32;
-const AXI_STREAM_FIFO_TLR: *mut u32 = phys_to_virt(0x1820_0014) as *mut u32;
+const AXI_STREAM_FIFO_TLR: *mut u32 = phys_to_virt(0x64A0_0014) as *mut u32;
-const AXI_STREAM_FIFO_RDFR: *mut u32 = phys_to_virt(0x1820_0018) as *mut u32;
+const AXI_STREAM_FIFO_RDFR: *mut u32 = phys_to_virt(0x64A0_0018) as *mut u32;
-const AXI_STREAM_FIFO_RDFO: *mut u32 = phys_to_virt(0x1820_001C) as *mut u32;
+const AXI_STREAM_FIFO_RDFO: *mut u32 = phys_to_virt(0x64A0_001C) as *mut u32;
-const AXI_STREAM_FIFO_RDFD: *mut u32 = phys_to_virt(0x1820_0020) as *mut u32;
+const AXI_STREAM_FIFO_RDFD: *mut u32 = phys_to_virt(0x64A0_0020) as *mut u32;
-const AXI_STREAM_FIFO_RLR: *mut u32 = phys_to_virt(0x1820_0024) as *mut u32;
+const AXI_STREAM_FIFO_RLR: *mut u32 = phys_to_virt(0x64A0_0024) as *mut u32;
-const AXI_STREAM_FIFO_TDR: *mut u32 = phys_to_virt(0x1820_002C) as *mut u32;
+const AXI_STREAM_FIFO_TDR: *mut u32 = phys_to_virt(0x64A0_002C) as *mut u32;
-const AXI_STREAM_FIFO_RDR: *mut u32 = phys_to_virt(0x1820_0030) as *mut u32;
+const AXI_STREAM_FIFO_RDR: *mut u32 = phys_to_virt(0x64A0_0030) as *mut u32;
 
 pub struct Router {
     buffer: Vec<Vec<u8>>,