Implement tx for router driver

master
Jiajie Chen 6 years ago
parent 5932372750
commit 2653069a43

@ -45,4 +45,4 @@ pub unsafe fn enable_serial_interrupt() {
// Intr enable | rx reset | tx reset // Intr enable | rx reset | tx reset
const UART_IE: u32 = 0x13; const UART_IE: u32 = 0x13;
SERIAL_BASE.add(UART_CTRL_REG).write_volatile(UART_IE); SERIAL_BASE.add(UART_CTRL_REG).write_volatile(UART_IE);
} }

@ -1,4 +1,4 @@
pub mod e1000; pub mod e1000;
pub mod ixgbe; pub mod ixgbe;
pub mod router;
pub mod virtio_net; pub mod virtio_net;
pub mod router;

@ -28,17 +28,21 @@ const AXI_STREAM_FIFO_RDFD: *mut u32 = (KERNEL_OFFSET + 0x1820_0020) as *mut u32
const AXI_STREAM_FIFO_RLR: *mut u32 = (KERNEL_OFFSET + 0x1820_0024) as *mut u32; const AXI_STREAM_FIFO_RLR: *mut u32 = (KERNEL_OFFSET + 0x1820_0024) as *mut u32;
const AXI_STREAM_FIFO_RDR: *mut u32 = (KERNEL_OFFSET + 0x1820_0030) as *mut u32; const AXI_STREAM_FIFO_RDR: *mut u32 = (KERNEL_OFFSET + 0x1820_0030) as *mut u32;
const AXI_STREAM_FIFO_TDR: *mut u32 = (KERNEL_OFFSET + 0x1820_002C) as *mut u32;
const AXI_STREAM_FIFO_TDFD: *mut u32 = (KERNEL_OFFSET + 0x1820_0010) as *mut u32;
const AXI_STREAM_FIFO_TLR: *mut u32 = (KERNEL_OFFSET + 0x1820_0014) as *mut u32;
pub struct Router { pub struct Router {
buffer: Vec<Vec<u8>> buffer: Vec<Vec<u8>>,
} }
impl Router { impl Router {
fn transmit_available(&self) -> bool { fn transmit_available(&self) -> bool {
false true
} }
fn receive_available(&self) -> bool { fn receive_available(&self) -> bool {
false self.buffer.len() > 0
} }
} }
@ -56,10 +60,7 @@ impl<'a> phy::Device<'a> for RouterDriver {
let driver = self.0.lock(); let driver = self.0.lock();
if driver.transmit_available() && driver.receive_available() { if driver.transmit_available() && driver.receive_available() {
// potential racing // potential racing
Some(( Some((RouterRxToken(self.clone()), RouterTxToken(self.clone())))
RouterRxToken(self.clone()),
RouterTxToken(self.clone()),
))
} else { } else {
None None
} }
@ -87,7 +88,9 @@ impl phy::RxToken for RouterRxToken {
where where
F: FnOnce(&[u8]) -> Result<R>, F: FnOnce(&[u8]) -> Result<R>,
{ {
unimplemented!() let mut router = (self.0).0.lock();
let buffer = router.buffer.pop().unwrap();
f(&buffer)
} }
} }
@ -96,7 +99,18 @@ impl phy::TxToken for RouterTxToken {
where where
F: FnOnce(&mut [u8]) -> Result<R>, F: FnOnce(&mut [u8]) -> Result<R>,
{ {
unimplemented!() let mut buffer = vec![0; len];
let res = f(&mut buffer);
debug!("out buf {}", len);
unsafe {
AXI_STREAM_FIFO_TDR.write_volatile(2);
for byte in buffer {
AXI_STREAM_FIFO_TDFD.write_volatile(byte as u32);
}
AXI_STREAM_FIFO_TLR.write(len as u32);
}
res
} }
} }
@ -109,12 +123,10 @@ impl Driver for RouterInterface {
fn try_handle_interrupt(&self, _irq: Option<u32>) -> bool { fn try_handle_interrupt(&self, _irq: Option<u32>) -> bool {
let mut driver = self.driver.0.lock(); let mut driver = self.driver.0.lock();
let isr = unsafe { let isr = unsafe { AXI_STREAM_FIFO_ISR.read_volatile() };
AXI_STREAM_FIFO_ISR.read_volatile()
};
if isr > 0 { if isr > 0 {
info!("handle router interrupt {:b}", isr); debug!("handle router interrupt {:b}", isr);
unsafe { unsafe {
AXI_STREAM_FIFO_ISR.write(isr); AXI_STREAM_FIFO_ISR.write(isr);
let rdfo = AXI_STREAM_FIFO_RDFO.read_volatile(); let rdfo = AXI_STREAM_FIFO_RDFO.read_volatile();
@ -125,9 +137,21 @@ impl Driver for RouterInterface {
for i in 0..rdfo { for i in 0..rdfo {
buffer.push(AXI_STREAM_FIFO_RDFD.read_volatile() as u8); buffer.push(AXI_STREAM_FIFO_RDFD.read_volatile() as u8);
} }
info!("got packet of length {}", rdfo); debug!("got packet of length {}", rdfo);
driver.buffer.push(buffer); driver.buffer.push(buffer);
} }
drop(driver);
let timestamp = Instant::from_millis(crate::trap::uptime_msec() as i64);
let mut sockets = SOCKETS.lock();
match self.iface.lock().poll(&mut sockets, timestamp) {
Ok(_) => {
SOCKET_ACTIVITY.notify_all();
}
Err(err) => {
debug!("poll got err {}", err);
}
}
} }
return true; return true;
} }
@ -159,15 +183,15 @@ impl Driver for RouterInterface {
} }
} }
pub fn router_init( pub fn router_init() -> Arc<RouterInterface> {
) -> Arc<RouterInterface> {
let ethernet_addr = EthernetAddress::from_bytes(&[2, 2, 3, 3, 0, 0]); let ethernet_addr = EthernetAddress::from_bytes(&[2, 2, 3, 3, 0, 0]);
let net_driver = RouterDriver(Arc::new(Mutex::new(Router { let net_driver = RouterDriver(Arc::new(Mutex::new(Router { buffer: Vec::new() })));
buffer: Vec::new()
})));
let ip_addrs = [IpCidr::new(IpAddress::v4(10, 0, 0, 1), 24), IpCidr::new(IpAddress::v4(10, 0, 1, 1), 24)]; let ip_addrs = [
IpCidr::new(IpAddress::v4(10, 0, 0, 1), 24),
IpCidr::new(IpAddress::v4(10, 0, 1, 1), 24),
];
let neighbor_cache = NeighborCache::new(BTreeMap::new()); let neighbor_cache = NeighborCache::new(BTreeMap::new());
let routes = Routes::new(BTreeMap::new()); let routes = Routes::new(BTreeMap::new());
let iface = EthernetInterfaceBuilder::new(net_driver.clone()) let iface = EthernetInterfaceBuilder::new(net_driver.clone())
@ -181,7 +205,7 @@ pub fn router_init(
let router_iface = RouterInterface { let router_iface = RouterInterface {
iface: Mutex::new(iface), iface: Mutex::new(iface),
driver: net_driver driver: net_driver,
}; };
let driver = Arc::new(router_iface); let driver = Arc::new(router_iface);

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