Pass dtb to driver, remove rv code in io

Signed-off-by: Harry Chen <i@harrychen.xyz>

kernel/src/arch/mipsel/consts.rs

@@ -1,10 +1,6 @@
-// Physical address available on THINPAD:
+/// Platform specific constants
-// [0x80000000, 0x80800000]
 
-pub const KERNEL_OFFSET: usize = 0xC000_0000;
+pub const KERNEL_OFFSET: usize = 0x80100000;
-
-#[cfg(target_arch = "riscv32")]
-pub const KERNEL_P2_INDEX: usize = (KERNEL_OFFSET >> 12 >> 10) & 0x3ff;
 
 pub const KERNEL_HEAP_SIZE: usize = 0x00a0_0000;
 

kernel/src/arch/mipsel/io.rs

@@ -1,5 +1,4 @@
 use core::fmt::{Write, Result, Arguments};
-use super::sbi;
 
 struct SerialPort;
 
@@ -19,16 +18,12 @@ impl Write for SerialPort {
 }
 
 fn putchar(c: u8) {
-    if cfg!(feature = "board_u540") {
+    // TODO: output to uart
-        if c == b'\n' {
-            sbi::console_putchar(b'\r' as usize);
-        }
-    }
-    sbi::console_putchar(c as usize);
 }
 
 pub fn getchar() -> char {
-    let c = sbi::console_getchar() as u8;
+    // TODO: get char from uart
+    let c = 0 as u8;
 
     match c {
         255 => '\0',   // null
@@ -37,7 +32,8 @@ pub fn getchar() -> char {
 }
 
 pub fn getchar_option() -> Option<char> {
-    let c = sbi::console_getchar() as isize;
+    // TODO: get char from uart
+    let c = 0 as u8;
     match c {
         -1 => None,
         c => Some(c as u8 as char),

kernel/src/arch/mipsel/memory.rs

@@ -1,26 +1,18 @@
 use core::mem;
-use riscv::{addr::*, register::sstatus};
 use rcore_memory::PAGE_SIZE;
 use log::*;
 use crate::memory::{FRAME_ALLOCATOR, init_heap, MemoryAttr, MemorySet, Linear};
 use crate::consts::{MEMORY_OFFSET, MEMORY_END, KERNEL_OFFSET};
-use riscv::register::satp;
 
 /// Initialize the memory management module
-pub fn init(dtb: usize) {
+pub fn init() {
-    unsafe { sstatus::set_sum(); }  // Allow user memory access
     // initialize heap and Frame allocator
     init_frame_allocator();
     init_heap();
-    // remap the kernel use 4K page
-    remap_the_kernel(dtb);
 }
 
 pub fn init_other() {
-    unsafe {
+    // TODO: init other CPU cores
-        sstatus::set_sum();         // Allow user memory access
-        asm!("csrw satp, $0; sfence.vma" :: "r"(SATP) :: "volatile");
-    }
 }
 
 fn init_frame_allocator() {
@@ -42,26 +34,6 @@ fn init_frame_allocator() {
     }
 }
 
-/// Remap the kernel memory address with 4K page recorded in p1 page table
-fn remap_the_kernel(dtb: usize) {
-    let offset = -(KERNEL_OFFSET as isize - MEMORY_OFFSET as isize);
-    let mut ms = MemorySet::new_bare();
-    ms.push(stext as usize, etext as usize, MemoryAttr::default().execute().readonly(), Linear::new(offset), "text");
-    ms.push(sdata as usize, edata as usize, MemoryAttr::default(), Linear::new(offset), "data");
-    ms.push(srodata as usize, erodata as usize, MemoryAttr::default().readonly(), Linear::new(offset), "rodata");
-    ms.push(bootstack as usize, bootstacktop as usize, MemoryAttr::default(), Linear::new(offset), "stack");
-    ms.push(sbss as usize, ebss as usize, MemoryAttr::default(), Linear::new(offset), "bss");
-    ms.push(dtb, dtb + super::consts::MAX_DTB_SIZE, MemoryAttr::default().readonly(), Linear::new(offset), "dts");
-    // map PLIC for HiFiveU
-    let offset = -(KERNEL_OFFSET as isize);
-    ms.push(KERNEL_OFFSET + 0x0C00_2000, KERNEL_OFFSET + 0x0C00_2000 + PAGE_SIZE, MemoryAttr::default(), Linear::new(offset), "plic0");
-    ms.push(KERNEL_OFFSET + 0x0C20_2000, KERNEL_OFFSET + 0x0C20_2000 + PAGE_SIZE, MemoryAttr::default(), Linear::new(offset), "plic1");
-    unsafe { ms.activate(); }
-    unsafe { SATP = ms.token(); }
-    mem::forget(ms);
-    info!("remap kernel end");
-}
-
 // First core stores its SATP here.
 // Other cores load it later.
 static mut SATP: usize = 0;

kernel/src/arch/mipsel/mod.rs

@@ -42,10 +42,9 @@ pub extern fn rust_main() -> ! {
 
     crate::logging::init();
     interrupt::init();
-    memory::init(dtb);
+    memory::init();
     timer::init();
-    // TODO: initialize device with dtb
+    crate::drivers::init(dtb_start);
-    // crate::drivers::init(dtb);
     crate::process::init();
 
     // TODO: start other CPU

kernel/src/drivers/device_tree.rs

@@ -14,6 +14,7 @@ fn walk_dt_node(dt: &Node) {
         if compatible == "virtio,mmio" {
             virtio_probe(dt);
         }
+        // TODO: initial other devices (16650, etc.)
     }
     if let Ok(bootargs) = dt.prop_str("bootargs") {
         if bootargs.len() > 0 {

kernel/src/drivers/mod.rs

@@ -77,7 +77,7 @@ lazy_static! {
     pub static ref SOCKET_ACTIVITY: Condvar = Condvar::new();
 }
 
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
 pub fn init(dtb: usize) {
     device_tree::init(dtb);
 }

kernel/src/memory.rs

@@ -17,7 +17,7 @@ pub type MemorySet = rcore_memory::memory_set::MemorySet<InactivePageTable0>;
 pub type FrameAlloc = bit_allocator::BitAlloc16M;
 
 // RISCV has 8M memory
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
 pub type FrameAlloc = bit_allocator::BitAlloc4K;
 
 // Raspberry Pi 3 has 1G memory