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@ -5,35 +5,53 @@ use alloc::string::String;
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use alloc::sync::Arc;
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use alloc::vec::Vec;
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use bitflags::*;
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use smoltcp::iface::*;
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use smoltcp::phy::{self, DeviceCapabilities};
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use smoltcp::time::Instant;
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use smoltcp::wire::*;
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use smoltcp::Result;
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use rcore_memory::PAGE_SIZE;
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use crate::drivers::provider::Provider;
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use crate::net::SOCKETS;
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use crate::sync::SpinNoIrqLock as Mutex;
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use super::super::{DeviceType, Driver, DRIVERS, NET_DRIVERS, SOCKET_ACTIVITY};
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use crate::memory::phys_to_virt;
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const AXI_STREAM_FIFO_ISR: *mut u32 = phys_to_virt(0x1820_0000) as *mut u32;
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const AXI_STREAM_FIFO_IER: *mut u32 = phys_to_virt(0x1820_0004) as *mut u32;
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const AXI_STREAM_FIFO_TDFR: *mut u32 = phys_to_virt(0x1820_0008) as *mut u32;
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const AXI_STREAM_FIFO_TDFD: *mut u32 = phys_to_virt(0x1820_0010) as *mut u32;
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const AXI_STREAM_FIFO_TLR: *mut u32 = phys_to_virt(0x1820_0014) as *mut u32;
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const AXI_STREAM_FIFO_RDFR: *mut u32 = phys_to_virt(0x1820_0018) as *mut u32;
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const AXI_STREAM_FIFO_RDFO: *mut u32 = phys_to_virt(0x1820_001C) as *mut u32;
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const AXI_STREAM_FIFO_RDFD: *mut u32 = phys_to_virt(0x1820_0020) as *mut u32;
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const AXI_STREAM_FIFO_RLR: *mut u32 = phys_to_virt(0x1820_0024) as *mut u32;
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const AXI_STREAM_FIFO_TDR: *mut u32 = phys_to_virt(0x1820_002C) as *mut u32;
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const AXI_STREAM_FIFO_RDR: *mut u32 = phys_to_virt(0x1820_0030) as *mut u32;
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const AXI_STREAM_FIFO_ISR: *mut u32 = phys_to_virt(0x64A0_0000) as *mut u32;
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const AXI_STREAM_FIFO_IER: *mut u32 = phys_to_virt(0x64A0_0004) as *mut u32;
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const AXI_STREAM_FIFO_TDFR: *mut u32 = phys_to_virt(0x64A0_0008) as *mut u32;
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const AXI_STREAM_FIFO_TDFD: *mut u32 = phys_to_virt(0x64A0_0010) as *mut u32;
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const AXI_STREAM_FIFO_TLR: *mut u32 = phys_to_virt(0x64A0_0014) as *mut u32;
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const AXI_STREAM_FIFO_RDFR: *mut u32 = phys_to_virt(0x64A0_0018) as *mut u32;
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const AXI_STREAM_FIFO_RDFO: *mut u32 = phys_to_virt(0x64A0_001C) as *mut u32;
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const AXI_STREAM_FIFO_RDFD: *mut u32 = phys_to_virt(0x64A0_0020) as *mut u32;
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const AXI_STREAM_FIFO_RLR: *mut u32 = phys_to_virt(0x64A0_0024) as *mut u32;
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const AXI_STREAM_FIFO_TDR: *mut u32 = phys_to_virt(0x64A0_002C) as *mut u32;
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const AXI_STREAM_FIFO_RDR: *mut u32 = phys_to_virt(0x64A0_0030) as *mut u32;
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const ENABLED_PORTS: u8 = 2;
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bitflags! {
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struct AXIStreamFifoInterrupt : u32 {
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const RECV_EMPTY = 1 << 19;
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const RECV_FULL = 1 << 20;
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const TRAN_EMPTY = 1 << 21;
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const TRAN_FULL = 1 << 22;
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const RECV_RESET = 1 << 23;
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const TRAN_RESET = 1 << 24;
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const TRAN_SIZE_ERR = 1 << 25;
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const RECV_COMPLETE = 1 << 26;
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const TRAN_COMPLETE = 1 << 27;
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const TRAN_PACKET_OVERRUN_ERR = 1 << 28;
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const RECV_PACKET_UNDERRUN_ERR = 1 << 29;
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const RECV_PACKET_OVERRUN_READ_ERR = 1 << 30;
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const RECV_PACKET_UNDERRUN_READ_ERR = 1 << 31;
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}
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}
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pub struct Router {
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buffer: Vec<Vec<u8>>,
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buffer: [Vec<Vec<u8>>; ENABLED_PORTS as usize],
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}
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impl Router {
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@ -41,13 +59,13 @@ impl Router {
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true
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}
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fn receive_available(&self) -> bool {
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self.buffer.len() > 0
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fn receive_available(&self, port: u8) -> bool {
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self.buffer[port as usize].len() > 0
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}
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}
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#[derive(Clone)]
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pub struct RouterDriver(Arc<Mutex<Router>>);
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pub struct RouterDriver(Arc<Mutex<Router>>, u8);
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pub struct RouterRxToken(RouterDriver);
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pub struct RouterTxToken(RouterDriver);
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@ -58,7 +76,7 @@ impl<'a> phy::Device<'a> for RouterDriver {
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fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
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let driver = self.0.lock();
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if driver.transmit_available() && driver.receive_available() {
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if driver.transmit_available() && driver.receive_available(self.1) {
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// potential racing
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Some((RouterRxToken(self.clone()), RouterTxToken(self.clone())))
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} else {
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@ -89,7 +107,7 @@ impl phy::RxToken for RouterRxToken {
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F: FnOnce(&[u8]) -> Result<R>,
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{
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let mut router = (self.0).0.lock();
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let buffer = router.buffer.pop().unwrap();
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let buffer = router.buffer[(self.0).1 as usize].pop().unwrap();
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f(&buffer)
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}
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}
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@ -101,14 +119,20 @@ impl phy::TxToken for RouterTxToken {
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{
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let mut buffer = vec![0; len];
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let res = f(&mut buffer);
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debug!("out buf {}", len);
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debug!(
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"out buf {} data {:x?} port {}",
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len,
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&buffer[..20],
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(self.0).1
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);
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unsafe {
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AXI_STREAM_FIFO_TDR.write_volatile(2);
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AXI_STREAM_FIFO_TDFD.write_volatile((self.0).1 as u32);
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for byte in buffer {
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AXI_STREAM_FIFO_TDFD.write_volatile(byte as u32);
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}
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AXI_STREAM_FIFO_TLR.write((len * 4) as u32);
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AXI_STREAM_FIFO_TLR.write(((len + 1) * 4) as u32);
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}
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res
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}
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@ -126,7 +150,10 @@ impl Driver for RouterInterface {
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let isr = unsafe { AXI_STREAM_FIFO_ISR.read_volatile() };
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if isr > 0 {
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debug!("handle router interrupt {:b}", isr);
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debug!(
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"handle router interrupt {:?}",
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AXIStreamFifoInterrupt::from_bits_truncate(isr)
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);
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unsafe {
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AXI_STREAM_FIFO_ISR.write(isr);
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let rdfo = AXI_STREAM_FIFO_RDFO.read_volatile();
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@ -134,11 +161,17 @@ impl Driver for RouterInterface {
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let mut buffer = Vec::new();
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let rlr = AXI_STREAM_FIFO_RLR.read_volatile();
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let rdr = AXI_STREAM_FIFO_RDR.read_volatile();
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for i in 0..rdfo {
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let port = AXI_STREAM_FIFO_RDFD.read_volatile();
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for i in 1..rdfo {
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buffer.push(AXI_STREAM_FIFO_RDFD.read_volatile() as u8);
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}
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debug!("got packet of length {}", rdfo);
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driver.buffer.push(buffer);
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debug!(
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"got packet of length {} port {} data {:x?}",
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rdfo,
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port,
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&buffer[..20]
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);
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driver.buffer[port as usize].push(buffer);
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}
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drop(driver);
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@ -183,7 +216,7 @@ impl Driver for RouterInterface {
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}
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}
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pub fn router_init() -> Arc<RouterInterface> {
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pub fn router_init() {
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unsafe {
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// reset tx fifo
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AXI_STREAM_FIFO_TDFR.write_volatile(0xA5);
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@ -191,38 +224,40 @@ pub fn router_init() -> Arc<RouterInterface> {
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AXI_STREAM_FIFO_RDFR.write_volatile(0xA5);
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}
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let ethernet_addr = EthernetAddress::from_bytes(&[2, 2, 3, 3, 0, 0]);
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let net_driver = RouterDriver(Arc::new(Mutex::new(Router { buffer: Vec::new() })));
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let ip_addrs = [
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IpCidr::new(IpAddress::v4(10, 0, 0, 1), 24),
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IpCidr::new(IpAddress::v4(10, 0, 1, 1), 24),
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];
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let neighbor_cache = NeighborCache::new(BTreeMap::new());
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let routes = Routes::new(BTreeMap::new());
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let iface = EthernetInterfaceBuilder::new(net_driver.clone())
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.ethernet_addr(ethernet_addr)
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.ip_addrs(ip_addrs)
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.neighbor_cache(neighbor_cache)
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.routes(routes)
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.finalize();
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info!("router interface up");
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let router_iface = RouterInterface {
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iface: Mutex::new(iface),
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driver: net_driver,
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};
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let driver = Arc::new(router_iface);
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DRIVERS.write().push(driver.clone());
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NET_DRIVERS.write().push(driver.clone());
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for i in 0..ENABLED_PORTS {
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let ethernet_addr = EthernetAddress::from_bytes(&[2, 2, 3, 3, 0, i]);
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let net_driver = RouterDriver(
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Arc::new(Mutex::new(Router {
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buffer: [Vec::new(), Vec::new()],
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})),
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i,
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);
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let ip_addrs = [IpCidr::new(IpAddress::v4(10, 0, i, 1), 24)];
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let neighbor_cache = NeighborCache::new(BTreeMap::new());
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let routes = Routes::new(BTreeMap::new());
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let iface = EthernetInterfaceBuilder::new(net_driver.clone())
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.ethernet_addr(ethernet_addr)
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.ip_addrs(ip_addrs)
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.neighbor_cache(neighbor_cache)
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.routes(routes)
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.finalize();
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info!("router interface up #{}", i);
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let router_iface = RouterInterface {
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iface: Mutex::new(iface),
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driver: net_driver,
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};
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let driver = Arc::new(router_iface);
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DRIVERS.write().push(driver.clone());
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NET_DRIVERS.write().push(driver.clone());
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}
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// Enable Receive Complete Interrupt
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unsafe {
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AXI_STREAM_FIFO_IER.write_volatile(1 << 26);
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}
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driver
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}
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PanQL
6 years ago
committed by
GitHub