commit
3eddda4000
@ -1,6 +1,3 @@
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[submodule "riscv-pk"]
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path = riscv-pk
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url = https://github.com/rcore-os/riscv-pk.git
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[submodule "user"]
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[submodule "user"]
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path = user
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path = user
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url = https://github.com/rcore-os/rcore-user.git
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url = https://github.com/rcore-os/rcore-user.git
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@ -1,49 +0,0 @@
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/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore */
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/* Simple linker script for the ucore kernel.
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See the GNU ld 'info' manual ("info ld") to learn the syntax. */
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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BASE_ADDRESS = 0xffffffffc0020000;
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SECTIONS
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{
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/* Load the kernel at this address: "." means the current address */
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. = BASE_ADDRESS;
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start = .;
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.text : {
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stext = .;
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*(.text.entry)
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*(.text .text.*)
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. = ALIGN(4K);
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etext = .;
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}
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.rodata : {
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srodata = .;
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*(.rodata .rodata.*)
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. = ALIGN(4K);
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erodata = .;
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}
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.data : {
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sdata = .;
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*(.data .data.*)
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edata = .;
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}
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.stack : {
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*(.bss.stack)
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}
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.bss : {
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sbss = .;
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*(.bss .bss.*)
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ebss = .;
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}
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PROVIDE(end = .);
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}
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@ -0,0 +1,18 @@
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use super::consts::KERNEL_OFFSET;
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/// Mask all external interrupt except serial.
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pub unsafe fn init_external_interrupt() {
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// By default:
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// riscv-pk (bbl) enables all S-Mode IRQs (ref: machine/minit.c)
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// OpenSBI v0.3 disables all IRQs (ref: platform/common/irqchip/plic.c)
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const HART0_S_MODE_INTERRUPT_ENABLES: *mut u32 = (KERNEL_OFFSET + 0x0C00_2080) as *mut u32;
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const SERIAL: u32 = 0xa;
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HART0_S_MODE_INTERRUPT_ENABLES.write_volatile(1 << SERIAL);
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}
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pub unsafe fn enable_serial_interrupt() {
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const UART16550: *mut u8 = (KERNEL_OFFSET + 0x10000000) as *mut u8;
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UART16550.add(4).write_volatile(0x0B);
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UART16550.add(1).write_volatile(0x01);
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}
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@ -1,19 +0,0 @@
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.section .text.entry
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.globl _start
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_start:
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add t0, a0, 1
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slli t0, t0, 16
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lui sp, %hi(bootstack)
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addi sp, sp, %lo(bootstack)
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add sp, sp, t0
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call rust_main
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.section .bss.stack
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.align 12 #PGSHIFT
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.global bootstack
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bootstack:
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.space 4096 * 16 * 8
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.global bootstacktop
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bootstacktop:
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@ -0,0 +1,55 @@
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.section .text.entry
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.globl _start
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_start:
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# a0 == hartid
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# pc == 0x80200000
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# sp == 0x800xxxxx
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# 1. set sp
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# sp = bootstack + (hartid + 1) * 0x10000
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add t0, a0, 1
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slli t0, t0, 16
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lui sp, %hi(bootstack)
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add sp, sp, t0
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# 2. enable paging
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# satp = (1 << 31) | PPN(boot_page_table_sv32)
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lui t0, %hi(boot_page_table_sv32)
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li t1, 0xc0000000 - 0x80000000
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sub t0, t0, t1
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srli t0, t0, 12
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li t1, 1 << 31
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or t0, t0, t1
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csrw satp, t0
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sfence.vma
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# 3. jump to rust_main (absolute address)
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lui t0, %hi(rust_main)
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addi t0, t0, %lo(rust_main)
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jr t0
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.section .bss.stack
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.align 12 # page align
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.global bootstack
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bootstack:
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.space 4096 * 16 * 8
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.global bootstacktop
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bootstacktop:
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.section .data
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.align 12 # page align
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boot_page_table_sv32:
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# NOTE: assume kernel image < 16M
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# 0x80000000 -> 0x80000000 (4M * 4)
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# 0xc0000000 -> 0x80000000 (4M * 4)
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.zero 4 * 512
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.word (0x80000 << 10) | 0xcf # VRWXAD
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.word (0x80400 << 10) | 0xcf # VRWXAD
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.word (0x80800 << 10) | 0xcf # VRWXAD
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.word (0x80c00 << 10) | 0xcf # VRWXAD
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.zero 4 * 252
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.word (0x80000 << 10) | 0xcf # VRWXAD
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.word (0x80400 << 10) | 0xcf # VRWXAD
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.word (0x80800 << 10) | 0xcf # VRWXAD
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.word (0x80c00 << 10) | 0xcf # VRWXAD
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.zero 4 * 252
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@ -0,0 +1,48 @@
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.section .text.entry
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.globl _start
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_start:
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# a0 == hartid
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# pc == 0x80200000
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# sp == 0x800xxxxx
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# 1. set sp
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# sp = bootstack + (hartid + 1) * 0x10000
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add t0, a0, 1
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slli t0, t0, 16
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lui sp, %hi(bootstack)
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add sp, sp, t0
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# 2. enable paging
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# satp = (8 << 60) | PPN(boot_page_table_sv39)
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lui t0, %hi(boot_page_table_sv39)
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li t1, 0xffffffffc0000000 - 0x80000000
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sub t0, t0, t1
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srli t0, t0, 12
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li t1, 8 << 60
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or t0, t0, t1
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csrw satp, t0
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sfence.vma
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# 3. jump to rust_main (absolute address)
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lui t0, %hi(rust_main)
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addi t0, t0, %lo(rust_main)
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jr t0
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.section .bss.stack
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.align 12 # page align
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.global bootstack
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bootstack:
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.space 4096 * 16 * 8
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.global bootstacktop
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bootstacktop:
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.section .data
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.align 12 # page align
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boot_page_table_sv39:
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# 0x00000000_80000000 -> 0x80000000 (1G)
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# 0xffffffff_c0000000 -> 0x80000000 (1G)
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.quad 0
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.quad 0
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.quad (0x80000 << 10) | 0xcf # VRWXAD
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.zero 8 * 508
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.quad (0x80000 << 10) | 0xcf # VRWXAD
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@ -1 +0,0 @@
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Subproject commit 405ea59dd7dd2762c5883822f21d9995bea32b0c
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|
@ -0,0 +1,9 @@
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|
# OpenSBI
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These are binary release of OpenSBI on this [commit](https://github.com/riscv/opensbi/tree/194dbbe5a13dff2255411c26d249f3ad4ef42c0b) at 2019.04.15.
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- fu540.elf: opensbi-0.3-rv64-bin/platform/sifive/fu540/firmware/fw_jump.elf
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- virt_rv32.elf: opensbi-0.3-rv32-bin/platform/qemu/virt/firmware/fw_jump.elf
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- virt_rv64.elf: opensbi-0.3-rv64-bin/platform/qemu/virt/firmware/fw_jump.elf
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NOTE: The [official v0.3 release](https://github.com/riscv/opensbi/releases/tag/v0.3) has bug on serial interrupt.
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Reference in new issue