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@ -1,52 +1,53 @@
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use mips::registers;
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use mips::registers::cp0;
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use crate::arch::paging::root_page_table_ptr;
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/// Saved registers on a trap.
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#[derive(Clone)]
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#[repr(C)]
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pub struct TrapFrame {
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/// CP0 status register
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pub status: u32,
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pub status: cp0::status::Status,
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/// CP0 cause register
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pub cause: u32,
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pub cause: cp0::cause::Cause,
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/// CP0 EPC register
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pub epc: u32,
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pub epc: usize,
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/// CP0 vaddr register
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pub vaddr: u32,
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pub vaddr: usize,
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/// HI/LO registers
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pub hi: u32,
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pub lo: u32,
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pub hi: usize,
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pub lo: usize,
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/// General registers
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pub at: u32,
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pub v0: u32,
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pub v1: u32,
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pub a0: u32,
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pub a1: u32,
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pub a2: u32,
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pub a3: u32,
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pub t0: u32,
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pub t1: u32,
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pub t2: u32,
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pub t3: u32,
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pub t4: u32,
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pub t5: u32,
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pub t6: u32,
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pub t7: u32,
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pub s0: u32,
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pub s1: u32,
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pub s2: u32,
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pub s3: u32,
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pub s4: u32,
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pub s5: u32,
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pub s6: u32,
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pub s7: u32,
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pub t8: u32,
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pub t9: u32,
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pub k0: u32,
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pub k1: u32,
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pub gp: u32,
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pub sp: u32,
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pub fp: u32,
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pub ra: u32,
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pub at: usize,
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pub v0: usize,
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pub v1: usize,
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pub a0: usize,
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pub a1: usize,
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pub a2: usize,
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pub a3: usize,
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pub t0: usize,
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pub t1: usize,
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pub t2: usize,
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pub t3: usize,
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pub t4: usize,
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pub t5: usize,
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pub t6: usize,
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pub t7: usize,
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pub s0: usize,
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pub s1: usize,
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pub s2: usize,
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pub s3: usize,
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pub s4: usize,
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pub s5: usize,
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pub s6: usize,
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pub s7: usize,
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pub t8: usize,
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pub t9: usize,
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pub k0: usize,
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pub k1: usize,
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pub gp: usize,
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pub sp: usize,
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pub fp: usize,
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pub ra: usize,
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/// Reserve space for hartid
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pub _hartid: usize,
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}
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@ -59,13 +60,13 @@ impl TrapFrame {
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fn new_kernel_thread(entry: extern fn(usize) -> !, arg: usize, sp: usize) -> Self {
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use core::mem::zeroed;
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let mut tf: Self = unsafe { zeroed() };
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tf.x[10] = arg; // a0
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tf.x[2] = sp;
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tf.sepc = entry as usize;
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tf.sstatus = sstatus::read();
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tf.sstatus.set_spie(true);
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tf.sstatus.set_sie(false);
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tf.sstatus.set_spp(sstatus::SPP::Supervisor);
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tf.a0 = arg;
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tf.sp = sp;
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tf.epc = entry as usize;
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tf.status = cp0::status::read();
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tf.status.set_kernel_mode();
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tf.status.set_ie();
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tf.status.set_exl();
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tf
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}
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@ -76,12 +77,12 @@ impl TrapFrame {
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fn new_user_thread(entry_addr: usize, sp: usize) -> Self {
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use core::mem::zeroed;
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let mut tf: Self = unsafe { zeroed() };
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tf.x[2] = sp;
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tf.sepc = entry_addr;
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tf.sstatus = sstatus::read();
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tf.sstatus.set_spie(true);
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tf.sstatus.set_sie(false);
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tf.sstatus.set_spp(sstatus::SPP::User);
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tf.sp = sp;
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tf.epc = entry_addr;
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tf.status = cp0::status::read();
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tf.status.set_user_mode();
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tf.status.set_ie();
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tf.status.set_exl();
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tf
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}
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}
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@ -89,23 +90,11 @@ impl TrapFrame {
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use core::fmt::{Debug, Formatter, Error};
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impl Debug for TrapFrame {
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fn fmt(&self, f: &mut Formatter) -> Result<(), Error> {
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struct Regs<'a>(&'a [usize; 32]);
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impl<'a> Debug for Regs<'a> {
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fn fmt(&self, f: &mut Formatter) -> Result<(), Error> {
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const REG_NAME: [&str; 32] = [
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"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
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"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6"];
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f.debug_map().entries(REG_NAME.iter().zip(self.0)).finish()
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}
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}
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f.debug_struct("TrapFrame")
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.field("regs", &Regs(&self.x))
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.field("sstatus", &self.sstatus)
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.field("sepc", &self.sepc)
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.field("stval", &self.stval)
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.field("scause", &self.scause.cause())
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.field("status", &self.status.bits)
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.field("epc", &self.epc.bits)
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.field("cause", &self.cause.bits)
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.field("vaddr", &self.vaddr.bits)
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.finish()
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}
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}
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@ -167,7 +156,6 @@ impl Context {
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#[naked]
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#[inline(never)]
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pub unsafe extern fn switch(&mut self, _target: &mut Self) {
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#[cfg(target_arch = "riscv32")]
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asm!(r"
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.equ XLENB, 4
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.macro Load reg, mem
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@ -176,15 +164,6 @@ impl Context {
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.macro Store reg, mem
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sw \reg, \mem
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.endm");
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#[cfg(target_arch = "riscv64")]
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asm!(r"
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.equ XLENB, 8
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.macro Load reg, mem
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ld \reg, \mem
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.endm
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.macro Store reg, mem
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sd \reg, \mem
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.endm");
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asm!("
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// save from's registers
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addi sp, sp, (-XLENB*14)
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@ -199,16 +178,16 @@ impl Context {
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Store s6, 8*XLENB(sp)
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Store s7, 9*XLENB(sp)
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Store s8, 10*XLENB(sp)
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Store s9, 11*XLENB(sp)
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Store s10, 12*XLENB(sp)
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Store s11, 13*XLENB(sp)
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csrr s11, satp
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Store s11, 1*XLENB(sp)
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Store gp, 11*XLENB(sp)
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Store ra, 12*XLENB(sp)
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Store sp, 13*XLENB(sp)
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Store $1, 1*XLENB(sp)
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// restore to's registers
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Load sp, 0(a1)
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Load s11, 1*XLENB(sp)
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csrw satp, s11
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Load $0, 1*XLENB(sp)
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Load ra, 0*XLENB(sp)
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Load s0, 2*XLENB(sp)
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Load s1, 3*XLENB(sp)
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@ -219,14 +198,15 @@ impl Context {
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Load s6, 8*XLENB(sp)
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Load s7, 9*XLENB(sp)
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Load s8, 10*XLENB(sp)
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Load s9, 11*XLENB(sp)
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Load s10, 12*XLENB(sp)
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Load s11, 13*XLENB(sp)
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Load gp, 11*XLENB(sp)
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Load ra, 12*XLENB(sp)
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Load sp, 13*XLENB(sp)
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addi sp, sp, (XLENB*14)
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Store zero, 0(a1)
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ret"
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: : : : "volatile" )
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jr ra
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nop"
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:"=r"(root_page_table_ptr) :"r"(root_page_table_ptr) : : "volatile" )
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}
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/// Constructs a null Context for the current running thread.
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@ -269,7 +249,7 @@ impl Context {
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tf: {
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let mut tf = tf.clone();
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// fork function's ret value, the new process is 0
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tf.x[10] = 0; // a0
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tf.a0 = 0;
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tf
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},
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}.push_at(kstack_top)
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@ -287,9 +267,9 @@ impl Context {
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context: ContextData::new(satp),
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tf: {
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let mut tf = tf.clone();
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tf.x[2] = ustack_top; // sp
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tf.x[4] = tls; // tp
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tf.x[10] = 0; // a0
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tf.sp = ustack_top; // sp
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tf.v1 = tls; // tp
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tf.a0 = 0; // a0
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tf
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},
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}.push_at(kstack_top)
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