Setup a simple page table, enable paging.

crate/riscv

@@ -1 +1 @@
-Subproject commit 4bf5f1b732b8977d445f668df0b3f11c0d19d9a5
+Subproject commit 1022571b07f946add5187f2933f0dabe5819309b

src/arch/riscv32/mod.rs

@@ -4,10 +4,25 @@ extern crate bbl;
 pub mod serial;
 pub mod interrupt;
 pub mod timer;
+pub mod paging;
 
 pub fn init() {
     println!("Hello RISCV! {}", 123);
     interrupt::init();
-    timer::init();
+//    timer::init();
+    println!("satp: {:x?}", riscv::register::satp::read());
+
+    use xmas_elf::ElfFile;
+    use core::slice;
+    use self::riscv::addr::*;
+    let begin = 0x80400000usize;
+    extern { fn end(); }
+    let end = end as usize;
+    println!("Kernel: {:#x} {:#x}", begin, end);
+//    let kernel = unsafe{ slice::from_raw_parts(begin as *const u8, end - begin) };
+//    let elf = ElfFile::new(kernel).unwrap();
+
+    paging::setup_page_table(Frame::of_addr(PhysAddr::new(end as u32 + 4096)));
+
     loop {}
 }

src/arch/riscv32/paging.rs

@@ -0,0 +1,20 @@
+pub use super::riscv::paging::*;
+pub use super::riscv::addr::*;
+
+// need 1 page
+pub fn setup_page_table(frame: Frame) {
+    let p2 = unsafe { &mut *(frame.start_address().as_u32() as *mut PageTable) };
+    p2.zero();
+
+    use self::PageTableFlags as F;
+    use consts::{KERNEL_PML4, RECURSIVE_PAGE_PML4};
+    // Set recursive map
+    p2[RECURSIVE_PAGE_PML4].set(frame.clone(), F::VALID);
+    // Set kernel identity map
+    p2[KERNEL_PML4].set(Frame::of_addr(PhysAddr::new((KERNEL_PML4 as u32) << 22)), F::VALID | F::READABLE | F::WRITABLE | F::EXCUTABLE);
+    p2[KERNEL_PML4 + 1].set(Frame::of_addr(PhysAddr::new((KERNEL_PML4 as u32 + 1) << 22)), F::VALID | F::READABLE | F::WRITABLE | F::EXCUTABLE);
+
+    use super::riscv::register::satp;
+    unsafe { satp::set(satp::Mode::Sv32, 0, frame); }
+    println!("New page table");
+}

src/consts.rs

@@ -2,6 +2,27 @@
 pub const MAX_CPU_NUM: usize = 8;
 pub const MAX_PROCESS_NUM: usize = 32;
 
+#[cfg(target_arch = "riscv")]
+pub use self::riscv::*;
+
+#[cfg(target_arch = "x86_64")]
+pub use self::x86_64::*;
+
+#[cfg(target_arch = "riscv")]
+mod riscv {
+    // Physical address available on THINPAD:
+    // [0x80000000, 0x80800000]
+    const P2_SIZE: usize = 1 << 22;
+    const P2_MASK: usize = 0x3ff << 22;
+    pub const RECURSIVE_PAGE_PML4: usize = 0x3ff;
+    pub const KERNEL_OFFSET: usize = 0;
+    pub const KERNEL_PML4: usize = 0x8040_0000 >> 22;
+    pub const KERNEL_HEAP_OFFSET: usize = 0x8000_0000;
+    pub const KERNEL_HEAP_SIZE: usize = 8 * 1024 * 1024; // 8 MB
+}
+
+#[cfg(target_arch = "x86_64")]
+mod x86_64 {
     // Copy from Redox consts.rs:
 
     // Because the memory map is so important to not be aliased, it is defined here, in one place
@@ -96,3 +117,4 @@ pub const MAX_PROCESS_NUM: usize = 32;
     /// Offset for usage in other temporary pages
     pub const USER_TMP_MISC_OFFSET: usize = USER_TMP_TLS_OFFSET + PML4_SIZE;
     pub const USER_TMP_MISC_PML4: usize = (USER_TMP_MISC_OFFSET & PML4_MASK) / PML4_SIZE;
+}