use core::sync::atomic::fence

master
WangRunji 6 years ago
parent 66c84b4599
commit 847a1c7576

@ -6,7 +6,3 @@ pub fn id() -> usize {
// TODO: cpu id // TODO: cpu id
0 0
} }
pub fn fence() {
unsafe { asm!("dmb ish" ::: "memory"); }
}

@ -35,7 +35,3 @@ pub unsafe fn start_others(hart_mask: usize) {
pub fn halt() { pub fn halt() {
unsafe { riscv::asm::wfi() } unsafe { riscv::asm::wfi() }
} }
pub fn fence() {
unsafe { asm!("fence" ::: "memory"); }
}

@ -30,7 +30,3 @@ pub fn halt() {
use x86_64::instructions::hlt; use x86_64::instructions::hlt;
hlt(); hlt();
} }
pub fn fence() {
unsafe { asm!("mfence" ::: "memory"); }
}

@ -4,6 +4,7 @@ use alloc::prelude::*;
use alloc::sync::Arc; use alloc::sync::Arc;
use core::mem::size_of; use core::mem::size_of;
use core::slice; use core::slice;
use core::sync::atomic::{fence, Ordering};
use bitflags::*; use bitflags::*;
use device_tree::Node; use device_tree::Node;
@ -215,7 +216,7 @@ impl phy::TxToken for VirtIONetTxToken {
desc.len.write((len + size_of::<VirtIONetHeader>()) as u32); desc.len.write((len + size_of::<VirtIONetHeader>()) as u32);
// memory barrier // memory barrier
crate::arch::cpu::fence(); fence(Ordering::SeqCst);
// add desc to available ring // add desc to available ring
ring.idx.write(ring.idx.read() + 1); ring.idx.write(ring.idx.read() + 1);
@ -376,7 +377,7 @@ pub fn virtio_net_init(node: &Node) {
desc.flags.write(0); desc.flags.write(0);
} }
// memory barrier // memory barrier
crate::arch::cpu::fence(); fence(Ordering::SeqCst);
if queue == VIRTIO_QUEUE_RECEIVE { if queue == VIRTIO_QUEUE_RECEIVE {

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