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@ -14,8 +14,40 @@ const VBE_DISPI_INDEX_ENABLE: u16 = 0x04;
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const VGA_AR_PAS: u8 = 0x20;
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const VBE_DISPI_ENABLED: u16 = 0x01;
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pub fn init(vga_base: usize, x_res: u16, y_res: u16) {
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const PCIR_COMMAND: u8 = 0x04;
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const PCIM_CMD_PORTEN: u16 = 0x0001;
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const PCIM_CMD_MEMEN: u16 = 0x0002;
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fn pci_read_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8) -> u16 {
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// enable access mechanism
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let data = 0xF0 | (func << 1);
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write(pci_base + 0xcf8, data);
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write(pci_base + 0xcfa, bus);
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// calculate port address
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let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
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// do the actual work
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read(pci_base + addr as usize)
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}
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fn pci_write_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8, value: u16) {
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// enable access mechanism
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let data = 0xF0 | (func << 1);
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write(pci_base + 0xcf8, data);
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write(pci_base + 0xcfa, bus);
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// calculate port address
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let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
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// do the actual work
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write(pci_base + addr as usize, value);
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}
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pub fn init(pci_base: usize, vga_base: usize, x_res: u16, y_res: u16) {
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// enable PCI MMIO
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let pci_state = pci_read_config(pci_base, 0x00, 0x12, 0x00, PCIR_COMMAND);
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pci_write_config(pci_base, 0x00, 0x12, 0x00, PCIR_COMMAND, pci_state | PCIM_CMD_PORTEN | PCIM_CMD_MEMEN);
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// vga operations
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let vga_write_io = |offset: u16, value: u8| {
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write(vga_base + VGA_MMIO_OFFSET + (offset as usize), value);
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};
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@ -38,4 +70,6 @@ pub fn init(vga_base: usize, x_res: u16, y_res: u16) {
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let vbe_enable = vga_read_vbe(VBE_DISPI_INDEX_ENABLE) | VBE_DISPI_ENABLED;
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vga_write_vbe(VBE_DISPI_INDEX_ENABLE, vbe_enable);
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}
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println!("QEMU STDVGA driver initialized @ {:x}", vga_base);
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}
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