|
|
@ -14,8 +14,40 @@ const VBE_DISPI_INDEX_ENABLE: u16 = 0x04;
|
|
|
|
const VGA_AR_PAS: u8 = 0x20;
|
|
|
|
const VGA_AR_PAS: u8 = 0x20;
|
|
|
|
const VBE_DISPI_ENABLED: u16 = 0x01;
|
|
|
|
const VBE_DISPI_ENABLED: u16 = 0x01;
|
|
|
|
|
|
|
|
|
|
|
|
pub fn init(vga_base: usize, x_res: u16, y_res: u16) {
|
|
|
|
const PCIR_COMMAND: u8 = 0x04;
|
|
|
|
|
|
|
|
const PCIM_CMD_PORTEN: u16 = 0x0001;
|
|
|
|
|
|
|
|
const PCIM_CMD_MEMEN: u16 = 0x0002;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fn pci_read_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8) -> u16 {
|
|
|
|
|
|
|
|
// enable access mechanism
|
|
|
|
|
|
|
|
let data = 0xF0 | (func << 1);
|
|
|
|
|
|
|
|
write(pci_base + 0xcf8, data);
|
|
|
|
|
|
|
|
write(pci_base + 0xcfa, bus);
|
|
|
|
|
|
|
|
// calculate port address
|
|
|
|
|
|
|
|
let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
|
|
|
|
|
|
|
|
// do the actual work
|
|
|
|
|
|
|
|
read(pci_base + addr as usize)
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fn pci_write_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8, value: u16) {
|
|
|
|
|
|
|
|
// enable access mechanism
|
|
|
|
|
|
|
|
let data = 0xF0 | (func << 1);
|
|
|
|
|
|
|
|
write(pci_base + 0xcf8, data);
|
|
|
|
|
|
|
|
write(pci_base + 0xcfa, bus);
|
|
|
|
|
|
|
|
// calculate port address
|
|
|
|
|
|
|
|
let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
|
|
|
|
|
|
|
|
// do the actual work
|
|
|
|
|
|
|
|
write(pci_base + addr as usize, value);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
pub fn init(pci_base: usize, vga_base: usize, x_res: u16, y_res: u16) {
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// enable PCI MMIO
|
|
|
|
|
|
|
|
let pci_state = pci_read_config(pci_base, 0x00, 0x12, 0x00, PCIR_COMMAND);
|
|
|
|
|
|
|
|
pci_write_config(pci_base, 0x00, 0x12, 0x00, PCIR_COMMAND, pci_state | PCIM_CMD_PORTEN | PCIM_CMD_MEMEN);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// vga operations
|
|
|
|
let vga_write_io = |offset: u16, value: u8| {
|
|
|
|
let vga_write_io = |offset: u16, value: u8| {
|
|
|
|
write(vga_base + VGA_MMIO_OFFSET + (offset as usize), value);
|
|
|
|
write(vga_base + VGA_MMIO_OFFSET + (offset as usize), value);
|
|
|
|
};
|
|
|
|
};
|
|
|
@ -38,4 +70,6 @@ pub fn init(vga_base: usize, x_res: u16, y_res: u16) {
|
|
|
|
let vbe_enable = vga_read_vbe(VBE_DISPI_INDEX_ENABLE) | VBE_DISPI_ENABLED;
|
|
|
|
let vbe_enable = vga_read_vbe(VBE_DISPI_INDEX_ENABLE) | VBE_DISPI_ENABLED;
|
|
|
|
vga_write_vbe(VBE_DISPI_INDEX_ENABLE, vbe_enable);
|
|
|
|
vga_write_vbe(VBE_DISPI_INDEX_ENABLE, vbe_enable);
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
println!("QEMU STDVGA driver initialized @ {:x}", vga_base);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|