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@ -1,6 +1,6 @@
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//! Page table implementations for aarch64.
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use bit_allocator::{BitAlloc};
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// Depends on kernel
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use consts::{KERNEL_PML4, RECURSIVE_INDEX};
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use memory::{active_table, alloc_frame, alloc_stack, dealloc_frame};
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use ucore_memory::memory_set::*;
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use ucore_memory::PAGE_SIZE;
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@ -11,29 +11,121 @@ use aarch64::paging::{Mapper, PageTable as Aarch64PageTable, PageTableEntry, Pag
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use aarch64::paging::{FrameAllocator, FrameDeallocator, Page, PageRange, PhysFrame as Frame, Size4KiB};
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use aarch64::{regs::*};
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// need 1 page
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pub fn setup_page_table(frame: Frame) {
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let p4 = unsafe { &mut *(frame.start_address().as_u64() as *mut Aarch64PageTable) };
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p4.zero();
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// p4.set_recursive(RECURSIVE_PAGE_PML4, frame.clone());
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// Set kernel identity map
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// 0x10000000 ~ 1K area
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p4.map_identity(0o777, EF::PRESENT | EF::PXN | EF::UXN);
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// 0x80000000 ~ 8K area
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p4.map_identity(0, EF::PRESENT);
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// p2.map_identity(KERNEL_PML4, EF::PRESENT | EF::READABLE | EF::WRITABLE);
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// p2.map_identity(KERNEL_PML4 + 1, EF::VALID | EF::READABLE | EF::WRITABLE | EF::EXECUTABLE);
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// use super::riscv::register::satp;
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// unsafe { satp::set(satp::Mode::Sv32, 0, frame); }
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// sfence_vma_all();
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register_bitfields! {u64,
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// AArch64 Reference Manual page 2150
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STAGE1_DESCRIPTOR [
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/// Execute-never
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XN OFFSET(54) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Various address fields, depending on use case
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LVL4_OUTPUT_ADDR_4KiB OFFSET(39) NUMBITS(9) [], // [47:39]
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LVL3_OUTPUT_ADDR_4KiB OFFSET(30) NUMBITS(18) [], // [47:30]
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LVL2_OUTPUT_ADDR_4KiB OFFSET(21) NUMBITS(27) [], // [47:21]
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NEXT_LVL_TABLE_ADDR_4KiB OFFSET(12) NUMBITS(36) [], // [47:12]
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/// Access flag
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AF OFFSET(10) NUMBITS(1) [
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False = 0,
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True = 1
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],
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/// Shareability field
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SH OFFSET(8) NUMBITS(2) [
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OuterShareable = 0b10,
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InnerShareable = 0b11
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],
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/// Access Permissions
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AP OFFSET(6) NUMBITS(2) [
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RW_EL1 = 0b00,
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RW_EL1_EL0 = 0b01,
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RO_EL1 = 0b10,
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RO_EL1_EL0 = 0b11
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],
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/// Memory attributes index into the MAIR_EL1 register
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AttrIndx OFFSET(2) NUMBITS(3) [],
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TYPE OFFSET(1) NUMBITS(1) [
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Block = 0,
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Table = 1
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],
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VALID OFFSET(0) NUMBITS(1) [
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False = 0,
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True = 1
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]
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]
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}
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ttbr0_el1_write(frame);
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// need 3 page
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pub fn setup_page_table(frame_lvl4: Frame, frame_lvl3: Frame, frame_lvl2: Frame) {
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let p4 = unsafe { &mut *(frame_lvl4.start_address().as_u64() as *mut Aarch64PageTable) };
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let p3 = unsafe { &mut *(frame_lvl3.start_address().as_u64() as *mut Aarch64PageTable) };
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let p2 = unsafe { &mut *(frame_lvl2.start_address().as_u64() as *mut Aarch64PageTable) };
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p4.zero();
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p3.zero();
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p2.zero();
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mod mair {
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pub const NORMAL: u64 = 0;
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pub const DEVICE: u64 = 1;
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}
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// Fill the rest of the LVL2 (2MiB) entries as block
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// descriptors. Differentiate between normal and device mem.
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const MMIO_BASE: u64 = 0x3F000000;
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let mmio_base: u64 = MMIO_BASE >> 21;
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let mut common = STAGE1_DESCRIPTOR::VALID::True
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+ STAGE1_DESCRIPTOR::TYPE::Block
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+ STAGE1_DESCRIPTOR::AP::RW_EL1
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+ STAGE1_DESCRIPTOR::AF::True;
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// + STAGE1_DESCRIPTOR::XN::True;
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for i in 0..512 {
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let j: u64 = i as u64;
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let mem_attr = if j >= mmio_base {
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STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE)
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} else {
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STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
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};
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p2[i].entry = (common + mem_attr + STAGE1_DESCRIPTOR::LVL2_OUTPUT_ADDR_4KiB.val(j)).value;
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}
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common = common + STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL);
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p3[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl2.start_address().as_u64() >> 12)).value;
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p3[1].entry = (common + STAGE1_DESCRIPTOR::LVL3_OUTPUT_ADDR_4KiB.val(1)).value;
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p4[0].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl3.start_address().as_u64() >> 12)).value;
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p4[RECURSIVE_INDEX].entry = (common + STAGE1_DESCRIPTOR::TYPE::Table + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(frame_lvl4.start_address().as_u64() >> 12)).value;
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// warn!("p2");
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// for i in 0..512 {
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// if p2[i].flags().bits() != 0 {
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// info!("{:x?} {:x?} {:x?}",i, &p2[i] as *const _ as usize, p2[i]);
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// }
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// }
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// warn!("p3");
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// for i in 0..512 {
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// if p3[i].flags().bits() != 0 {
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// info!("{:x?} {:x?} {:x?}",i, &p3[i] as *const _ as usize, p3[i]);
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// }
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// }
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// warn!("p4");
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// for i in 0..512 {
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// if p4[i].flags().bits() != 0 {
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// info!("{:x?} {:x?} {:x?}",i, &p4[i] as *const _ as usize, p4[i]);
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// }
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// }
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ttbr0_el1_write(frame_lvl4);
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tlb_invalidate();
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info!("setup init page table end");
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}
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@ -69,7 +161,7 @@ impl PageTable for ActivePageTable {
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type Entry = PageEntry;
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fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry {
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let flags = EF::PRESENT | EF::WRITE | EF::UXN;
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let flags = EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::UXN | EF::PAGE_BIT;
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self.0.map_to(Page::of_addr(addr), Frame::of_addr(target), flags, &mut FrameAllocatorForAarch64)
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.unwrap().flush();
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self.get_entry(addr)
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@ -81,7 +173,7 @@ impl PageTable for ActivePageTable {
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}
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fn get_entry(&mut self, addr: usize) -> &mut PageEntry {
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let entry_addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000;
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let entry_addr = ((addr >> 9) & 0o777_777_777_7770) | (RECURSIVE_INDEX << 39);
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unsafe { &mut *(entry_addr as *mut PageEntry) }
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}
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@ -99,9 +191,12 @@ impl PageTable for ActivePageTable {
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}
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}
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const ROOT_PAGE_TABLE: *mut Aarch64PageTable =
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((RECURSIVE_INDEX << 39) | (RECURSIVE_INDEX << 30) | (RECURSIVE_INDEX << 21) | (RECURSIVE_INDEX << 12)) as *mut Aarch64PageTable;
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impl ActivePageTable {
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pub unsafe fn new() -> Self {
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ActivePageTable(RecursivePageTable::new(&mut *(0xffff_ffff_ffff_f000 as *mut _)).unwrap())
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ActivePageTable(RecursivePageTable::new(&mut *(ROOT_PAGE_TABLE as *mut _)).unwrap())
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}
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fn with_temporary_map(&mut self, frame: &Frame, f: impl FnOnce(&mut ActivePageTable, &mut Aarch64PageTable)) {
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// Create a temporary page
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@ -161,7 +256,7 @@ impl Entry for PageEntry {
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let mut addr = self as *const _ as usize;
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for _ in 0..3 {
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// Upper level entry
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addr = ((addr >> 9) & 0o777_777_777_7770) | 0xffffff80_00000000;
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addr = ((addr >> 9) & 0o777_777_777_7770) | (RECURSIVE_INDEX << 39);
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// set USER_ACCESSIBLE
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unsafe { (*(addr as *mut EF)).insert(EF::USER_ACCESSIBLE) };
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}
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@ -200,24 +295,24 @@ impl InactivePageTable for InactivePageTable0 {
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active_table().with_temporary_map(&frame, |_, table: &mut Aarch64PageTable| {
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table.zero();
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// set up recursive mapping for the table
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table[511].set_frame(frame.clone(), EF::PRESENT | EF::WRITE);
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table[RECURSIVE_INDEX].set_frame(frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT);
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});
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InactivePageTable0 { p4_frame: frame }
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}
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fn edit(&mut self, f: impl FnOnce(&mut Self::Active)) {
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active_table().with_temporary_map(&ttbr0_el1_read().0, |active_table, p4_table: &mut Aarch64PageTable| {
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let backup = p4_table[0o777].clone();
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let backup = p4_table[RECURSIVE_INDEX].clone();
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// overwrite recursive mapping
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p4_table[0o777].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE);
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p4_table[RECURSIVE_INDEX].set_frame(self.p4_frame.clone(), EF::PRESENT | EF::WRITE | EF::ACCESSED | EF::PAGE_BIT);
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tlb_invalidate();
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// execute f in the new context
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f(active_table);
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// restore recursive mapping to original p4 table
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p4_table[0o777] = backup;
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p4_table[RECURSIVE_INDEX] = backup;
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tlb_invalidate();
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});
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}
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@ -228,6 +323,7 @@ impl InactivePageTable for InactivePageTable0 {
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debug!("switch table {:?} -> {:?}", old_frame, new_frame);
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if old_frame != new_frame {
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ttbr0_el1_write(new_frame);
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tlb_invalidate();
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}
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}
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@ -237,11 +333,13 @@ impl InactivePageTable for InactivePageTable0 {
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debug!("switch table {:?} -> {:?}", old_frame, new_frame);
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if old_frame != new_frame {
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ttbr0_el1_write(new_frame);
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tlb_invalidate();
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}
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f();
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debug!("switch table {:?} -> {:?}", new_frame, old_frame);
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if old_frame != new_frame {
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ttbr0_el1_write(old_frame);
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tlb_invalidate();
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}
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}
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@ -264,13 +362,12 @@ impl InactivePageTable for InactivePageTable0 {
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impl InactivePageTable0 {
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fn map_kernel(&mut self) {
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let mut table = unsafe { &mut *(0xffff_ffff_ffff_f000 as *mut Aarch64PageTable) };
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// Kernel at 0xffff_ff00_0000_0000
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// Kernel stack at 0x0000_57ac_0000_0000 (defined in bootloader crate)
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let e0 = table[0].clone();
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let table = unsafe { &mut *ROOT_PAGE_TABLE };
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let e0 = table[KERNEL_PML4].clone();
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assert!(!e0.is_unused());
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self.edit(|_| {
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table[0].set_addr(e0.addr(), e0.flags() & EF::GLOBAL);
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//table[175].set_addr(estack.addr(), estack.flags() & EF::GLOBAL);
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table[KERNEL_PML4].set_addr(e0.addr(), e0.flags() & EF::GLOBAL);
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});
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}
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}
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equation314
6 years ago