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@ -15,30 +15,24 @@ const VGA_AR_PAS: u8 = 0x20;
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const VBE_DISPI_ENABLED: u16 = 0x01;
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const PCIR_COMMAND: u8 = 0x04;
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const PCIM_CMD_PORTEN: u16 = 0x0001;
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const PCIM_CMD_MEMEN: u16 = 0x0002;
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const PCIM_CMD_PORTEN: u32 = 0x0001;
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const PCIM_CMD_MEMEN: u32 = 0x0002;
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fn pci_read_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8) -> u16 {
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// enable access mechanism
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let data = 0xF0 | (func << 1);
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write(pci_base + 0xcf8, data);
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write(pci_base + 0xcfa, bus);
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// calculate port address
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let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
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fn pci_read_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8) -> u32 {
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// write config address
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let address = (1 << 31) | ((bus as u32) << 16) | ((slot as u32) << 11) | ((func as u32) << 8) | (offset as u32);
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write(pci_base + 0xcf8, address);
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// do the actual work
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read(pci_base + addr as usize)
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read(pci_base + 0xcfc)
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}
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fn pci_write_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8, value: u16) {
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// enable access mechanism
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let data = 0xF0 | (func << 1);
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write(pci_base + 0xcf8, data);
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write(pci_base + 0xcfa, bus);
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// calculate port address
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let addr: u16 = (0xC000 | ((slot as u16) << 8) | (offset as u16)) & 0xFFFC;
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fn pci_write_config(pci_base: usize, bus: u8, slot: u8, func: u8, offset: u8, value: u32) {
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// write config address
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let address = (1 << 31) | ((bus as u32) << 16) | ((slot as u32) << 11) | ((func as u32) << 8) | (offset as u32);
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write(pci_base + 0xcf8, address);
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// do the actual work
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write(pci_base + addr as usize, value);
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write(pci_base + 0xcfc, value)
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}
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pub fn init(pci_base: usize, vga_base: usize, x_res: u16, y_res: u16) {
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