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//! driver for qemu stdvga (Cirrus)
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use crate::util::{read, write};
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const VGA_MMIO_OFFSET: usize = 0x400 - 0x3c0;
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const VBE_MMIO_OFFSET: usize = 0x500;
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const VGA_AR_ADDR: u16 = 0x3C0;
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const VBE_DISPI_INDEX_XRES: u16 = 0x01;
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const VBE_DISPI_INDEX_YRES: u16 = 0x02;
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const VBE_DISPI_INDEX_BPP: u16 = 0x03;
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const VBE_DISPI_INDEX_ENABLE: u16 = 0x04;
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const VGA_AR_PAS: u8 = 0x20;
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const VBE_DISPI_ENABLED: u16 = 0x01;
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pub fn init(vga_base: usize, x_res: u16, y_res: u16) {
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let vga_write_io = |offset: u16, value: u8| {
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write(vga_base + VGA_MMIO_OFFSET + (offset as usize), value);
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};
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let vga_write_vbe = |offset: u16, value: u16| {
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write(vga_base + VBE_MMIO_OFFSET + (offset as usize) * 2, value);
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};
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let vga_read_vbe = |offset: u16| -> u16 {
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read(vga_base + VBE_MMIO_OFFSET + (offset as usize) * 2)
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};
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// enable palette access
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vga_write_io(VGA_AR_ADDR, VGA_AR_PAS);
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// set resolution and color depth
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vga_write_vbe(VBE_DISPI_INDEX_XRES, x_res);
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vga_write_vbe(VBE_DISPI_INDEX_YRES, y_res);
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vga_write_vbe(VBE_DISPI_INDEX_BPP, 8);
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// enable vbe
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let vbe_enable = vga_read_vbe(VBE_DISPI_INDEX_ENABLE) | VBE_DISPI_ENABLED;
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vga_write_vbe(VBE_DISPI_INDEX_ENABLE, vbe_enable);
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}
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@ -1 +1 @@
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Subproject commit 215b8c52b33ef5f31935fe6be1abec57b64d8866
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Subproject commit 07619a48d4e8051766c294d9d616337869e4c1a0
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