New crate `bbl`, port `sbi` mod.

Cargo.toml

@@ -40,6 +40,7 @@ ucore-memory = { path = "crate/memory" }
 
 [target.riscv32i-unknown-none.dependencies]
 riscv = { git = "https://github.com/riscv-rust/riscv" }
+bbl = { path = "crate/bbl" }
 
 [build-dependencies]
 cc = "1.0"

Makefile

@@ -80,7 +80,7 @@ ld := $(prefix)ld
 objdump := $(prefix)objdump
 cc := $(prefix)gcc
 
-.PHONY: all clean run iso build asm doc justrun
+.PHONY: all clean run iso build asm doc justrun kernel
 
 all: $(kernel)
 
@@ -125,11 +125,11 @@ build/os-riscv32.iso: $(kernel)
 	 make && \
 	 cp bbl ../../$@
 
-$(kernel): $(rust_lib) $(assembly_object_files) $(linker_script)
+$(kernel): kernel $(assembly_object_files) $(linker_script)
 	@$(ld) -n --gc-sections -T $(linker_script) -o $(kernel) \
 		$(assembly_object_files) $(rust_lib)
 
-$(rust_lib):
+kernel:
 	@RUST_TARGET_PATH=$(shell pwd) CC=$(cc) xargo build $(build_args)
 
 # compile assembly files

crate/bbl/Cargo.toml

@@ -0,0 +1,6 @@
+[package]
+name = "bbl"
+version = "0.1.0"
+authors = ["WangRunji <wangrunji0408@163.com>"]
+
+[dependencies]

crate/bbl/src/lib.rs

@@ -0,0 +1,4 @@
+#![no_std]
+#![feature(asm)]
+
+pub mod sbi;

crate/bbl/src/sbi.rs

@@ -0,0 +1,60 @@
+//! Port from sbi.h
+
+#[inline(always)]
+fn sbi_call(which: u32, arg0: u32, arg1: u32, arg2: u32) -> u32 {
+    let ret;
+    unsafe {
+        asm!("ecall"
+            : "={x10}" (ret)
+            : "{x10}" (arg0), "{x11}" (arg1), "{x12}" (arg2), "{x17}" (which)
+            : "memory"
+            : "volatile");
+    }
+    ret
+}
+
+pub fn console_putchar(ch: u32) {
+    sbi_call(SBI_CONSOLE_PUTCHAR, ch, 0, 0);
+}
+
+pub fn console_getchar() -> u32 {
+    sbi_call(SBI_CONSOLE_GETCHAR, 0, 0, 0)
+}
+
+pub fn shutdown() {
+    sbi_call(SBI_SHUTDOWN, 0, 0, 0);
+}
+
+pub fn set_timer(stime_value: u64) {
+    sbi_call(SBI_SET_TIMER, stime_value as u32, (stime_value >> 32) as u32, 0);
+}
+
+pub fn clear_ipi() {
+    sbi_call(SBI_CLEAR_IPI, 0, 0, 0);
+}
+
+pub fn send_ipi(hart_mask: *const u32) {
+    sbi_call(SBI_SEND_IPI, hart_mask as u32, 0, 0);
+}
+
+pub fn remote_fence_i(hart_mask: *const u32) {
+    sbi_call(SBI_REMOTE_FENCE_I, hart_mask as u32, 0, 0);
+}
+
+pub fn remote_sfence_vma(hart_mask: *const u32, _start: u32, _size: u32) {
+    sbi_call(SBI_REMOTE_SFENCE_VMA, hart_mask as u32, 0, 0);
+}
+
+pub fn remote_sfence_vma_asid(hart_mask: *const u32, _start: u32, _size: u32, _asid: u32) {
+    sbi_call(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask as u32, 0, 0);
+}
+
+const SBI_SET_TIMER: u32 = 0;
+const SBI_CONSOLE_PUTCHAR: u32 = 1;
+const SBI_CONSOLE_GETCHAR: u32 = 2;
+const SBI_CLEAR_IPI: u32 = 3;
+const SBI_SEND_IPI: u32 = 4;
+const SBI_REMOTE_FENCE_I: u32 = 5;
+const SBI_REMOTE_SFENCE_VMA: u32 = 6;
+const SBI_REMOTE_SFENCE_VMA_ASID: u32 = 7;
+const SBI_SHUTDOWN: u32 = 8;

src/arch/riscv32/mod.rs

@@ -1,3 +1,8 @@
 global_asm!(include_str!("boot/entry.S"));
 
 extern crate riscv;
+extern crate bbl;
+
+pub fn test() {
+    bbl::sbi::console_putchar(b'g' as u8 as u32);
+}

src/lib.rs

@@ -102,6 +102,7 @@ mod arch;
 #[no_mangle]
 #[cfg(target_arch = "riscv")]
 pub extern fn rust_main() -> ! {
+    arch::test();
     loop {}
 }