Add part of comments for riscv32 module

kernel/src/arch/riscv32/memory.rs

@@ -3,6 +3,10 @@ use memory::{active_table, FRAME_ALLOCATOR, init_heap, MemoryArea, MemoryAttr, M
 use super::riscv::{addr::*, register::sstatus};
 use ucore_memory::PAGE_SIZE;
 
+/*
+* @brief:
+*   Init the mermory management module, allow memory access and set up page table and init heap and frame allocator
+*/
 pub fn init() {
     #[repr(align(4096))]  // align the PageData struct to 4096 bytes
     struct PageData([u8; PAGE_SIZE]);
@@ -17,6 +21,10 @@ pub fn init() {
     init_heap();
 }
 
+/*
+* @brief: 
+*   Init frame allocator, here use a BitAlloc implemented by segment tree.
+*/
 fn init_frame_allocator() {
     use bit_allocator::BitAlloc;
     use core::ops::Range;
@@ -44,6 +52,10 @@ fn init_frame_allocator() {
     }
 }
 
+/*
+* @brief: 
+*   remmap the kernel memory address
+*/
 fn remap_the_kernel() {
     use consts::{KERNEL_HEAP_OFFSET, KERNEL_HEAP_SIZE};
     // set up kernel stack

kernel/src/arch/riscv32/paging.rs

@@ -42,10 +42,22 @@ pub struct PageEntry(PageTableEntry);
 impl PageTable for ActivePageTable {
     type Entry = PageEntry;
 
+    /*
+    * @param: 
+    *   addr: the virtual addr to be matched
+    *   target: the physical addr to be matched with addr
+    * @brief: 
+    *   map the virtual address 'addr' to the physical address 'target' in pagetable.
+    * @retval: 
+    *   the matched PageEntry
+    */
     fn map(&mut self, addr: usize, target: usize) -> &mut PageEntry {
+        // the flag for the new page entry
         let flags = EF::VALID | EF::READABLE | EF::WRITABLE;
+        // here page is for the virtual address while frame is for the physical, both of them is 4096 bytes align
         let page = Page::of_addr(VirtAddr::new(addr));
         let frame = Frame::of_addr(PhysAddr::new(target as u32));
+        // map the page to the frame using FrameAllocatorForRiscv
         self.0.map_to(page, frame, flags, &mut FrameAllocatorForRiscv)
             .unwrap().flush();
         self.get_entry(addr)

kernel/src/arch/riscv32/timer.rs

@@ -1,11 +1,19 @@
 use super::riscv::register::*;
 use super::bbl::sbi;
 
+/*
+* @brief: 
+*   get timer cycle for 64 bit cpu
+*/ 
 #[cfg(target_pointer_width = "64")]
 pub fn get_cycle() -> u64 {
     time::read() as u64
 }
 
+/*
+* @brief: 
+*   get timer cycle for 32 bit cpu
+*/ 
 #[cfg(target_pointer_width = "32")]
 pub fn get_cycle() -> u64 {
     loop {
@@ -18,6 +26,10 @@ pub fn get_cycle() -> u64 {
     }
 }
 
+/*
+* @brief: 
+*   enable supervisor timer interrupt and set next timer interrupt
+*/
 pub fn init() {
     // Enable supervisor timer interrupt
     unsafe { sie::set_stimer(); }
@@ -26,14 +38,20 @@ pub fn init() {
     info!("timer: init end");
 }
 
-// set the next timer interrupt
+/*
+* @brief: 
+*   set the next timer interrupt
+*/
 pub fn set_next() {
     // 100Hz @ QEMU
     let timebase = 250000;
     set_timer(get_cycle() + timebase);
 }
 
-// set time for timer interrupt
+/*
+* @brief: 
+*   set time for timer interrupt
+*/
 fn set_timer(t: u64) {
     #[cfg(feature = "no_bbl")]
     unsafe {