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@ -153,6 +153,7 @@ impl Context {
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/// Push all callee-saved registers at the current kernel stack.
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/// Push all callee-saved registers at the current kernel stack.
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/// Store current sp, switch to target.
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/// Store current sp, switch to target.
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/// Pop all callee-saved registers, then return to the target.
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/// Pop all callee-saved registers, then return to the target.
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#[cfg(target_arch = "riscv32")]
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#[naked]
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#[naked]
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#[inline(never)]
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#[inline(never)]
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pub unsafe extern fn switch(&mut self, target: &mut Self) {
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pub unsafe extern fn switch(&mut self, target: &mut Self) {
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@ -201,6 +202,55 @@ impl Context {
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: : : : "volatile" )
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: : : : "volatile" )
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}
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}
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#[cfg(target_arch = "riscv64")]
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#[naked]
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#[inline(never)]
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pub unsafe extern fn switch(&mut self, target: &mut Self) {
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asm!(
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"
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// save from's registers
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addi sp, sp, -8*14
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sd sp, 0(a0)
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sd ra, 0*8(sp)
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sd s0, 2*8(sp)
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sd s1, 3*8(sp)
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sd s2, 4*8(sp)
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sd s3, 5*8(sp)
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sd s4, 6*8(sp)
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sd s5, 7*8(sp)
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sd s6, 8*8(sp)
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sd s7, 9*8(sp)
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sd s8, 10*8(sp)
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sd s9, 11*8(sp)
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sd s10, 12*8(sp)
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sd s11, 13*8(sp)
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csrrs s11, 0x180, x0 // satp
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sd s11, 1*8(sp)
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// restore to's registers
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ld sp, 0(a1)
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ld s11, 1*8(sp)
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csrrw x0, 0x180, s11 // satp
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ld ra, 0*8(sp)
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ld s0, 2*8(sp)
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ld s1, 3*8(sp)
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ld s2, 4*8(sp)
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ld s3, 5*8(sp)
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ld s4, 6*8(sp)
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ld s5, 7*8(sp)
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ld s6, 8*8(sp)
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ld s7, 9*8(sp)
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ld s8, 10*8(sp)
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ld s9, 11*8(sp)
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ld s10, 12*8(sp)
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ld s11, 13*8(sp)
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addi sp, sp, 8*14
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sd zero, 0(a1)
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ret"
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: : : : "volatile" )
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}
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/*
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/*
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* @brief:
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* @brief:
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* generate a null Context
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* generate a null Context
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@ -274,4 +324,4 @@ impl Context {
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pub unsafe fn get_init_tf(&self) -> TrapFrame {
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pub unsafe fn get_init_tf(&self) -> TrapFrame {
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(*(self.0 as *const InitStack)).tf.clone()
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(*(self.0 as *const InitStack)).tf.clone()
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}
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}
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}
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}
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