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@ -1,4 +1,16 @@
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use riscv::register::*;
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#[cfg(feature = "m_mode")]
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use riscv::register::{
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mstatus as xstatus,
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mscratch as xscratch,
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mtvec as xtvec,
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};
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#[cfg(not(feature = "m_mode"))]
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use riscv::register::{
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sstatus as xstatus,
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sscratch as xscratch,
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stvec as xtvec,
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};
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use riscv::register::{mcause, mepc, sie};
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pub use self::context::*;
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use crate::memory::{MemorySet, InactivePageTable0};
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use log::*;
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@ -17,13 +29,16 @@ pub fn init() {
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unsafe {
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// Set sscratch register to 0, indicating to exception vector that we are
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// presently executing in the kernel
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sscratch::write(0);
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xscratch::write(0);
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// Set the exception vector address
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stvec::write(__alltraps as usize, stvec::TrapMode::Direct);
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xtvec::write(__alltraps as usize, xtvec::TrapMode::Direct);
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// Enable IPI
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sie::set_ssoft();
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// Enable serial interrupt
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sie::set_sext();
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// NOTE: In M-mode: mie.MSIE is set by BBL.
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// mie.MEIE can not be set in QEMU v3.0
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// (seems like a bug)
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}
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info!("interrupt: init end");
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}
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@ -34,7 +49,7 @@ pub fn init() {
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*/
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#[inline(always)]
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pub unsafe fn enable() {
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sstatus::set_sie();
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xstatus::set_xie();
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}
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/*
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@ -45,8 +60,8 @@ pub unsafe fn enable() {
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*/
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#[inline(always)]
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pub unsafe fn disable_and_store() -> usize {
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let e = sstatus::read().sie() as usize;
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sstatus::clear_sie();
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let e = xstatus::read().xie() as usize;
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xstatus::clear_xie();
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e
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}
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@ -59,7 +74,7 @@ pub unsafe fn disable_and_store() -> usize {
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#[inline(always)]
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pub unsafe fn restore(flags: usize) {
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if flags != 0 {
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sstatus::set_sie();
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xstatus::set_xie();
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}
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}
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@ -71,9 +86,15 @@ pub unsafe fn restore(flags: usize) {
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*/
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#[no_mangle]
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pub extern fn rust_trap(tf: &mut TrapFrame) {
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use riscv::register::scause::{Trap, Interrupt as I, Exception as E};
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use self::mcause::{Trap, Interrupt as I, Exception as E};
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trace!("Interrupt @ CPU{}: {:?} ", super::cpu::id(), tf.scause.cause());
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match tf.scause.cause() {
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// M-mode only
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Trap::Interrupt(I::MachineExternal) => serial(),
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Trap::Interrupt(I::MachineSoft) => ipi(),
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Trap::Interrupt(I::MachineTimer) => timer(),
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Trap::Exception(E::MachineEnvCall) => sbi(tf),
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Trap::Interrupt(I::SupervisorExternal) => serial(),
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Trap::Interrupt(I::SupervisorSoft) => ipi(),
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Trap::Interrupt(I::SupervisorTimer) => timer(),
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@ -87,6 +108,12 @@ pub extern fn rust_trap(tf: &mut TrapFrame) {
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trace!("Interrupt end");
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}
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/// Call BBL SBI functions for M-mode kernel
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fn sbi(tf: &mut TrapFrame) {
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(super::BBL.mcall_trap)(tf.x.as_ptr(), tf.scause.bits(), tf.sepc);
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tf.sepc += 4;
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}
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fn serial() {
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crate::trap::serial(super::io::getchar());
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}
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@ -101,8 +128,8 @@ fn ipi() {
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* process timer interrupt
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*/
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fn timer() {
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crate::trap::timer();
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super::timer::set_next();
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crate::trap::timer();
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}
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/*
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@ -124,9 +151,8 @@ fn syscall(tf: &mut TrapFrame) {
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* process IllegalInstruction exception
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*/
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fn illegal_inst(tf: &mut TrapFrame) {
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if !emulate_mul_div(tf) {
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crate::trap::error(tf);
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}
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(super::BBL.illegal_insn_trap)(tf.x.as_ptr(), tf.scause.bits(), tf.sepc);
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tf.sepc = mepc::read();
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}
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/*
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@ -136,73 +162,10 @@ fn illegal_inst(tf: &mut TrapFrame) {
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* process page fault exception
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*/
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fn page_fault(tf: &mut TrapFrame) {
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let addr = stval::read();
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let addr = tf.stval;
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trace!("\nEXCEPTION: Page Fault @ {:#x}", addr);
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if !crate::memory::page_fault_handler(addr) {
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crate::trap::error(tf);
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}
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}
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/// Migrate from riscv-pk
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/*
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* @param:
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* TrapFrame: the Trapframe for the illegal inst exception
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* @brief:
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* emulate the multiply and divide operation (if not this kind of operation return false)
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* @retval:
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* a bool indicates whether emulate the multiply and divide operation successfully
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*/
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fn emulate_mul_div(tf: &mut TrapFrame) -> bool {
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let insn = unsafe { *(tf.sepc as *const usize) };
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let rs1 = tf.x[get_reg(insn, RS1)];
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let rs2 = tf.x[get_reg(insn, RS2)];
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let rd = if (insn & MASK_MUL) == MATCH_MUL {
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rs1 * rs2
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} else if (insn & MASK_DIV) == MATCH_DIV {
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((rs1 as i32) / (rs2 as i32)) as usize
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} else if (insn & MASK_DIVU) == MATCH_DIVU {
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rs1 / rs2
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} else if (insn & MASK_REM) == MATCH_REM {
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((rs1 as i32) % (rs2 as i32)) as usize
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} else if (insn & MASK_REMU) == MATCH_REMU {
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rs1 % rs2
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} else if (insn & MASK_MULH) == MATCH_MULH {
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(((rs1 as i32 as i64) * (rs2 as i32 as i64)) >> 32) as usize
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} else if (insn & MASK_MULHU) == MATCH_MULHU {
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(((rs1 as i64) * (rs2 as i64)) >> 32) as usize
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} else if (insn & MASK_MULHSU) == MATCH_MULHSU {
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(((rs1 as i32 as i64) * (rs2 as i64)) >> 32) as usize
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} else {
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return false;
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};
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tf.x[get_reg(insn, RD)] = rd;
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tf.sepc += 4; // jump to next instruction
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return true;
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fn get_reg(inst: usize, offset: usize) -> usize {
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(inst >> offset) & 0x1f
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}
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const RS1: usize = 15;
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const RS2: usize = 20;
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const RD: usize = 7;
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const MATCH_MUL: usize = 0x2000033;
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const MASK_MUL: usize = 0xfe00707f;
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const MATCH_MULH: usize = 0x2001033;
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const MASK_MULH: usize = 0xfe00707f;
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const MATCH_MULHSU: usize = 0x2002033;
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const MASK_MULHSU: usize = 0xfe00707f;
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const MATCH_MULHU: usize = 0x2003033;
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const MASK_MULHU: usize = 0xfe00707f;
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const MATCH_DIV: usize = 0x2004033;
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const MASK_DIV: usize = 0xfe00707f;
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const MATCH_DIVU: usize = 0x2005033;
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const MASK_DIVU: usize = 0xfe00707f;
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const MATCH_REM: usize = 0x2006033;
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const MASK_REM: usize = 0xfe00707f;
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const MATCH_REMU: usize = 0x2007033;
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const MASK_REMU: usize = 0xfe00707f;
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}
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WangRunji
6 years ago