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NN2FPGA
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master
ready
#1
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a1d39e6743
Update README.md
master
pl5g92irw
2022-04-05 23:35:30 +0800
db09feff98
Merge pull request '初始文件同步' (
#1
) from ready into master
pl5g92irw
2022-04-05 23:34:03 +0800
48bebc411a
FPGA神经网络所重复调动的函数模块,Verilog语言
#1
ready
pl5g92irw
2022-04-05 23:32:50 +0800
267521f871
以Verilog语言实现FPGA神经网络
pl5g92irw
2022-04-05 23:30:48 +0800
3240e076ea
Python描述的神经网络模型
pl5g92irw
2022-04-05 23:29:19 +0800
92fa790709
Initial commit
pl5g92irw
2022-04-05 23:27:17 +0800