fix(ARegfile): 修正寄存器位宽注释为XLEN

10 months ago · 8e6db9f912
parent 5c2305b0ed
commit 8e6db9f912
1 changed files with 1 additions and 1 deletions
--- a/chisel/playground/src/pipeline/decode/ARegfile.scala
+++ b/chisel/playground/src/pipeline/decode/ARegfile.scala
@ -28,7 +28,7 @@ class ARegFile extends Module {
    val write = Flipped(new RegWrite())
  })

-  // 定义32个32位寄存器
+  // 定义32个XLEN位寄存器
  val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))

  // 写寄存器堆