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271 lines
12 KiB
271 lines
12 KiB
3 years ago
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`timescale 1ns / 1ps
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// 数据通路
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`include "pipeline_regs.sv"
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import Pipe_Buf_Reg_PKG::*;
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module Datapath #(
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parameter PC_W = 9, // Program Counter
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parameter INS_W = 32, // Instruction Width
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parameter DATA_W = 32, // Data WriteData
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parameter DM_ADDRESS = 9, // Data Memory Address
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parameter ALU_CC_W = 4 // ALU Control Code Width
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)(
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input logic clock,
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input logic reset, // reset , sets the PC to zero
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input logic reg_write_en, // Register file writing enable
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input logic MemtoReg, // Memory or ALU MUX
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input logic alu_src, // Register file or Immediate MUX
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input logic mem_write_en, // Memroy Writing Enable
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input logic mem_read_en, // Memroy Reading Enable
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input logic branch_taken, // Branch Enable
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input logic jalr_sel, // Jalr Mux Select
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input logic [1:0] alu_op,
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input logic [1:0] RWSel, // Mux4to1 Select
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input logic [ALU_CC_W -1:0] alu_cc, // ALU Control Code ( input of the ALU )
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output logic [6:0] opcode,
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output logic [6:0] funct7,
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output logic [2:0] funct3,
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output logic [1:0] aluop_current,
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output logic [DATA_W-1:0] wb_data // data write back to register
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);
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// ====================================================================================
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// Instruction Fetch (IF)
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// ====================================================================================
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//
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// peripheral logic here.
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//
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logic BrFlush, stall;
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logic [31:0] PC_mux_result, PC, PCplus4, BrPC, instr;
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flipflop #(32) PC_unit(.clock(clock), .reset(reset), .d(PC_mux_result), .stall(stall), .q(PC));
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mux2 PC_mux(.d0(PCplus4), .d1(BrPC), .s(BrFlush), .y(PC_mux_result));
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adder #(32) PC_adder(.a(PC), .b(32'd4), .y(PCplus4));
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//
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// add your instruction memory
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//
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Insn_mem IM(.read_address(PC[PC_W - 1 : 0]), .insn(instr));
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// ====================================================================================
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// End of Instruction Fetch (IF)
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// ====================================================================================
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if_id_reg RegA;
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id_ex_reg RegB;
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ex_mem_reg RegC;
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mem_wb_reg RegD;
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always @(posedge clock, posedge reset)
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begin
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// add your logic here to update the IF_ID_Register
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if (BrFlush | reset)
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begin
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RegA.Curr_Pc <= 9'b0;
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RegA.Curr_Instr <= 32'b0;
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end
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else if (!stall)
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begin
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RegA.Curr_Pc <= PC[PC_W - 1 : 0];
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RegA.Curr_Instr <= instr;
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end
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end
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// ====================================================================================
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// Instruction Decoding (ID)
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// ====================================================================================
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//
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// peripheral logic here.
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//
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assign opcode = RegA.Curr_Instr[6:0];
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logic [31:0] rd1, rd2, ImmG;
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//
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// add your register file here.
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//
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Reg_file RF(.clock(clock), .reset(reset), .write_en(RegD.RegWrite), .write_addr(RegD.rd),
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.data_in(wb_data), .read_addr1(RegA.Curr_Instr[19:15]),
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.read_addr2(RegA.Curr_Instr[24:20]), .data_out1(rd1), .data_out2(rd2));
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//
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// add your immediate generator here
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//
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Imm_gen Imm_Gen(.inst_code(RegA.Curr_Instr), .imm_out(ImmG));
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// ====================================================================================
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// End of Instruction Decoding (ID)
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// ====================================================================================
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always @(posedge clock, posedge reset)
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begin
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// add your logic here to update the ID_EX_Register
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if (BrFlush | reset | stall)
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begin
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RegB.ALUSrc <= 1'b0;
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RegB.MemtoReg <= 1'b0;
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RegB.RegWrite <= 1'b0;
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RegB.MemRead <= 1'b0;
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RegB.MemWrite <= 1'b0;
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RegB.ALUOp <= 2'b0;
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RegB.Branch <= 1'b0;
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RegB.JalrSel <= 1'b0;
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RegB.RWSel <= 2'b0;
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RegB.Curr_Pc <= 9'b0;
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RegB.RD_One <= 32'b0;
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RegB.RD_Two <= 32'b0;
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RegB.RS_One <= 5'b0;
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RegB.RS_Two <= 5'b0;
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RegB.rd <= 5'b0;
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RegB.ImmG <= 32'b0;
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RegB.func3 <= 3'b0;
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RegB.func7 <= 7'b0;
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RegB.Curr_Instr <= 32'b0;
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end
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else if (!stall)
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begin
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RegB.ALUSrc <= alu_src;
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RegB.MemtoReg <= MemtoReg;
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RegB.RegWrite <= reg_write_en;
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RegB.MemRead <= mem_read_en;
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RegB.MemWrite <= mem_write_en;
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RegB.ALUOp <= alu_op;
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RegB.Branch <= branch_taken;
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RegB.JalrSel <= jalr_sel;
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RegB.RWSel <= RWSel;
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RegB.Curr_Pc <= RegA.Curr_Pc;
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RegB.RD_One <= rd1;
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RegB.RD_Two <= rd2;
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RegB.RS_One <= RegA.Curr_Instr[19:15];
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RegB.RS_Two <= RegA.Curr_Instr[24:20];
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RegB.rd <= RegA.Curr_Instr[11:7];
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RegB.ImmG <= ImmG;
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RegB.func3 <= RegA.Curr_Instr[14:12];
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RegB.func7 <= RegA.Curr_Instr[31:25];
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RegB.Curr_Instr <= RegA.Curr_Instr;
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end
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end
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// ====================================================================================
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// Execution (EX)
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// ====================================================================================
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//
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// add your ALU, branch unit and with peripheral logic here
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//
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logic [31:0] FA_mux_result, FB_mux_result, ALU_result, PCplusImm, PCplus4_EX, src_mux_result, lui_mux_resultA, lui_mux_resultB;
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logic [1:0] ForwardA, ForwardB;
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logic zero, if_lui1, if_lui2;
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assign aluop_current = RegB.ALUOp;
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assign funct3 = RegB.func3;
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assign funct7 = RegB.func7;
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assign if_lui = (RegC.Curr_Instr[6:0] == 7'b0110111)? 1'b1 : 1'b0;
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alu ALU(.operand_a(FA_mux_result), .operand_b(src_mux_result), .alu_ctrl(alu_cc), .alu_result(ALU_result), .zero(zero));
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BranchUnit Branch_unit(.cur_pc(RegB.Curr_Pc), .imm(RegB.ImmG), .jalr_sel(RegB.JalrSel), .branch_taken(RegB.Branch),
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.alu_result(ALU_result), .pc_plus_imm(PCplusImm), .pc_plus_4(PCplus4_EX), .branch_target(BrPC), .pc_sel(BrFlush));
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mux4 FA_mux(.d00(RegB.RD_One), .d01(lui_mux_resultA), .d10(wb_data), .d11(32'b0), .s(ForwardA), .y(FA_mux_result));
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mux4 FB_mux(.d00(RegB.RD_Two), .d01(lui_mux_resultB), .d10(wb_data), .d11(32'b0), .s(ForwardB), .y(FB_mux_result));
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mux2 src_mux(.d0(FB_mux_result), .d1(RegB.ImmG), .s(RegB.ALUSrc), .y(src_mux_result));
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mux2 lui_muxA(.d0(RegC.Alu_Result), .d1(RegC.Imm_Out), .s(if_lui), .y(lui_mux_resultA));
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mux2 lui_muxB(.d0(RegC.Alu_Result), .d1(RegC.Imm_Out), .s(if_lui), .y(lui_mux_resultB));
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// ====================================================================================
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// End of Execution (EX)
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// ====================================================================================
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always @(posedge clock, posedge reset)
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begin
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// add your logic here to update the EX_MEM_Register
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if(reset)
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begin
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RegC.RegWrite <= 1'b0;
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RegC.MemtoReg <= 1'b0;
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RegC.MemRead <= 1'b0;
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RegC.MemWrite <= 1'b0;
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RegC.RWSel <= 2'b0;
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RegC.Pc_Imm <= 32'b0;
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RegC.Pc_Four <= 32'b0;
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RegC.Imm_Out <= 32'b0;
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RegC.Alu_Result <= 32'b0;
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RegC.RD_Two <= 32'b0;
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RegC.rd <= 5'b0;
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RegC.func3 <= 3'b0;
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RegC.func7 <= 7'b0;
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RegC.Curr_Instr <= 32'b0;
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end
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else
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begin
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RegC.RegWrite <= RegB.RegWrite;
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RegC.MemtoReg <= RegB.MemtoReg;
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RegC.MemRead <= RegB.MemRead;
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RegC.MemWrite <= RegB.MemWrite;
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RegC.RWSel <= RegB.RWSel;
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RegC.Pc_Imm <= PCplusImm;
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RegC.Pc_Four <= PCplus4_EX;
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RegC.Imm_Out <= RegB.ImmG; // lui
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RegC.Alu_Result <= ALU_result;
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RegC.RD_Two <= FB_mux_result;
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RegC.rd <= RegB.rd;
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RegC.func3 <= RegB.func3;
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RegC.func7 <= RegB.func7;
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RegC.Curr_Instr <= RegB.Curr_Instr;
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end
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end
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// ====================================================================================
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// Memory Access (MEM)
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// ====================================================================================
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// add your data memory here.
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logic [31:0] ReadData;
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datamemory DM(.clock(clock), .read_en(RegC.MemRead), .write_en(RegC.MemWrite),
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.address(RegC.Alu_Result[11:0]), .data_in(RegC.RD_Two), .funct3(RegC.func3), .data_out(ReadData));
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// ====================================================================================
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// End of Memory Access (MEM)
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// ====================================================================================
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always @(posedge clock)
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begin
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// add your logic here to update the MEM_WB_Register
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if(reset)
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begin
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RegD.RegWrite <= 1'b0;
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RegD.MemtoReg <= 1'b0;
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RegD.RWSel <= 2'b0;
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RegD.Pc_Imm <= 32'b0;
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RegD.Pc_Four <= 32'b0;
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RegD.Imm_Out <= 32'b0;
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RegD.Alu_Result <= 32'b0;
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RegD.MemReadData <= 32'b0;
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RegD.rd <= 5'b0;
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RegD.Curr_Instr <= 5'b0;
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end
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else
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begin
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RegD.RegWrite <= RegC.RegWrite;
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RegD.MemtoReg <= RegC.MemtoReg;
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RegD.RWSel <= RegC.RWSel;
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RegD.Pc_Imm <= RegC.Pc_Imm;
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RegD.Pc_Four <= RegC.Pc_Four;
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RegD.Imm_Out <= RegC.Imm_Out;
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RegD.Alu_Result <= RegC.Alu_Result;
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RegD.MemReadData <= ReadData;
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RegD.rd <= RegC.rd;
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RegD.Curr_Instr <= RegC.Curr_Instr;
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end
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end
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// ====================================================================================
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// Write Back (WB)
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// ====================================================================================
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//
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// add your write back logic here.
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//
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logic [31:0] res_mux_result;
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mux2 res_mux(.d0(RegD.Alu_Result), .d1(RegD.MemReadData), .s(RegD.MemtoReg), .y(res_mux_result));
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mux4 wrs_mux(.d00(res_mux_result), .d01(RegD.Pc_Four), .d10(RegD.Imm_Out), .d11(RegD.Pc_Imm), .s(RegD.RWSel), .y(wb_data));
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// ====================================================================================
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// End of Write Back (WB)
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// ====================================================================================
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// ====================================================================================
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// other logic
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// ====================================================================================
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//
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// add your hazard detection logic here
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//
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Hazard_detector hazard_unit(.clock(clock), .reset(reset), .if_id_rs1(RegA.Curr_Instr[19:15]), .if_id_rs2(RegA.Curr_Instr[24:20]),
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.id_ex_rd(RegB.rd), .id_ex_memread(RegB.MemRead), .stall(stall));
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//
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// add your forwarding logic here
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//
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ForwardingUnit forwarding_unit(.rs1(RegB.RS_One), .rs2(RegB.RS_Two), .ex_mem_rd(RegC.rd), .mem_wb_rd(RegD.rd),
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.ex_mem_regwrite(RegC.RegWrite), .mem_wb_regwrite(RegD.RegWrite), .forward_a(ForwardA), .forward_b(ForwardB));
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//
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// possible extra code
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//
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endmodule
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