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33 lines
907 B
33 lines
907 B
3 years ago
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`timescale 1ns / 1ps
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// 数据定向处理单元
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module ForwardingUnit (
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input logic [4:0] rs1,
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input logic [4:0] rs2,
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input logic [4:0] ex_mem_rd,
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input logic [4:0] mem_wb_rd,
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input logic ex_mem_regwrite,
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input logic mem_wb_regwrite,
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output logic [1:0] forward_a,
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output logic [1:0] forward_b
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);
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// define your forwarding logic here.
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always_comb
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begin
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if ((rs1 != 0) && (rs1 == ex_mem_rd) && ex_mem_regwrite)
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forward_a = 2'b01;
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else if ((rs1 != 0) && (rs1 == mem_wb_rd) && mem_wb_regwrite)
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forward_a = 2'b10;
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else
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forward_a = 2'b00;
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if ((rs2 != 0) && (rs2 == ex_mem_rd) && ex_mem_regwrite)
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forward_b = 2'b01;
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else if ((rs2 != 0) && (rs2 == mem_wb_rd) && mem_wb_regwrite)
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forward_b = 2'b10;
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else
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forward_b = 2'b00;
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end
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endmodule
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