Shard
郑几方 3 years ago
parent bb2fae9bb4
commit 2e8d21b710

@ -1,2 +1,2 @@
def adder(a,b): #返回加法运算结果y
return a+b
def adder(a, b): # 返回加法运算结果y
return a + b

@ -35,4 +35,4 @@ def alu(a, b, alu_ctrl): # a,b为两个运算数alu_ctrl为控制信号
elif alu_ctrl == '01111':
pass
else:
pass
pass

@ -1,5 +1,6 @@
class insn_mem:
memory=[8*'0']*4*1024*16
def fetch(self,address):
insn=self.memory[address]
memory = [8 * '0'] * 4 * 1024 * 16
def fetch(self, address):
insn = self.memory[address]
return insn

@ -1,5 +1,5 @@
def mux(d0,d1,s): #返回选择结果
if s=='0':
def mux(d0, d1, s): # 返回选择结果
if s == '0':
return d0
else:
return d1

@ -1,9 +1,9 @@
def mux4(d00,d01,d10,d11,s): #返回选择结果
if s=='00':
def mux4(d00, d01, d10, d11, s): # 返回选择结果
if s == '00':
return d00
elif s=='01':
elif s == '01':
return d01
elif s=='10':
elif s == '10':
return d10
else:
return d11

@ -1,25 +1,27 @@
def proc_controller(opcode):
if opcode=='0110011': #(add,and,or,sll,slt,sltu,sra,srl,sub,xor)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','10','0','0','00'
elif opcode=='0110111': #(lui)20位立即数
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','00','0','0','10'
elif opcode=='1101111': #(jal)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01'
elif opcode=='0010011': #(addi,andi,ori,slli,slti,sltiu,srai,srli,xori)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','0','0','00'
elif opcode=='0000011': #(lb,lbu,lh,lhu,lw)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','1','1','1','0','00','0','0','00'
elif opcode=='1100111': #(jalr)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','1','1','01'
elif opcode=='0100011': #(sb, sh, sw)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','0','0','1','00','0','0','00'
elif opcode=='1100011': #(beq,bge,bgeu,blt,bne,bltu)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','01','1','0','00'
elif opcode=='1101111': #(jal)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01'
if opcode == '0110011': # (add,and,or,sll,slt,sltu,sra,srl,sub,xor)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '10', '0', '0', '00'
elif opcode == '0110111': # (lui)20位立即数
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '00', '0', '0', '10'
elif opcode == '1101111': # (jal)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01'
elif opcode == '0010011': # (addi,andi,ori,slli,slti,sltiu,srai,srli,xori)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '0', '0', '00'
elif opcode == '0000011': # (lb,lbu,lh,lhu,lw)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '1', '1', '1', '0', '00', '0', '0', '00'
elif opcode == '1100111': # (jalr)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '1', '1', '01'
elif opcode == '0100011': # (sb, sh, sw)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '0', '0', '1', '00', '0', '0', '00'
elif opcode == '1100011': # (beq,bge,bgeu,blt,bne,bltu)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '01', '1', '0', '00'
elif opcode == '1101111': # (jal)
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01'
#################################
elif opcode=='0010111': #(auipc)20位立即数
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','00','1','0','11'
elif opcode == '0010111': # (auipc)20位立即数
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '00', '1', '0', '11'
else:
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','00','0','0','00'
ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '00', '0', '0', '00'
return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel
Loading…
Cancel
Save