Shard
郑几方 3 years ago
parent b93aa5abb5
commit bb2fae9bb4

@ -1,36 +1,38 @@
import binandint import binandint
def alu(a,b,alu_ctrl): #a,b为两个运算数alu_ctrl为控制信号返回运算结果result与是否为0 zero
if alu_ctrl=='00000':
def alu(a, b, alu_ctrl): # a,b为两个运算数alu_ctrl为控制信号返回运算结果result与是否为0 zero
if alu_ctrl == '00000':
pass pass
elif alu_ctrl=='00001': elif alu_ctrl == '00001':
pass pass
elif alu_ctrl=='00010': elif alu_ctrl == '00010':
pass pass
elif alu_ctrl=='00011': elif alu_ctrl == '00011':
pass pass
elif alu_ctrl=='00100': elif alu_ctrl == '00100':
pass pass
elif alu_ctrl=='00101': elif alu_ctrl == '00101':
pass pass
elif alu_ctrl=='00110': elif alu_ctrl == '00110':
pass pass
elif alu_ctrl=='00111': elif alu_ctrl == '00111':
pass pass
elif alu_ctrl=='01000': elif alu_ctrl == '01000':
pass pass
elif alu_ctrl=='01001': elif alu_ctrl == '01001':
pass pass
elif alu_ctrl=='01010': elif alu_ctrl == '01010':
pass pass
elif alu_ctrl=='01011': elif alu_ctrl == '01011':
pass pass
elif alu_ctrl=='01100': elif alu_ctrl == '01100':
pass pass
elif alu_ctrl=='01101': elif alu_ctrl == '01101':
pass pass
elif alu_ctrl=='01110': elif alu_ctrl == '01110':
pass pass
elif alu_ctrl=='01111': elif alu_ctrl == '01111':
pass pass
else: else:
pass pass

@ -1,48 +1,49 @@
def alu_controller(alu_op,funct7,funct3): #alu_op来自主控制器funct7和funct3来自指令的特定部位 返回alu_ctrl def alu_controller(alu_op, funct7,
if alu_op=='00': funct3): # alu_op来自主控制器funct7和funct3来自指令的特定部位 返回alu_ctrl
opreation='00000' #lw.sw.auipc if alu_op == '00':
elif alu_op=='01': opreation = '00000' # lw.sw.auipc
if funct3=='000': elif alu_op == '01':
opreation='00101' #beq if funct3 == '000':
elif funct3=='001': opreation = '00101' # beq
opreation='00110' #bne elif funct3 == '001':
elif funct3=='100': opreation = '00110' # bne
opreation='00111' #blt elif funct3 == '100':
elif funct3=='101': opreation = '00111' # blt
opreation='01000' #bge elif funct3 == '101':
elif funct3=='110': opreation = '01000' # bge
opreation='01001' #bltu elif funct3 == '110':
elif funct3=='111': opreation = '01001' # bltu
opreation='01010' #bgeu elif funct3 == '111':
opreation = '01010' # bgeu
else: else:
opreation='00000' opreation = '00000'
elif alu_op=='10': elif alu_op == '10':
if funct3=='000': if funct3 == '000':
if funct7=='0100000': #sub if funct7 == '0100000': # sub
opreation='00001' opreation = '00001'
else: #add,addi else: # add,addi
opreation='00000' opreation = '00000'
elif funct3=='100': elif funct3 == '100':
opreation='01100' #xor,xori opreation = '01100' # xor,xori
elif funct3=='110': elif funct3 == '110':
opreation='00010' #or,ori opreation = '00010' # or,ori
elif funct3=='111': elif funct3 == '111':
opreation='00011' #and, andi opreation = '00011' # and, andi
elif funct3=='010': elif funct3 == '010':
opreation='00100' #slt,slti opreation = '00100' # slt,slti
elif funct3=='001': elif funct3 == '001':
opreation='01101' #sll,slli 未存在 opreation = '01101' # sll,slli 未存在
elif funct3=='011': elif funct3 == '011':
opreation='01110' #sliu,sltiu 未存在 opreation = '01110' # sliu,sltiu 未存在
elif funct3=='101': elif funct3 == '101':
if funct7=='0100000': #sra,srai if funct7 == '0100000': # sra,srai
opreation='01111' opreation = '01111'
else: #srl,srli else: # srl,srli
opreation='10000' opreation = '10000'
else: else:
opreation='00000' opreation = '00000'
elif alu_op=='11': #jal elif alu_op == '11': # jal
opreation='01011' opreation = '01011'
else: else:
opreation='00000' opreation = '00000'
return opreation return opreation

@ -1,9 +1,10 @@
def branch_unit(cur_pc,imm,jalr_sel,branch_taken,alu_result): #输入值为当前pcint立即数jalr信号是否跳转信号alu运算结果(全是int型) def branch_unit(cur_pc, imm, jalr_sel, branch_taken,
pc_plus_4=cur_pc+4 #输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了,需要回头再看) alu_result): # 输入值为当前pcint立即数jalr信号是否跳转信号alu运算结果(全是int型)
pc_plus_imm=cur_pc+imm pc_plus_4 = cur_pc + 4 # 输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了,需要回头再看)
pc_sel = jalr_sel | (branch_taken & (alu_result%2)) pc_plus_imm = cur_pc + imm
if jalr_sel==1: pc_sel = jalr_sel | (branch_taken & (alu_result % 2))
branch_target=alu_result&(2**32-2) if jalr_sel == 1:
branch_target = alu_result & (2**32 - 2)
else: else:
branch_target=cur_pc+imm*2 branch_target = cur_pc + imm * 2
return pc_plus_imm,pc_plus_4,branch_target,pc_sel return pc_plus_imm, pc_plus_4, branch_target, pc_sel

@ -1,26 +1,28 @@
class data_mem: class data_mem:
memory=[8*'0']*4*1024*16 memory = [8 * '0'] * 4 * 1024 * 16
def mem(self,write_en,read_en,address,data_in,funct3): #写使能,读使能,(使能为int的0或1)地址输入数据func3 #输出为data_out
def mem(self, write_en, read_en, address, data_in, funct3
): # 写使能,读使能,(使能为int的0或1)地址输入数据func3 # 输出为data_out
if write_en: if write_en:
if funct3=='000': if funct3 == '000':
pass pass
elif funct3=='001': elif funct3 == '001':
pass pass
elif funct3=='010': elif funct3 == '010':
pass pass
else: else:
pass pass
if read_en: if read_en:
if funct3=='000': if funct3 == '000':
pass pass
elif funct3=='001': elif funct3 == '001':
pass pass
elif funct3=='010': elif funct3 == '010':
pass pass
elif funct3=='100': elif funct3 == '100':
pass pass
elif funct3=='101': elif funct3 == '101':
pass pass
else: else:
pass pass

@ -1,14 +1,15 @@
def fowardingunit(rs1,rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite): def fowardingunit(rs1, rs2, ex_mem_rd, mem_wb_rd, ex_mem_regwrite,
if rs1!=0 and rs1==ex_mem_rd and ex_mem_regwrite: mem_wb_regwrite):
forward_a='01' if rs1 != 0 and rs1 == ex_mem_rd and ex_mem_regwrite:
elif rs1!=0 and rs1==mem_wb_rd and mem_wb_regwrite: forward_a = '01'
forward_a='10' elif rs1 != 0 and rs1 == mem_wb_rd and mem_wb_regwrite:
forward_a = '10'
else: else:
forward_a='00' forward_a = '00'
if rs2!=0 and rs2==ex_mem_rd and ex_mem_regwrite: if rs2 != 0 and rs2 == ex_mem_rd and ex_mem_regwrite:
forward_b='01' forward_b = '01'
elif rs2!=0 and rs2==mem_wb_rd and mem_wb_regwrite: elif rs2 != 0 and rs2 == mem_wb_rd and mem_wb_regwrite:
forward_b='10' forward_b = '10'
else: else:
forward_b='00' forward_b = '00'
return forward_a,forward_b return forward_a, forward_b

@ -1,6 +1,6 @@
def hazard_detector(if_id_rs1,if_id_rs2,id_ex_rd,id_ex_memread): def hazard_detector(if_id_rs1, if_id_rs2, id_ex_rd, id_ex_memread):
if id_ex_memread and (id_ex_rd==if_id_rs1 or id_ex_rd==if_id_rs2): if id_ex_memread and (id_ex_rd == if_id_rs1 or id_ex_rd == if_id_rs2):
stall=1 stall = 1
else: else:
stall=0 stall = 0
return stall return stall
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