imm_gen and formatted

code/Imm_gen.py

@@ -1,17 +1,15 @@
-def Imm_gen(inst_code):
+def Imm_gen(inst_code: str) -> str:
     test = inst_code[25:32]
-    if test == '0010011':
+    if test in ['0010011', '0000011', '1100111']:  # i-Type, l, jalr
-        imm_out = 20*inst_code[0]+inst_code[0:12]
+        imm_out = inst_code[0:12].rjust(32, inst_code[0])
-    elif test == '0000011':
+    elif test == '0100011':  # s
-        pass
+        imm_out = (inst_code[0:7] + inst_code[20:25]).rjust(32, inst_code[0])
-    elif test == '0100011':
+    elif test == '1100011':  # branch
-        pass
+        imm_out = (inst_code[0] + inst_code[24] + inst_code[1:7] +
-    elif test == '1100011':
+                   inst_code[20:24]).rjust(32, inst_code[0])
-        pass
+    elif test == '1101111':  # jal
-    elif test == '1101111':
+        imm_out = (inst_code[0] + inst_code[12:20] + inst_code[11] +
-        pass
+                   inst_code[1:11]).rjust(32, inst_code[0])
-    elif test == '1100111':
+    elif test in ['0110111', '0010111']:  # lui, auipc
-        pass
+        imm_out = inst_code[0:20].rjust(32, inst_code[0])
-    elif test == '0110111':
-        pass
     return imm_out

code/alu.py

@@ -2,17 +2,17 @@ from binandint import *
 
 
 def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，返回运算结果result与是否为0 zero
-    signed = a-b
+    signed = a - b
     if alu_ctrl == '00000':  # add,jalr
-        alu_result = a+b
+        alu_result = a + b
     elif alu_ctrl == '00001':  # sub
-        alu_result = a-b
+        alu_result = a - b
     elif alu_ctrl == '00010':  # or
         alu_result = a | b
     elif alu_ctrl == '00011':  # and
         alu_result = a & b
     elif alu_ctrl == '00100':  # slt
-        if(signed >= 0):
+        if (signed >= 0):
             alu_result = 0
         else:
             alu_result = 1
@@ -38,11 +38,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01001':
         if a < 0:
-            ua = a+2**32
+            ua = a + 2**32
         else:
             ua = a
         if b < 0:
-            ub = b+2**32
+            ub = b + 2**32
         else:
             ub = b
         if ua < ub:
@@ -51,11 +51,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01010':
         if a < 0:
-            ua = a+2**32
+            ua = a + 2**32
         else:
             ua = a
         if b < 0:
-            ub = b+2**32
+            ub = b + 2**32
         else:
             ub = b
         if ua >= ub:
@@ -70,11 +70,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
         alu_result = a << b
     elif alu_ctrl == '01110':
         if a < 0:
-            ua = a+2**32
+            ua = a + 2**32
         else:
             ua = a
         if b < 0:
-            ub = b+2**32
+            ub = b + 2**32
         else:
             ub = b
         if ua <= ub:
@@ -83,7 +83,7 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01111':
         if a < 0:
-            ua = a+2**32
+            ua = a + 2**32
         else:
             ua = a
         alu_result = a >> b

code/alu_controller.py

@@ -1,48 +1,49 @@
-def alu_controller(alu_op,funct7,funct3):               #alu_op来自主控制器，funct7和funct3来自指令的特定部位   返回alu_ctrl
+def alu_controller(alu_op, funct7,
-    if alu_op=='00':
+                   funct3):  # alu_op来自主控制器，funct7和funct3来自指令的特定部位   返回alu_ctrl
-        opreation='00000'        #lw.sw.auipc
+    if alu_op == '00':
-    elif alu_op=='01':
+        opreation = '00000'  # lw.sw.auipc
-        if funct3=='000':
+    elif alu_op == '01':
-            opreation='00101'    #beq
+        if funct3 == '000':
-        elif funct3=='001':
+            opreation = '00101'  # beq
-            opreation='00110'    #bne
+        elif funct3 == '001':
-        elif funct3=='100':
+            opreation = '00110'  # bne
-            opreation='00111'    #blt
+        elif funct3 == '100':
-        elif funct3=='101':
+            opreation = '00111'  # blt
-            opreation='01000'    #bge
+        elif funct3 == '101':
-        elif funct3=='110':
+            opreation = '01000'  # bge
-            opreation='01001'    #bltu
+        elif funct3 == '110':
-        elif funct3=='111':
+            opreation = '01001'  # bltu
-            opreation='01010'    #bgeu
+        elif funct3 == '111':
+            opreation = '01010'  # bgeu
         else:
-            opreation='00000'
+            opreation = '00000'
-    elif alu_op=='10':
+    elif alu_op == '10':
-        if funct3=='000':
+        if funct3 == '000':
-            if funct7=='0100000':   #sub
+            if funct7 == '0100000':  # sub
-                opreation='00001'
+                opreation = '00001'
-            else:                   #add,addi
+            else:  # add,addi
-                opreation='00000'
+                opreation = '00000'
-        elif funct3=='100':
+        elif funct3 == '100':
-            opreation='01100'        #xor,xori
+            opreation = '01100'  # xor,xori
-        elif funct3=='110':
+        elif funct3 == '110':
-            opreation='00010'        #or,ori
+            opreation = '00010'  # or,ori
-        elif funct3=='111':
+        elif funct3 == '111':
-            opreation='00011'        #and, andi
+            opreation = '00011'  # and, andi
-        elif funct3=='010':
+        elif funct3 == '010':
-            opreation='00100'        #slt,slti
+            opreation = '00100'  # slt,slti
-        elif funct3=='001':
+        elif funct3 == '001':
-            opreation='01101'        #sll,slli   未存在
+            opreation = '01101'  # sll,slli   未存在
-        elif funct3=='011':
+        elif funct3 == '011':
-            opreation='01110'        #slti,sltiu 未存在
+            opreation = '01110'  # sliu,sltiu 未存在
-        elif funct3=='101':
+        elif funct3 == '101':
-            if funct7=='0100000':   #sra,srai
+            if funct7 == '0100000':  # sra,srai
-                opreation='01111'
+                opreation = '01111'
-            else:                   #srl,srli
+            else:  # srl,srli
-                opreation='10000'
+                opreation = '10000'
         else:
-            opreation='00000'
+            opreation = '00000'
-    elif alu_op=='11':              #jal
+    elif alu_op == '11':  # jal
-        opreation='01011'
+        opreation = '01011'
     else:
-        opreation='00000'
+        opreation = '00000'
     return opreation

code/branch_unit.py

@@ -1,9 +1,10 @@
-def branch_unit(cur_pc,imm,jalr_sel,branch_taken,alu_result):           #输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
+def branch_unit(cur_pc, imm, jalr_sel, branch_taken,
-    pc_plus_4=cur_pc+4                                                  #输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看)
+                alu_result):  # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
-    pc_plus_imm=cur_pc+imm
+    pc_plus_4 = cur_pc + 4  # 输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看)
-    pc_sel = jalr_sel | (branch_taken & (alu_result%2))
+    pc_plus_imm = cur_pc + imm
-    if jalr_sel=='1':
+    pc_sel = jalr_sel | (branch_taken & (alu_result % 2))
-        branch_target=alu_result&(2**32-2)
+    if jalr_sel == 1:
+        branch_target = alu_result & (2**32 - 2)
     else:
-        branch_target=cur_pc+imm*2
+        branch_target = cur_pc + imm * 2
-    return pc_plus_imm,pc_plus_4,branch_target,pc_sel
+    return pc_plus_imm, pc_plus_4, branch_target, pc_sel

code/data_mem.py

@@ -1,38 +1,49 @@
 from binandint import *
+
+
 class data_mem:
-    memory=[8*'0']*4*1024*16
+    memory = [8 * '0'] * 4 * 1024 * 16
 
     def __init__(self) -> None:
         pass
 
-    def mem(self,write_en,read_en,address,data_in,funct3):      #写使能，读使能，(使能为int的0或1)地址，输入数据，func3              #输出为data_out
+    def mem(self, write_en, read_en, address, data_in, funct3
+            ):  # 写使能，读使能，(使能为int的0或1)地址，输入数据，func3              #输出为data_out
         if write_en:
-            if funct3=='000':                   #sb
+            if funct3 == '000':  # sb
-                self.memory[address]=InttoBin(data_in%2**8, 8)
+                self.memory[address] = InttoBin(data_in % 2**8, 8)
-            elif funct3=='001':                 #sh
+            elif funct3 == '001':  # sh
-                temp=InttoBin(data_in%2**16, 16)
+                temp = InttoBin(data_in % 2**16, 16)
-                self.memory[address+1]=temp[0:8]
+                self.memory[address + 1] = temp[0:8]
-                self.memory[address]=temp[8:16]
+                self.memory[address] = temp[8:16]
-            elif funct3=='010':                 #sw
+            elif funct3 == '010':  # sw
-                temp=InttoBin(data_in, 32)
+                temp = InttoBin(data_in, 32)
-                self.memory[address+3]=temp[0:8]
+                self.memory[address + 3] = temp[0:8]
-                self.memory[address+2]=temp[8:16]
+                self.memory[address + 2] = temp[8:16]
-                self.memory[address+1]=temp[16:24]
+                self.memory[address + 1] = temp[16:24]
-                self.memory[address]=temp[24:32]
+                self.memory[address] = temp[24:32]
             else:
                 pass
 
         if read_en:
-            if funct3=='000':                   #lb
+            if funct3 == '000':  # lb
-                data_out=BintoInt(self.memory[address])
+                data_out = BintoInt(self.memory[address])
-            elif funct3=='001':                 #lh
+            elif funct3 == '001':  # lh
-                data_out=BintoInt(self.memory[address+1]+self.memory[address])
+                data_out = BintoInt(self.memory[address + 1] +
-            elif funct3=='010':                 #lw
+                                    self.memory[address])
-                data_out=BintoInt(self.memory[address+3]+self.memory[address+2]+self.memory[address+1]+self.memory[address])
+            elif funct3 == '010':  # lw
-            elif funct3=='100':                 #lbu
+                data_out = BintoInt(self.memory[address + 3] +
-                data_out=BintoUInt(self.memory[address+1]+self.memory[address])
+                                    self.memory[address + 2] +
-            elif funct3=='101':                 #lhu
+                                    self.memory[address + 1] +
-                data_out=BintoUInt(self.memory[address+3]+self.memory[address+2]+self.memory[address+1]+self.memory[address])
+                                    self.memory[address])
+            elif funct3 == '100':  # lbu
+                data_out = BintoUInt(self.memory[address + 1] +
+                                     self.memory[address])
+            elif funct3 == '101':  # lhu
+                data_out = BintoUInt(self.memory[address + 3] +
+                                     self.memory[address + 2] +
+                                     self.memory[address + 1] +
+                                     self.memory[address])
             else:
                 pass
         return data_out

code/datapath.py

@@ -13,50 +13,67 @@ from mux4 import *
 from proc_controller import *
 from reg_file import reg_file
 
-IM=insn_mem()
+IM = insn_mem()
-PC=0
+PC = 0
-def IF(BrPC,Brflush,stall,PC,IM):
+
-    PCplus4=adder(PC,4)
+
-    if Brflush=='1':
+def IF(BrPC, Brflush, stall, PC, IM):
-        nPC=BrPC
+    PCplus4 = adder(PC, 4)
+    if Brflush == '1':
+        nPC = BrPC
     else:
-        nPC=PC+4
+        nPC = PC + 4
-    insn=IM.fetch(nPC)
+    insn = IM.fetch(nPC)
-    return nPC,insn
+    return nPC, insn
-
+
-REG=reg_file()
+
-
+REG = reg_file()
-def ID(PC,insn,RegWrite,Brflush,stall,REG,WB_data):
+
-    funct7=insn[0:7]
+
-    rs2=BintoUInt(insn[7:12])
+def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
-    rs1=BintoUInt(insn[12:17])
+    funct7 = insn[0:7]
-    funct3=insn[17:20]
+    rs2 = BintoUInt(insn[7:12])
-    rd=BintoUInt(insn[20:25])
+    rs1 = BintoUInt(insn[12:17])
-    opcode=insn[25:32]
+    funct3 = insn[17:20]
-    ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel=proc_controller(opcode)
+    rd = BintoUInt(insn[20:25])
-    ImmG=Imm_gen(insn)
+    opcode = insn[25:32]
-    REG.write(RegWrite,rd,WB_data)
+    ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
-    RD1,RD2=REG.read(rs1,rs2)
+        opcode)
-    return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel,PC,RD1,RD2,ImmG,rs1,rs2,rd,funct3,funct7
+    ImmG = Imm_gen(insn)
-
+    REG.write(RegWrite, rd, WB_data)
-def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel,PC,RD1,RD2,ImmG,rs1,rs2,rd,funct3,funct7,lastrs1,lastrs2,forwardA,forwardB,WB_data,alu_out):
+    RD1, RD2 = REG.read(rs1, rs2)
-    stall=hazard_detector(lastrs1,lastrs2,rd,MemRead)
+    return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7
-    tempA=mux4(RD1,alu_out,WB_data,0,forwardA)
+
-    tempB=mux4(RD2,alu_out,WB_data,0,forwardB)
+
-    tempB2=mux(tempB,ImmG,ALUSrc)
+def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
-    alu_ctrl=alu_controller(ALUOp,funct7,funct3)
+       RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7, lastrs1,
-    ALU_result=alu(tempA, tempB2, alu_ctrl)
+       lastrs2, forwardA, forwardB, WB_data, alu_out):
-    pc_plus_imm,pc_plus_4,branch_target,pc_sel=branch_unit(PC,ImmG,JalrSel,Branch,ALU_result)
+    stall = hazard_detector(lastrs1, lastrs2, rd, MemRead)
-    return MemtoReg, RegWrite,MemWrite,RWSel,MemRead,pc_plus_imm,pc_plus_4,branch_target,pc_sel,ALU_result,rs1,rs2,rd,tempA,tempB,funct3,funct7
+    tempA = mux4(RD1, alu_out, WB_data, 0, forwardA)
-
+    tempB = mux4(RD2, alu_out, WB_data, 0, forwardB)
-MEMORY=data_mem()
+    tempB2 = mux(tempB, ImmG, ALUSrc)
-
+    alu_ctrl = alu_controller(ALUOp, funct7, funct3)
-def MEM(MEMORY,MemtoReg, RegWrite,MemWrite,RWSel,MemRead,pc_plus_imm,pc_plus_4,ALU_result,rs1,rs2,rd,tempA,tempB,funct3,funct7):
+    ALU_result = alu(tempA, tempB2, alu_ctrl)
-    data_out=MEMORY(MemWrite,MemRead,ALU_result,tempB,funct3)
+    pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
-    return MemtoReg, RegWrite,RWSel,pc_plus_imm,pc_plus_4,data_out,tempB,rd
+        PC, ImmG, JalrSel, Branch, ALU_result)
-
+    return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7
-def WB(MemtoReg, RegWrite,RWSel,pc_plus_imm,pc_plus_4,data_out,tempB,ex_mem_rd,mem_wb_rd,ex_mem_rs1,ex_mem_rs2,ex_mem_regwrite,mem_wb_regwrite):
+
-    mem_out=mux(data_out,tempB,MemtoReg)
+
-    WB_data=mux4(mem_out,pc_plus_4,pc_plus_imm,0,RWSel)
+MEMORY = data_mem()
-    forward_a,forward_b= fowardingunit(ex_mem_rs1,ex_mem_rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite)
+
-    return WB_data,RegWrite,forward_a,forward_b
+
+def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
+        pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
+    data_out = MEMORY(MemWrite, MemRead, ALU_result, tempB, funct3)
+    return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd
+
+
+def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
+       ex_mem_rd, mem_wb_rd, ex_mem_rs1, ex_mem_rs2, ex_mem_regwrite,
+       mem_wb_regwrite):
+    mem_out = mux(data_out, tempB, MemtoReg)
+    WB_data = mux4(mem_out, pc_plus_4, pc_plus_imm, 0, RWSel)
+    forward_a, forward_b = fowardingunit(ex_mem_rs1, ex_mem_rs2, ex_mem_rd,
+                                         mem_wb_rd, ex_mem_regwrite,
+                                         mem_wb_regwrite)
+    return WB_data, RegWrite, forward_a, forward_b

code/forwarding_unit.py

@@ -1,14 +1,15 @@
-def fowardingunit(rs1,rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite):
+def fowardingunit(rs1, rs2, ex_mem_rd, mem_wb_rd, ex_mem_regwrite,
-    if rs1!=0 and rs1==ex_mem_rd and ex_mem_regwrite:
+                  mem_wb_regwrite):
-        forward_a='01'
+    if rs1 != 0 and rs1 == ex_mem_rd and ex_mem_regwrite:
-    elif rs1!=0 and rs1==mem_wb_rd and mem_wb_regwrite:
+        forward_a = '01'
-        forward_a='10'
+    elif rs1 != 0 and rs1 == mem_wb_rd and mem_wb_regwrite:
+        forward_a = '10'
     else:
-        forward_a='00'
+        forward_a = '00'
-    if rs2!=0 and rs2==ex_mem_rd and ex_mem_regwrite:
+    if rs2 != 0 and rs2 == ex_mem_rd and ex_mem_regwrite:
-        forward_b='01'
+        forward_b = '01'
-    elif rs2!=0 and rs2==mem_wb_rd and mem_wb_regwrite:
+    elif rs2 != 0 and rs2 == mem_wb_rd and mem_wb_regwrite:
-        forward_b='10'
+        forward_b = '10'
     else:
-        forward_b='00'
+        forward_b = '00'
-    return forward_a,forward_b
+    return forward_a, forward_b

code/hazard_detector.py

@@ -1,6 +1,6 @@
-def hazard_detector(if_id_rs1,if_id_rs2,id_ex_rd,id_ex_memread):
+def hazard_detector(if_id_rs1, if_id_rs2, id_ex_rd, id_ex_memread):
-    if id_ex_memread and (id_ex_rd==if_id_rs1 or id_ex_rd==if_id_rs2):
+    if id_ex_memread and (id_ex_rd == if_id_rs1 or id_ex_rd == if_id_rs2):
-        stall='1'
+        stall = '1'
     else:
-        stall='0'
+        stall = '0'
     return stall