imm_gen and formatted

code/Imm_gen.py

@@ -1,17 +1,15 @@
-def Imm_gen(inst_code):
+def Imm_gen(inst_code: str) -> str:
     test = inst_code[25:32]
-    if test == '0010011':
-        imm_out = 20*inst_code[0]+inst_code[0:12]
-    elif test == '0000011':
-        pass
-    elif test == '0100011':
-        pass
-    elif test == '1100011':
-        pass
-    elif test == '1101111':
-        pass
-    elif test == '1100111':
-        pass
-    elif test == '0110111':
-        pass
+    if test in ['0010011', '0000011', '1100111']:  # i-Type, l, jalr
+        imm_out = inst_code[0:12].rjust(32, inst_code[0])
+    elif test == '0100011':  # s
+        imm_out = (inst_code[0:7] + inst_code[20:25]).rjust(32, inst_code[0])
+    elif test == '1100011':  # branch
+        imm_out = (inst_code[0] + inst_code[24] + inst_code[1:7] +
+                   inst_code[20:24]).rjust(32, inst_code[0])
+    elif test == '1101111':  # jal
+        imm_out = (inst_code[0] + inst_code[12:20] + inst_code[11] +
+                   inst_code[1:11]).rjust(32, inst_code[0])
+    elif test in ['0110111', '0010111']:  # lui, auipc
+        imm_out = inst_code[0:20].rjust(32, inst_code[0])
     return imm_out

code/alu_controller.py

@@ -1,4 +1,5 @@
-def alu_controller(alu_op,funct7,funct3):               #alu_op来自主控制器，funct7和funct3来自指令的特定部位   返回alu_ctrl
+def alu_controller(alu_op, funct7,
+                   funct3):  # alu_op来自主控制器，funct7和funct3来自指令的特定部位   返回alu_ctrl
     if alu_op == '00':
         opreation = '00000'  # lw.sw.auipc
     elif alu_op == '01':
@@ -33,7 +34,7 @@ def alu_controller(alu_op,funct7,funct3):               #alu_op来自主控制
         elif funct3 == '001':
             opreation = '01101'  # sll,slli   未存在
         elif funct3 == '011':
-            opreation='01110'        #slti,sltiu 未存在
+            opreation = '01110'  # sliu,sltiu 未存在
         elif funct3 == '101':
             if funct7 == '0100000':  # sra,srai
                 opreation = '01111'

code/branch_unit.py

@@ -1,8 +1,9 @@
-def branch_unit(cur_pc,imm,jalr_sel,branch_taken,alu_result):           #输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
+def branch_unit(cur_pc, imm, jalr_sel, branch_taken,
+                alu_result):  # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
     pc_plus_4 = cur_pc + 4  # 输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看)
     pc_plus_imm = cur_pc + imm
     pc_sel = jalr_sel | (branch_taken & (alu_result % 2))
-    if jalr_sel=='1':
+    if jalr_sel == 1:
         branch_target = alu_result & (2**32 - 2)
     else:
         branch_target = cur_pc + imm * 2

code/data_mem.py

@@ -1,11 +1,14 @@
 from binandint import *
+
+
 class data_mem:
     memory = [8 * '0'] * 4 * 1024 * 16
 
     def __init__(self) -> None:
         pass
 
-    def mem(self,write_en,read_en,address,data_in,funct3):      #写使能，读使能，(使能为int的0或1)地址，输入数据，func3              #输出为data_out
+    def mem(self, write_en, read_en, address, data_in, funct3
+            ):  # 写使能，读使能，(使能为int的0或1)地址，输入数据，func3              #输出为data_out
         if write_en:
             if funct3 == '000':  # sb
                 self.memory[address] = InttoBin(data_in % 2**8, 8)
@@ -26,13 +29,21 @@ class data_mem:
             if funct3 == '000':  # lb
                 data_out = BintoInt(self.memory[address])
             elif funct3 == '001':  # lh
-                data_out=BintoInt(self.memory[address+1]+self.memory[address])
+                data_out = BintoInt(self.memory[address + 1] +
+                                    self.memory[address])
             elif funct3 == '010':  # lw
-                data_out=BintoInt(self.memory[address+3]+self.memory[address+2]+self.memory[address+1]+self.memory[address])
+                data_out = BintoInt(self.memory[address + 3] +
+                                    self.memory[address + 2] +
+                                    self.memory[address + 1] +
+                                    self.memory[address])
             elif funct3 == '100':  # lbu
-                data_out=BintoUInt(self.memory[address+1]+self.memory[address])
+                data_out = BintoUInt(self.memory[address + 1] +
+                                     self.memory[address])
             elif funct3 == '101':  # lhu
-                data_out=BintoUInt(self.memory[address+3]+self.memory[address+2]+self.memory[address+1]+self.memory[address])
+                data_out = BintoUInt(self.memory[address + 3] +
+                                     self.memory[address + 2] +
+                                     self.memory[address + 1] +
+                                     self.memory[address])
             else:
                 pass
         return data_out

code/datapath.py

@@ -15,6 +15,8 @@ from reg_file import reg_file
 
 IM = insn_mem()
 PC = 0
+
+
 def IF(BrPC, Brflush, stall, PC, IM):
     PCplus4 = adder(PC, 4)
     if Brflush == '1':
@@ -24,8 +26,10 @@ def IF(BrPC,Brflush,stall,PC,IM):
     insn = IM.fetch(nPC)
     return nPC, insn
 
+
 REG = reg_file()
 
+
 def ID(PC, insn, RegWrite, Brflush, stall, REG, WB_data):
     funct7 = insn[0:7]
     rs2 = BintoUInt(insn[7:12])
@@ -33,30 +37,43 @@ def ID(PC,insn,RegWrite,Brflush,stall,REG,WB_data):
     funct3 = insn[17:20]
     rd = BintoUInt(insn[20:25])
     opcode = insn[25:32]
-    ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel=proc_controller(opcode)
+    ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = proc_controller(
+        opcode)
     ImmG = Imm_gen(insn)
     REG.write(RegWrite, rd, WB_data)
     RD1, RD2 = REG.read(rs1, rs2)
     return ALUSrc, MemtoReg, RegWritex, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7
 
-def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel,PC,RD1,RD2,ImmG,rs1,rs2,rd,funct3,funct7,lastrs1,lastrs2,forwardA,forwardB,WB_data,alu_out):
+
+def EX(ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel,
+       RWSel, PC, RD1, RD2, ImmG, rs1, rs2, rd, funct3, funct7, lastrs1,
+       lastrs2, forwardA, forwardB, WB_data, alu_out):
     stall = hazard_detector(lastrs1, lastrs2, rd, MemRead)
     tempA = mux4(RD1, alu_out, WB_data, 0, forwardA)
     tempB = mux4(RD2, alu_out, WB_data, 0, forwardB)
     tempB2 = mux(tempB, ImmG, ALUSrc)
     alu_ctrl = alu_controller(ALUOp, funct7, funct3)
     ALU_result = alu(tempA, tempB2, alu_ctrl)
-    pc_plus_imm,pc_plus_4,branch_target,pc_sel=branch_unit(PC,ImmG,JalrSel,Branch,ALU_result)
+    pc_plus_imm, pc_plus_4, branch_target, pc_sel = branch_unit(
+        PC, ImmG, JalrSel, Branch, ALU_result)
     return MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm, pc_plus_4, branch_target, pc_sel, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7
 
+
 MEMORY = data_mem()
 
-def MEM(MEMORY,MemtoReg, RegWrite,MemWrite,RWSel,MemRead,pc_plus_imm,pc_plus_4,ALU_result,rs1,rs2,rd,tempA,tempB,funct3,funct7):
+
+def MEM(MEMORY, MemtoReg, RegWrite, MemWrite, RWSel, MemRead, pc_plus_imm,
+        pc_plus_4, ALU_result, rs1, rs2, rd, tempA, tempB, funct3, funct7):
     data_out = MEMORY(MemWrite, MemRead, ALU_result, tempB, funct3)
     return MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB, rd
 
-def WB(MemtoReg, RegWrite,RWSel,pc_plus_imm,pc_plus_4,data_out,tempB,ex_mem_rd,mem_wb_rd,ex_mem_rs1,ex_mem_rs2,ex_mem_regwrite,mem_wb_regwrite):
+
+def WB(MemtoReg, RegWrite, RWSel, pc_plus_imm, pc_plus_4, data_out, tempB,
+       ex_mem_rd, mem_wb_rd, ex_mem_rs1, ex_mem_rs2, ex_mem_regwrite,
+       mem_wb_regwrite):
     mem_out = mux(data_out, tempB, MemtoReg)
     WB_data = mux4(mem_out, pc_plus_4, pc_plus_imm, 0, RWSel)
-    forward_a,forward_b= fowardingunit(ex_mem_rs1,ex_mem_rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite)
+    forward_a, forward_b = fowardingunit(ex_mem_rs1, ex_mem_rs2, ex_mem_rd,
+                                         mem_wb_rd, ex_mem_regwrite,
+                                         mem_wb_regwrite)
     return WB_data, RegWrite, forward_a, forward_b

code/forwarding_unit.py

@@ -1,4 +1,5 @@
-def fowardingunit(rs1,rs2,ex_mem_rd,mem_wb_rd,ex_mem_regwrite,mem_wb_regwrite):
+def fowardingunit(rs1, rs2, ex_mem_rd, mem_wb_rd, ex_mem_regwrite,
+                  mem_wb_regwrite):
     if rs1 != 0 and rs1 == ex_mem_rd and ex_mem_regwrite:
         forward_a = '01'
     elif rs1 != 0 and rs1 == mem_wb_rd and mem_wb_regwrite: